CN210742772U

CN210742772U - Stable current generating circuit

Info

Publication number: CN210742772U
Application number: CN201922420672.9U
Authority: CN
Inventors: 陈强; 张艳波; 姚罗燕
Original assignee: Ant Suzhou Semiconductor Co Ltd
Current assignee: Ant Suzhou Semiconductor Co Ltd
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-06-12
Anticipated expiration: 2029-12-27

Abstract

The utility model provides a stable current produces circuit. The stable current generating circuit comprises a main circuit, a current adjusting circuit and an output circuit; the main circuit is used for generating driving current, the current adjusting circuit is connected with the main circuit and used for acquiring the driving current, comparing the acquired current with a reference current and outputting a comparison result to the output circuit, and the output circuit is connected with the current adjusting circuit and used for outputting stable driving current Iout according to the comparison result, so that stable output of the current generating circuit is realized, and abnormal work of the LED caused by over-small output current is avoided.

Description

Stable current generating circuit

Technical Field

The utility model relates to an analog integrated circuit design field specifically relates to a stabilization current produces circuit.

Background

The LED has more and more extensive applications due to its outstanding advantages, and the LED driving current has a critical influence on the performance of the LED, so that the demand of people on the LED driving current circuit is higher and higher. In the prior art, the resistance units in the circuits are usually adjusted to obtain driving circuits with different requirements, so as to meet the needs of different users.

However, due to factors such as the production process of the resistor, the environment and the like, the resistance value inevitably fluctuates around a standard value, for example, the resistance value of the resistor changes with the change of temperature, and the LED generates a certain amount of heat during operation, so that the resistance value of the resistor changes, when the resistance value of the resistor is too large, the output current may become small, and when the resistance value of the resistor is too small, the LED may operate abnormally, or even the LED may not operate, so that the overall lighting effect is affected. Therefore, how to design a circuit with good stability and still capable of stably driving the driving current of the LED when the internal resistance of the circuit is too large due to abnormal conditions is a crucial difficult problem in circuit design.

SUMMERY OF THE UTILITY MODEL

To the not enough of above-mentioned prior art, the utility model aims to: the circuit can solve the problems that the output of the existing LED driving current circuit is not stable enough and is greatly influenced by resistance value.

In order to achieve the above object, the present invention provides the following technical solutions:

a stable current generating circuit comprises a main circuit, a current adjusting circuit and an output circuit; the main circuit is used for generating a driving current I0, the current adjusting circuit is connected with the main circuit and used for collecting the driving current I0, comparing the collected current I6 with a reference current I1 and outputting a comparison result to the output circuit, and the output circuit is connected with the current adjusting circuit and used for outputting a stable driving current Iout according to the comparison result, so that stable output of the current generating circuit is achieved.

Wherein, the main circuit includes: an operational amplifier P1, resistors R1 and R2, a transistor MN1 and an MP 1; the non-inverting input end of the operational amplifier P1 is connected with a reference voltage Vref, the inverting input end is connected with the common end of the resistors R1 and R2, the other end of the resistor R2 is grounded, the other end of the resistor R1 is connected with the source of the transistor MN1, the gate of the transistor MN1 is connected with the output end of the operational amplifier P1, the drain of the transistor MN1 is connected with the drain and the gate of the transistor MP1, and the source of the transistor MP1 is connected with the power supply voltage VDD.

The current regulation circuit includes: transistors MP2-MP6, MN2, MN3, current source I. The transistor MP2 and the transistor MP1 form a mirror circuit for mirroring the driving circuit I0; the transistors MN2 and MN3 form a mirror circuit; the source of the transistor MP2 is connected with a power supply voltage VDD, the gate is connected with the gate of the transistor MP1, the drain is connected with the drain of the transistor MN2, the drain of the transistor MN2 is connected with the gate of the transistor MN2 and the gate of the transistor MN3, and the sources of the transistors MN2 and MN3 are grounded; the drain of the transistor MN3 is connected with one end of the current source I and the drain of the transistor MP 4; the other end of the current source I is connected with the drain and the gate of the transistor MP3, the gate of the transistor MP3 is connected with the gate of the transistor MP6, and the sources of the transistors MP3-MP6 are connected with the power supply voltage VDD; the gate of the transistor MP4 is connected to the drain thereof and the gate of the transistor MP5, and the drain of the transistor MP5 is connected to the drain of the transistor MP 6.

The output circuit comprises transistors MN4 and MN5, wherein the transistors MN4 and MN5 form a current mirror circuit, are used for mirroring the current I5 and serve as an output current Iout; the drain of the transistor MN4 is connected to the gate thereof and the drain of the transistor MP6, the gate of the transistor MN4 is connected to the gate of the transistor MN5, and the sources of the transistors MN4 and MN5 are grounded.

The transistors MP1-MP6 are PMOS transistors, and the transistors MN1-MN5 are NMOS transistors.

Advantageous effects

The utility model provides a pair of stable current produces circuit can export stable electric current, compares with prior art and has following beneficial effect:

1. the circuit has a feedback structure, can realize self-adaptive stable regulation, and enables the circuit to output stable current.

2. When the influence because resistance leads to output current too little, the utility model discloses the circuit passes through current adjustment circuit's collection, contrast, adjustment to realize output current's stability, guarantee LED's normal work.

3. The circuit structure of the circuit is simple, the circuit can work under lower power supply voltage, the leakage current is small, and the signal to noise ratio is higher.

Drawings

Fig. 1 is a circuit diagram of a stable current generation circuit according to an embodiment of the present invention;

Detailed Description

The following description will further describe embodiments of the present invention with reference to the accompanying drawings and examples. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

As shown in fig. 1, a stable current generating circuit includes a main circuit, a current adjusting circuit and an output circuit; the main circuit is used for generating a driving current I0, the current adjusting circuit is connected with the main circuit and used for collecting the driving current I0, comparing the collected current I6 with a reference current I1 and outputting a comparison result to the output circuit, and the output circuit is connected with the current adjusting circuit and used for outputting a stable driving current Iout according to the comparison result, so that stable output of the current generating circuit is achieved.

Wherein, the main circuit includes: an operational amplifier P1, a resistor R1, a resistor R2, a transistor MN1 and a transistor MP 1; the non-inverting input end of the operational amplifier P1 is connected with a reference voltage Vref, the inverting input end is connected with the common end of the resistor R1 and the resistor R2, the other end of the resistor R2 is grounded, the other end of the resistor R1 is connected with the source of the transistor MN1, the gate of the transistor MN1 is connected with the output end of the operational amplifier P1, the drain of the transistor MN1 is connected with the drain and the gate of the transistor MP1, and the source of the transistor MP1 is connected with the power supply voltage VDD.

The current regulation circuit includes: transistors MP2-MP6, MN2, MN3, current source I. The transistor MP2 and the transistor MP1 form a mirror circuit for mirroring the driving circuit I0; the transistors MN2 and MN3 form a mirror circuit; the source of the transistor MP2 is connected with a power supply voltage VDD, the gate is connected with the gate of the transistor MP1, the drain is connected with the drain of the transistor MN2, the drain of the transistor MN2 is connected with the gate of the transistor MN2 and the gate of the transistor MN3, and the sources of the transistors MN2 and MN3 are grounded; the drain of the transistor MN3 is connected with one end of the current source I and the drain of the transistor MP 4; the current source I generates a current I1, the other end of the current source I is connected with the drain and the gate of the transistor MP3, the gate of the transistor MP3 is connected with the gate of the transistor MP6, and the sources of the transistors MP3-MP6 are connected with a power supply voltage VDD; the gate of the transistor MP4 is connected to the drain thereof and the gate of the transistor MP5, and the drain of the transistor MP5 is connected to the drain of the transistor MP 6.

The output circuit comprises transistors MN4 and MN5, wherein the transistors MN4 and MN5 form a current mirror circuit for mirroring the current I5 and making an output current Iout; the drain of the transistor MN4 is connected to the gate thereof and the drain of the transistor MP6, the gate of the transistor MN4 is connected to the gate of the transistor MN5, and the sources of the transistors MN4 and MN5 are grounded.

In the present embodiment, the ratio of each current mirror is 1:1, but it is known to those skilled in the art that the ratio may be set to other values according to actual needs, and the ratio is not limited herein. Since the transistors MP1 and MP2 form a cascode current mirror, the current I6 becomes I0, and since the transistors MN2 and MN3 also form a cascode current mirror, the current I2 is: I2-I6-I1-I0-I1; when I0> I1, the above formula holds, and when I0< I1, the transistors MP4 and MP5 are in an off state, and when I2 is 0.

Since the transistors MP4 and MP5 also constitute a current mirror circuit, I3 is I2; i5 ═ I3+ I4; since the transistors MP6 and MP3 form a current mirror structure, I4 is I1; i5 ═ I2+ I1; thus, when I0> I1, I5 ═ I0; i5 ═ I1 when I0< I1. The output current has an Iout of I5 due to mirror structures of the transistor MN4 and the transistor MN 5. Therefore, the structure realizes that the value of I0 is directly output when the output current I0 is larger than a reference current I1, and the value is output at the reference current I1 when the output current is smaller than the reference current I1. The reference value I1 is determined according to the minimum current required for proper operation of the LED in actual operation.

In the above embodiments, the transistors MP1, MP2, MP3, MP4, MP5, and MP6 are all described as transistors MP1-MP 6. The transistor MN1 is composed of a transistor MN2, a transistor MN3, a transistor MN4 and a transistor MN5, which are all described as being abbreviated as transistors MN1-MN 5.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.

Claims

1. A stable current generating circuit is characterized by comprising a main circuit, a current adjusting circuit and an output circuit; the main circuit is used for generating a driving current I0, the current adjusting circuit is connected with the main circuit and used for collecting the driving current I0, comparing the collected current I6 with a reference current and outputting a comparison result to the output circuit, and the output circuit is connected with the current adjusting circuit and used for outputting a stable driving current Iout according to the comparison result, so that stable output of the current generating circuit is realized;

wherein, the main circuit includes: an operational amplifier P1, resistors R1 and R2, a transistor MN1 and an MP 1; the positive phase input end of the operational amplifier P1 is connected with a reference voltage Vref, the negative phase input end is connected with the common end of the resistors R1 and R2, the other end of the resistor R2 is grounded, the other end of the resistor R1 is connected with the source of the transistor MN1, the gate of the transistor MN1 is connected with the output end of the operational amplifier P1, the drain of the transistor MN1 is connected with the drain and the gate of the transistor MP1, and the source of the transistor MP1 is connected with a power supply voltage VDD;

the current regulation circuit includes: transistors MP2-MP6, MN2, MN3, current source I; the transistor MP2 and the transistor MP1 form a mirror circuit for mirroring the driving circuit I0; the transistors MN2 and MN3 form a mirror circuit; the source of the transistor MP2 is connected with a power supply voltage VDD, the gate is connected with the gate of the transistor MP1, the drain is connected with the drain of the transistor MN2, the drain of the transistor MN2 is connected with the gate of the transistor MN2 and the gate of the transistor MN3, and the sources of the transistors MN2 and MN3 are grounded; the drain of the transistor MN3 is connected with one end of the current source I and the drain of the transistor MP 4; the other end of the current source I is connected with the drain and the gate of the transistor MP3, the gate of the transistor MP3 is connected with the gate of the transistor MP6, and the sources of the transistors MP3-MP6 are connected with the power supply voltage VDD; the gate of the transistor MP4 is connected to the drain thereof and the gate of the transistor MP5, and the drain of the transistor MP5 is connected to the drain of the transistor MP 6.

2. The stabilized current generating circuit according to claim 1, wherein the output circuit comprises transistors MN4, MN5, wherein the transistors MN4, MN5 constitute a current mirror circuit for mirroring the current I5 as the output current Iout; the drain of the transistor MN4 is connected to the gate thereof and the drain of the transistor MP6, the gate of the transistor MN4 is connected to the gate of the transistor MN5, and the sources of the transistors MN4 and MN5 are grounded.

3. The stabilized current generating circuit according to claim 1 or 2, wherein the transistors MP1-MP6 are PMOS transistors and the transistors MN1-MN5 are NMOS transistors.