CN210670006U - Adjustable pulse generating circuit - Google Patents
Adjustable pulse generating circuit Download PDFInfo
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- CN210670006U CN210670006U CN201921102933.6U CN201921102933U CN210670006U CN 210670006 U CN210670006 U CN 210670006U CN 201921102933 U CN201921102933 U CN 201921102933U CN 210670006 U CN210670006 U CN 210670006U
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Abstract
The utility model discloses an adjustable pulse generating circuit, the utility model discloses a RC charge-discharge circuit is constituteed through digit adjustable resistance U1 and electric capacity C1 to cooperate software programming SPI digital interface, input control command adjusts the resistance of digit adjustable resistance, adjusts the output frequency PWM _ OUT of this circuit with this; the on-off of the periodic pulse output PWM _ OUT is realized by matching the triode TR with the reverser U1A, the power consumption of the circuit is reduced, and the cost is reduced by building an oscillation circuit through discrete components.
Description
Technical Field
The utility model belongs to the technical field of the electronic technology and specifically relates to a pulse generating circuit with adjustable.
Background
The periodic frequency generating circuit has wide application in circuits of various scales. The periodic pulse circuit in the prior art can be realized by two ways; the first method comprises the following steps: the method is realized by combining the crystal oscillator with devices (such as MCU, DSP, FPGA and the like) integrated with PLL, specifically, a periodic pulse output with high precision and stability is generated after an analog periodic frequency signal of a crystal oscillator circuit is processed by the PLL.
For a small-scale space limited circuit, another method is to build an oscillation circuit through discrete components to realize the output of periodic pulses, but the pulse frequency consistency of the output of the circuit is not good enough, and when in batch production, the output frequencies of various products are different, and the convergence of the frequency consistency cannot be realized through dynamic adjustment; for a circuit sensitive to power consumption, when the circuit is not used, the oscillation of the oscillation circuit cannot be stopped well, and in order to solve the problem, most methods implement switching of pulse output by cutting off a transmission path of periodic pulses, but the oscillation circuit still works, and the power consumption is not reduced effectively.
SUMMERY OF THE UTILITY MODEL
The present invention aims at solving at least one of the technical problems in the related art to a certain extent. Therefore, the utility model discloses an aim at provides an adjustable pulse generation circuit, and the frequency can be adjusted dynamically, but periodic pulse output switch control, and builds oscillating circuit through discrete components and parts, and the cost is lower.
The utility model adopts the technical proposal that:
the embodiment of the utility model provides an adjustable pulse generating circuit, which comprises a charging and discharging circuit, a switch control circuit, a digital interface and a signal output end;
one end of the charge-discharge circuit is connected with the digital interface through a triode, the other end of the charge-discharge circuit is connected with the signal output end, and the charge-discharge circuit is used for adjusting the output frequency;
one end of the switch control circuit is connected with the digital interface through a triode, the other end of the switch control circuit is connected with the signal output end, and the switch control circuit is used for adjusting the output on-off.
Furthermore, the charge and discharge circuit comprises a digital adjustable resistor and a first capacitor, wherein a PRA pin of the digital adjustable resistor is connected with one end of the first capacitor, and the other end of the first capacitor is connected with a signal output end.
Further, the switch control circuit comprises a digital interface, a triode, a second resistor, a first phase inverter and a second phase inverter, wherein one end of the second resistor is connected with the base electrode of the triode, the other end of the second resistor is connected with the digital interface, the collector electrode of the triode is connected with the input end of the first phase inverter, the emitter electrode of the triode is grounded, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the signal output end.
Further, a PRW pin of the digital adjustable resistor is connected between the first inverter and the second inverter.
Further, the digital adjustable resistor comprises a control chip and a second capacitor, the second capacitor is connected between a GND pin and a VCC pin of the control chip, and the second capacitor is connected with a power supply.
The diode is further included, the anode of the diode is connected with one end of the first capacitor through the first resistor, and the cathode of the diode is connected with the power supply.
The utility model has the advantages that: the utility model adopts the digital adjustable resistor U1 and the first capacitor C1 to form an RC charge-discharge circuit, and cooperates with a software programming SPI digital interface to input a control command to adjust the resistance value of the digital adjustable resistor, so as to adjust the output frequency PWM _ OUT of the circuit; because the output frequency of the circuit can be adjusted, the consistency correction can be carried out on the output frequency at the rear end of the output, and the consistency can reach a certain convergence effect by adjusting the output frequency; the on-off of periodic pulse output is realized through the cooperation of the triode and the first reverser, the power consumption of the circuit is reduced, and the circuit cost is reduced by building the oscillation circuit through discrete components.
Drawings
Fig. 1 is a circuit schematic diagram of an embodiment of the present invention;
fig. 2 is a schematic diagram of a waveform of an embodiment of the present invention during operation.
Reference numerals
The circuit comprises an EN CTL-digital interface, a PWM OUT-signal output end, a U1A-first inverter, a U2B-second inverter, a U1-digital adjustable resistor, a R1-first resistor, a R2-second resistor, a D2-diode, a C1-first capacitor, a C2-second capacitor and a TR-triode.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Example (b):
referring to fig. 1, fig. 1 is a diagram of an adjustable pulse generating circuit capable of implementing the adjusting method according to the embodiment, which includes a charging/discharging circuit and a switch control circuit, wherein one end of the charging/discharging circuit is connected to a digital interface through a triode, and the other end of the charging/discharging circuit is connected to a signal output end; specifically, the charging and discharging circuit includes a digital adjustable resistor U1 and a first capacitor C1, a PRA pin of the digital adjustable resistor is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the signal output terminal PWM _ OUT.
In a specific embodiment, the charging and discharging circuit is composed of a digital adjustable resistor U1 and a first capacitor C1; because the charging and discharging time of the RC is in direct proportion to the value of R & ltC & gt, the first capacitor C1 in the circuit has a fixed capacitance value, and the resistance value of the digital adjustable resistor can be adjusted by inputting a control command through a software programming SPI digital interface; so as to adjust the output frequency PWM _ OUT of the signal output end of the circuit; when the resistance value of the digital adjustable resistor U1 is increased, the charging and discharging time of the first capacitor C1 is prolonged; the period of the output frequency PWM _ OUT of the signal output end is lengthened; on the contrary, when the resistance of the digital adjustable resistor U1 becomes smaller, the charging and discharging time of the capacitor becomes shorter, and the output frequency PWM _ TOU period of the signal output end becomes shorter, so that the adjustment of the output frequency is achieved.
A circuit schematic diagram of an output controllable frequency adjustable pulse generating circuit is given in fig. 1. Where V1 and V3 are the input and output, respectively, of the second inverter U2B, and thus the waveforms of V1 and V3 are inverted. When the V1 is high, and the V3 is low, the output current of the first inverter U1A charges the capacitor C1 through the resistor digital adjustable resistor U1; when the voltage V1 is low and the voltage V3 is high, the capacitor C1 discharges the output of the first inverter U1A through the digital adjustable resistor U1;
one end of the switch control circuit is connected with the digital interface EN _ CTL, and the other end of the switch control circuit is connected with the signal output end PWM _ OUT. Specifically, the switch control circuit includes digital interface EN _ CTL, triode TR, second resistance R2, first inverter U1A, second inverter U2B, second resistance R2 one end is connected to triode TR's base, digital interface is connected to the second resistance R2 other end, first inverter U1A's input is connected to triode TR's collecting electrode, triode TR's emitter ground, the input of second inverter U2B is connected to first inverter U1A's output, signal output is connected to second inverter U2B's output. Wherein, the value of the second resistor R2 is 2K omega.
In a specific embodiment, when the control signal of the digital interface EN _ CTL is at a logic high level, the transistor TR is turned on; the input of the first inverter U1A is grounded through the conducting transistor TR; the output of the first inverter U1A is always high, and the output of the second inverter U2B is always low; the original periodic pulse output PWM _ OUT is turned off. When the control signal EN _ CTL of the digital interface is a logic low level, the triode TR is in a cut-off state; the first capacitor C1 resumes the above charging and discharging process, and the whole circuit resumes the periodic pulse output, so as to achieve the adjustment of the output switch control.
The PRW pin of the digitally adjustable resistor is connected between the first inverter U1A and the second inverter U2B.
The digital adjustable resistor U1 comprises a control chip and a second capacitor C2, wherein the second capacitor C2 is connected between a GND pin and a VCC pin of the control chip, the second capacitor C2 is connected with a power supply, the power supply is +5V, and the value of the second capacitor is 0.1 muF.
Preferably, the model of the control chip is MCP 41010-I/SN.
The diode D2 is further included, the anode of the diode D2 is connected with one end of the first capacitor through the first resistor R1, and the cathode of the diode D2 is connected with the power supply. The power supply is +5V, and the value of the first resistor is 100K omega. The first resistor R1 can effectively reduce the overshoot voltage at the input end of the first inverter U1A;
referring to fig. 2, fig. 2 is a schematic waveform diagram of the circuit during operation, and the charging and discharging processes in the first embodiment are specifically described in conjunction with the schematic waveform diagram.
And (3) charging process: specifically, as shown in the waveform B of the time period from T1 to T2 in the charging and discharging process of the first capacitor C1 in fig. 2, when V1 is high and V3 is low, the output current of the first inverter U1A charges the first capacitor C1 through the digital adjustable resistor U1; the voltage of V2 gradually rises; when the V2 voltage rises to the high threshold voltage Vth of the input voltage of the first inverter U1A, the output of the first inverter U1A flips to low while the output V3 of the second inverter U2B flips to high; since the voltage across the first capacitor C1 (V2-V3) cannot change suddenly and V2 (i.e. the voltage of the capacitor to ground) is always the voltage across the first capacitor C1 superimposed with the voltage of V3, when the voltage of V3 is inverted from low level to high level, the voltage of V2 also changes suddenly, specifically, the voltage of V2 changes suddenly from voltage + V3 (low level) across the first capacitor C1 to voltage + V3 (high level) across the first capacitor C1, and then the first capacitor C1 turns to the discharging process.
And (3) discharging: specifically, see the waveform B of the time period T2-T3 in the charging and discharging process waveform of the first capacitor C1 in fig. 2. When the voltage V1 is low and the voltage V3 is high, the first capacitor C1 discharges the output of the first inverter U1A through the digital adjustable resistor U1; when the first capacitor C1 discharges to the output of the first inverter U1A through the digital adjustable resistor U1, the voltage of V2 gradually decreases, and when the voltage of V2 decreases to the low level threshold voltage Vtl of the first inverter U1A, the output of the first inverter U1A flips to high level, and the output of the second inverter U2B V3 flips to low level. After the level of V3 is inverted and becomes lower, V2 (voltage + V3 at both ends of the first capacitor C1) changes abruptly, the voltage of V2 changes abruptly from voltage + V3 (high level) at both ends of the first capacitor C1 to voltage + V3 (low level) at both ends of the first capacitor C1, and then the first capacitor C1 performs the charging process again, and the process is repeated.
The utility model adopts the digital adjustable resistor U1 and the first capacitor C1 to form an RC charge-discharge circuit, and cooperates with a software programming SPI digital interface to input a control command to adjust the resistance value of the digital adjustable resistor, so as to adjust the output frequency PWM _ OUT of the circuit; because the output frequency of the circuit can be adjusted, the consistency correction can be carried out on the output frequency at the rear end of the output, and the consistency can reach a certain convergence effect by adjusting the output frequency; the on-off of periodic pulse output is realized through the cooperation of the triode and the first reverser, the power consumption of the circuit is reduced, and the circuit cost is reduced by building the oscillation circuit through discrete components.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are intended to be included within the scope of the present invention as defined by the appended claims.
Claims (6)
1. An adjustable pulse generating circuit, comprising: the device comprises a digital interface, a charging and discharging circuit, a switch control circuit, a digital interface and a signal output end;
one end of the charge-discharge circuit is connected with the digital interface through a triode, the other end of the charge-discharge circuit is connected with the signal output end, and the charge-discharge circuit is used for adjusting the output frequency;
one end of the switch control circuit is connected with the digital interface through a triode, the other end of the switch control circuit is connected with the signal output end, and the switch control circuit is used for adjusting the output on-off.
2. The adjustable pulse generating circuit of claim 1, wherein: the charge and discharge circuit comprises a digital adjustable resistor and a first capacitor, wherein a PRA pin of the digital adjustable resistor is connected with one end of the first capacitor, and the other end of the first capacitor is connected with a signal output end.
3. The adjustable pulse generating circuit of claim 2, wherein: the switch control circuit comprises a digital interface, a triode, a second resistor, a first phase inverter and a second phase inverter, wherein the base of the triode is connected with one end of the second resistor, the other end of the second resistor is connected with the digital interface, the collector of the triode is connected with the input end of the first phase inverter, the emitting electrode of the triode is grounded, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the signal output end.
4. The adjustable pulse generating circuit of claim 3, wherein: the PRW pin of the digital adjustable resistor is connected between the first inverter and the second inverter.
5. The adjustable pulse generating circuit of claim 4, wherein: the digital adjustable resistor comprises a control chip and a second resistor, a second capacitor is connected between a GND pin and a VCC pin of the control chip, and the second capacitor is connected with a power supply.
6. The adjustable pulse generating circuit of claim 5, wherein: the diode is characterized by further comprising a diode, wherein the anode of the diode is connected with one end of the first capacitor through a first resistor, and the cathode of the diode is connected with a power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921102933.6U CN210670006U (en) | 2019-07-15 | 2019-07-15 | Adjustable pulse generating circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921102933.6U CN210670006U (en) | 2019-07-15 | 2019-07-15 | Adjustable pulse generating circuit |
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| CN210670006U true CN210670006U (en) | 2020-06-02 |
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| CN201921102933.6U Expired - Fee Related CN210670006U (en) | 2019-07-15 | 2019-07-15 | Adjustable pulse generating circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110365316A (en) * | 2019-07-15 | 2019-10-22 | 中航(深圳)航电科技发展有限公司 | A kind of adjusting method and its circuit of pulse generating circuit |
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2019
- 2019-07-15 CN CN201921102933.6U patent/CN210670006U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110365316A (en) * | 2019-07-15 | 2019-10-22 | 中航(深圳)航电科技发展有限公司 | A kind of adjusting method and its circuit of pulse generating circuit |
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