CN114640324A - Low-power-consumption periodic pulse generation circuit - Google Patents
Low-power-consumption periodic pulse generation circuit Download PDFInfo
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- CN114640324A CN114640324A CN202210157404.6A CN202210157404A CN114640324A CN 114640324 A CN114640324 A CN 114640324A CN 202210157404 A CN202210157404 A CN 202210157404A CN 114640324 A CN114640324 A CN 114640324A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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Abstract
The invention relates to a low-power consumption periodic pulse generating circuit, comprising: the switch circuit is respectively connected with the charge-discharge circuit and the potential rise circuit through the first node; the second node is connected with a buffer circuit, and the output end of the buffer circuit is connected with the control end of the switch circuit through an inverter circuit; the electric potential rising circuit is used for enabling the electric potential of the second node to rise rapidly, and by flexibly utilizing the substrate bias modulation effect and the characteristic of flexible configuration of the electric potential of an N trap in the integrated circuit, the electric leakage current of the secondary inverter is reduced by isolating the influence of the slowly-changing signal falling edge on the secondary inverter, so that the low power consumption of the whole circuit is realized.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a low-power-consumption periodic pulse generating circuit.
Background
Periodic pulse signals are often used in the field of integrated circuits, such as in circuits that require periodic refreshing or sample-and-hold circuits. In the conventional method, the generation of the periodic pulse signal can be realized by dividing the frequency of the clock signal or adjusting the duty ratio of the signal after the periodic signal is generated by using a ring oscillator circuit.
The method for generating periodic pulses by using clock signal frequency division requires an external input of a clock signal, which reduces the flexibility of the circuit (for example, some circuits cannot provide clock signals), and the counter for frequency division of the clock signal generates dynamic power consumption per cycle.
The method for generating the periodic signal by using the ring oscillator circuit does not need an external input clock signal, and the circuit is flexible, but the circuit using the method still has the problem of overhigh power consumption when generating the pulse signal with a long period, because the circuit generating the signal with the long period inevitably has a node with slowly rising or falling voltage, the slowly rising or falling voltage signal can generate leakage current in a next-stage inverter of the node, and the useless power consumption is increased to cause overhigh power consumption of the circuit.
Disclosure of Invention
The invention aims to provide a low-power-consumption periodic pulse generating circuit which can avoid leakage current generated in a next-stage inverter.
The technical scheme adopted by the invention for solving the technical problems is as follows: provided is a low power consumption periodic pulse generating circuit including: the switch circuit is respectively connected with the charge and discharge circuit and the potential rise circuit through the first node; the second node is connected with a buffer circuit, and the output end of the buffer circuit is connected with the control end of the switch circuit through an inverter circuit; the potential rising circuit is used for rapidly rising the potential of the second node and comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the grid electrode of the first MOS tube is connected with the first node, the body electrode and the source electrode are both connected with a power supply end, and the drain electrode is connected with the source electrode of the second MOS tube; the grid electrode of the second MOS tube is connected with the first node, the body electrode of the second MOS tube is connected with the power supply end, the source electrode of the second MOS tube is connected with the first reset circuit, and the drain electrode of the second MOS tube is connected with the source electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with the first node, the body electrode of the third MOS tube is connected with the source electrode and then connected with the second reset circuit, and the drain electrode of the third MOS tube is connected with the second node; the control ends of the first reset circuit and the second reset circuit are connected with the output end of the buffer circuit, the second node is further connected with a third reset circuit, and the third reset circuit is connected with the output end of the buffer circuit.
The switch circuit controls the charge and discharge circuit through an MOS tube.
The charge and discharge circuit comprises a resistor and a capacitor, one end of the resistor is connected with the first node, and the other end of the resistor is grounded; one end of the capacitor is connected with the first node, and the other end of the capacitor is connected with alternating current ground.
The buffer circuit is formed by connecting an even number of inverters in series.
The first reset circuit comprises a first switch tube, the control end of the first switch tube is connected with the output end of the buffer circuit, the first end of the first switch tube is connected with the source electrode of the second MOS tube, the second end of the first switch tube is grounded, and a first capacitor is connected between the first end and the second end of the first switch tube.
The second reset circuit comprises a second switch tube, the control end of the second switch tube is connected with the output end of the buffer circuit, the first end of the second switch tube is connected with the source electrode of the third MOS tube, the second end of the second switch tube is grounded, and a second capacitor is connected between the first end and the second end of the second switch tube.
The third reset circuit comprises a third switching tube, the control end of the third switching tube is connected with the output end of the buffer circuit, the first end of the third switching tube is connected with the second node, and the second end of the third switching tube is grounded.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention improves on the basis of a basic ring oscillation circuit, reduces the leakage current of the secondary inverter to realize the low power consumption of the whole circuit by flexibly utilizing the substrate bias modulation effect of PMOS and the flexible configuration characteristic of the N-well potential in the integrated circuit and isolating the influence of the slowly-changed signal falling edge on the secondary inverter, and the circuit structure provided by the invention is convenient for adjusting the pulse period and the pulse duty ratio and has wide applicability.
Drawings
Fig. 1 is a circuit diagram of an embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a low-power consumption periodic pulse generating circuit, as shown in figure 1, comprising: the charging and discharging circuit comprises a switching circuit 1, a first node B and a second node C, wherein the switching circuit 1 is respectively connected with a charging and discharging circuit 2 and a potential rising circuit 3 through the first node B; the second node C is connected to the buffer circuit 4, and the output end H of the buffer circuit 4 is connected to the control end of the switch circuit 1 through the inverter circuit 5.
The potential rising circuit 3 is configured to rapidly rise the potential of the second node C, and includes a first MOS transistor MP1, a second MOS transistor MP2, and a third MOS transistor MP3, where a gate of the first MOS transistor MP1 is connected to the first node B, a body and a source are both connected to a power supply terminal VDD, and a drain is connected to a source of the second MOS transistor MP 2; the gate of the second MOS transistor MP2 is connected to the first node B, the body is connected to the power supply terminal VDD, the source is connected to the first reset circuit 6, and the drain is connected to the source of the third MOS transistor MP 3; the gate of the third MOS transistor MP3 is connected to the first node B, the body is connected to the source and then to the second reset circuit 7, and the drain is connected to the second node C; the control ends of the first reset circuit 6 and the second reset circuit 7 are connected with the output end of the buffer circuit 4, the second node C is further connected with a third reset circuit 8, and the third reset circuit 8 is connected with the output end of the buffer circuit 4.
In this embodiment, the body of the second MOS transistor MP2 is connected to the power supply terminal VDD, and the source of the second MOS transistor MP2 is an X node, so that the second MOS transistor MP2 has a substrate bias modulation effect. The body and the source of the third MOS transistor MP3 are both Y-nodes, so the third MOS transistor MP3 has no substrate bias modulation effect. Due to the substrate bias effect, the absolute value of the threshold voltage of the second MOS transistor MP2 is greater than the absolute value of the threshold voltage of the third MOS transistor MP 3.
The switch circuit 1 controls the charging and discharging circuit through a MOS transistor MP 0. The gate of the MOS transistor MP0 is connected to the output terminal a of the inverter circuit 5, the source is connected to the power supply terminal VDD, and the drain is connected to the first node B.
The charge and discharge circuit 2 comprises a resistor R and a capacitor Cb, one end of the resistor R is connected with the first node B, and the other end of the resistor R is grounded; one end of the capacitor Cb is connected to the first node B, and the other end is connected to an ac ground, which may be a power supply terminal VDD or a ground. The period of the pulse signal generated by the circuit structure of the present embodiment is proportional to the product of the resistor R and the capacitor Cb, and the period of the pulse signal can be adjusted by adjusting the resistor R or the capacitor Cb.
The buffer circuit 4 is formed by connecting an even number of inverters in series. The duty ratio of the pulse signal generated by the circuit configuration of the present embodiment is proportional to the delay of the even number of inverters, and the duty ratio of the pulse signal can be adjusted by adjusting the number of inverters or the delay of a single inverter.
The first reset circuit 6 includes a first switch MN1, a control terminal of the first switch MN1 is connected to the output terminal H of the buffer circuit 4, a first terminal of the first switch MN1 is connected to the source of the second MOS transistor MP2 (i.e., connected to the X node), a second terminal of the first switch MN is grounded, and a first capacitor Cx is further connected between the first terminal and the second terminal.
The second reset circuit 7 includes a second switch MN2, a control end of the second switch MN2 is connected to the output end H of the buffer circuit 4, a first end of the second switch MN2 is connected to a source of the third MOS transistor MP3 (i.e., connected to the Y node), a second end of the second switch MN is grounded, and a second capacitor Cy is further connected between the first end and the second end.
The third reset circuit 8 comprises a third switch tube MN0, a control terminal of the third switch tube MN0 is connected to the output terminal H of the buffer circuit 4, a first terminal is connected to the second node C, and a second terminal is grounded.
When the circuit works, at the beginning of each period, the potential of the node A is VDD, the potential of the node B is VDD, the potentials of the node X and the node Y are GND, the potential of the node C is GND, and the potential of the node H is GND. The charge on the capacitor Cb connected to the node B is discharged through the resistor R, the voltage at the node B gradually decreases, in this process, the first MOS transistor MP1 is turned on first to charge the node X, the second MOS transistor MP2 is turned on to charge the node Y, and finally the third MOS transistor MP3 is turned on to pull up the potential at the node C. Since the absolute value of the threshold voltage of the second MOS transistor MP2 is greater than the absolute value of the threshold voltage of the third MOS transistor MP3, the node Y maintains the GND potential and the third MOS transistor MP3 maintains the off state before the voltage at the node B is reduced enough to turn on the second MOS transistor MP 2. When the voltage at the node B is decreased to a level sufficient to turn on the second MOS transistor MP2, the potential at the node Y is pulled high, because the absolute value of the threshold voltage of the third MOS transistor MP3 is lower than the absolute value of the threshold voltage of the second MOS transistor MP2, the third MOS transistor MP3 is in a state of strong conductivity as soon as it is turned on, and therefore the potential at the node C is pulled high rapidly. In summary, the voltage of the node B, which is slowly changed, is restored to a signal that rises rapidly when it is conducted to the node C, so that leakage of the inverter of the next-stage buffer circuit 4 connected to the node C is avoided, whereby low power consumption of the circuit can be achieved.
After the voltage of the node C rises to the threshold flipping point of the inverter of the buffer circuit 4, the voltage of the node H rises through the delay of the even number of inverters, the third switching tube MN0 is turned on, the node C recovers to the GND potential, the potential of the node a falls to turn on the MOS transistor MP0, the potential of the node B is pulled high, and the signal rising of the node H also turns on the first switching tube MN1 and the second switching tube MN2 to reset the node X and the node Y to the GND.
After the potential of the node C is restored to GND, the node H signal is pulled low through the delay of the even number of inverters, the node A signal is raised, the MOS tube MP0 is turned off, the resetting process is finished, and a new signal period is turned on.
Because the circuit is always in dynamic change and does not have a stable static state, the circuit structure has a self-starting function, and a power supply is electrified and can normally work after a period of establishment time to generate a stable periodic pulse signal.
It is not easy to find that the invention improves on the basis of the basic ring oscillation circuit, and reduces the leakage current of the secondary inverter to realize the low power consumption of the whole circuit by flexibly using the substrate bias modulation effect of PMOS and the flexible configuration characteristic of the N-well potential in the integrated circuit and by isolating the influence of the slowly changing signal falling edge on the secondary inverter, and the circuit structure provided by the invention is convenient for adjusting the pulse period and the pulse duty ratio and has wide applicability.
Claims (7)
1. A low power consumption periodic pulse generating circuit, comprising: the switch circuit is respectively connected with the charge and discharge circuit and the potential rise circuit through the first node; the second node is connected with a buffer circuit, and the output end of the buffer circuit is connected with the control end of the switch circuit through an inverter circuit; the potential rising circuit is used for rapidly rising the potential of the second node and comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the grid electrode of the first MOS tube is connected with the first node, the body electrode and the source electrode are both connected with a power supply end, and the drain electrode is connected with the source electrode of the second MOS tube; the grid electrode of the second MOS tube is connected with the first node, the body electrode of the second MOS tube is connected with the power supply end, the source electrode of the second MOS tube is connected with the first reset circuit, and the drain electrode of the second MOS tube is connected with the source electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with the first node, the body electrode of the third MOS tube is connected with the source electrode and then connected with the second reset circuit, and the drain electrode of the third MOS tube is connected with the second node; the control ends of the first reset circuit and the second reset circuit are connected with the output end of the buffer circuit, the second node is further connected with a third reset circuit, and the third reset circuit is connected with the output end of the buffer circuit.
2. The low power consumption periodic pulse generating circuit of claim 1, wherein the switching circuit controls the charging and discharging circuit through a MOS transistor.
3. The low power consumption periodic pulse generating circuit of claim 1, wherein the charge and discharge circuit comprises a resistor and a capacitor, one end of the resistor is connected to the first node, and the other end of the resistor is grounded; one end of the capacitor is connected with the first node, and the other end of the capacitor is connected with alternating current ground.
4. The low power consumption periodic pulse generating circuit of claim 1, wherein the buffer circuit is formed by connecting an even number of inverters in series.
5. The low power consumption periodic pulse generating circuit according to claim 1, wherein the first reset circuit comprises a first switching tube, a control terminal of the first switching tube is connected to the output terminal of the buffer circuit, a first terminal of the first switching tube is connected to the source of the second MOS tube, a second terminal of the first switching tube is grounded, and a first capacitor is further connected between the first terminal and the second terminal.
6. The low power consumption periodic pulse generating circuit according to claim 1, wherein the second reset circuit comprises a second switching tube, a control end of the second switching tube is connected to the output end of the buffer circuit, a first end of the second switching tube is connected to a source of the third MOS tube, a second end of the second switching tube is grounded, and a second capacitor is further connected between the first end and the second end.
7. The low power consumption periodic pulse generating circuit of claim 1, wherein the third reset circuit comprises a third switch, a control terminal of the third switch is connected to the output terminal of the buffer circuit, a first terminal of the third switch is connected to the second node, and a second terminal of the third switch is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210157404.6A CN114640324A (en) | 2022-02-21 | 2022-02-21 | Low-power-consumption periodic pulse generation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210157404.6A CN114640324A (en) | 2022-02-21 | 2022-02-21 | Low-power-consumption periodic pulse generation circuit |
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| CN114640324A true CN114640324A (en) | 2022-06-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210157404.6A Pending CN114640324A (en) | 2022-02-21 | 2022-02-21 | Low-power-consumption periodic pulse generation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024012250A1 (en) * | 2022-07-15 | 2024-01-18 | 北京比特大陆科技有限公司 | Logic control circuit, trigger, and pulse generation circuit |
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2022
- 2022-02-21 CN CN202210157404.6A patent/CN114640324A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024012250A1 (en) * | 2022-07-15 | 2024-01-18 | 北京比特大陆科技有限公司 | Logic control circuit, trigger, and pulse generation circuit |
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