CN210183299U - Nonlinear harmonic signal generation circuit - Google Patents
Nonlinear harmonic signal generation circuit Download PDFInfo
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- CN210183299U CN210183299U CN201920808233.2U CN201920808233U CN210183299U CN 210183299 U CN210183299 U CN 210183299U CN 201920808233 U CN201920808233 U CN 201920808233U CN 210183299 U CN210183299 U CN 210183299U
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Abstract
The utility model discloses a nonlinear harmonic signal generating circuit adopts the transistor response input signal of work in linear interval, generates input signal's nonlinear component to 2 harmonic components based on input signal generation input signal, nonlinear harmonic components such as 3 harmonic components, and then can compensate or the plastic to input signal, guarantee input signal's direct current component, linearity etc. improve analog circuit's comprehensive properties.
Description
Technical Field
The utility model relates to an analog signal handles technical field, especially relates to a can follow the nonlinear harmonic signal generation circuit that generates corresponding nonlinear harmonic in the input signal.
Background
In many analog signal processing applications, the input signal itself contains non-ideal non-linear harmonic components, such as 2 nd harmonic component, 3 rd harmonic component, etc. The existence of these nonlinear harmonic components affects the direct current component, linearity, etc. of the signal, and thus a corresponding analog circuit is required to eliminate these nonlinear harmonic components.
For example, the nonlinear power consumption devices are largely used in the power grid, so that the proportion of the nonlinear harmonic component of the power grid is increased, and harmonic pollution is caused. The method for eliminating the nonlinear harmonic in the power grid at the present stage comprises the following steps: 1. a rectifier transformer is additionally arranged; 2. a rectifier with high power factor is selected. These ways of eliminating non-linear harmonics in the grid are cumbersome, inconvenient to maintain, and have no significant effect on eliminating harmonic generation.
Therefore, how to eliminate the nonlinear harmonic component of the input signal in the analog circuit by using a simple circuit structure and ensure the dc component, linearity, etc. of the input signal becomes a technical problem to be solved in the development of the analog circuit processing technology.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a nonlinear harmonic signal generating circuit to the technical problem who exists among the prior art, can follow and generate corresponding nonlinear harmonic in the input signal and compensate or the plastic to input signal to improve analog circuit's comprehensive properties.
In order to achieve the above object, the present invention provides a nonlinear harmonic signal generation circuit, the circuit including: the feedback circuit comprises an input unit, a feedback unit and an operational amplification unit, wherein the operational amplification unit and the feedback unit form a closed-loop feedback amplification circuit; the input end and the control end of the input unit are used for receiving input signals, and the output end of the input unit is electrically connected to the input end of the operational amplification unit; the input end of the feedback unit is electrically connected to the input end of the operational amplification unit, the control end of the feedback unit is used for receiving the input signal, and the output end of the feedback unit is electrically connected to the output end of the operational amplification unit; at least one of the input unit and the feedback unit responds to the input signal by adopting a transistor working in a linear interval to generate a nonlinear component of the input signal, wherein the polarity of the nonlinear component generated by the input unit is opposite to that of the nonlinear component generated by the feedback unit; and the operational amplification unit generates and outputs a nonlinear harmonic component of the input signal according to the nonlinear component.
The utility model has the advantages that: the utility model discloses nonlinear harmonic signal generating circuit adopts the work to respond to input signal at linear interval's transistor, generates input signal's nonlinear component to 2 harmonic components based on input signal generation input signal, nonlinear harmonic components such as 3 harmonic components, and then can compensate or the plastic to input signal, guarantee input signal's direct current component, linearity etc. improves analog circuit's comprehensive properties, and circuit structure is simple.
Drawings
Fig. 1 is a schematic diagram of a nonlinear harmonic signal generation circuit architecture of the present invention;
fig. 2 is a schematic diagram of the working principle of the nonlinear harmonic signal generating circuit of the present invention;
fig. 3 is a schematic circuit diagram of a first embodiment of the nonlinear harmonic signal generation circuit of the present invention;
fig. 4 is a schematic circuit diagram of a second embodiment of the nonlinear harmonic signal generating circuit of the present invention;
fig. 5 is a schematic circuit diagram of the amplitude adjustment of the nonlinear harmonic signal generation circuit according to the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention. Furthermore, the present invention repeats reference numerals and/or reference letters in different examples, which are repeated for purposes of simplicity and clarity and do not, themselves, indicate a relationship between the various embodiments and/or arrangements discussed.
Referring to fig. 1, the structure of the nonlinear harmonic signal generating circuit of the present invention is schematically illustrated. The utility model discloses nonlinear harmonic signal generation circuit includes: the feedback circuit comprises an input unit 11, a feedback unit 13 and an operational amplification unit 12, wherein the operational amplification unit 12 and the feedback unit 13 form a closed-loop feedback amplification circuit. The input end and the control end of the input unit 11 are used for receiving input signals, and the output end is electrically connected to the input end of the operational amplification unit 12; the input end of the feedback unit 13 is electrically connected to the input end of the operational amplification unit 12, the control end thereof is used for receiving the input signal, and the output end thereof is electrically connected to the output end of the operational amplification unit 12; at least one of the input unit 11 and the feedback unit 13 responds to the input signal by adopting a transistor working in a linear interval to generate a nonlinear component of the input signal, wherein the polarity of the nonlinear component generated by the input unit 11 is opposite to that of the nonlinear component generated by the feedback unit 13; the operational amplifier 12 generates and outputs a nonlinear harmonic component of the input signal based on the nonlinear component.
Optionally, the input unit 11 includes a first transistor and/or a second transistor operating in a linear region. The first transistor is used for responding to a negative input signal in the input signals to enable a first nonlinear component with a negative direction to be generated in the equivalent conductance of the input signals, and the second transistor is used for responding to a positive input signal in the input signals to enable a first nonlinear component with a positive direction to be generated in the equivalent conductance of the input signals. That is, by controlling only the transistors of the input section to generate nonlinear components, various nonlinear harmonic components such as the 2 nd harmonic component and the 3 rd harmonic component of the input signal required for analog circuit processing can be generated at the output end of the operational amplifier section 12. At this time, the feedback unit 13 may adopt a resistor, or a transistor operating in a linear region, and a gate of the transistor is in phase with a driving signal of a source, so that a non-linear component does not exist in an equivalent conductance.
Optionally, the feedback unit 13 includes a third transistor and/or a fourth transistor operating in a linear region. The third transistor is used for responding to a positive input signal in the input signals so as to generate a positive second nonlinear component in the equivalent conductance of the input signals; the fourth transistor is used for responding to a negative input signal in the input signals so as to generate a second nonlinear component with a negative direction in the equivalent conductance of the fourth transistor. That is, by controlling only the transistors of the feedback section to generate nonlinear components, various nonlinear harmonic components such as the 2 nd harmonic component and the 3 rd harmonic component of the input signal required for analog circuit processing can be generated at the output terminal of the operational amplifier section 12. At this time, the input unit 11 may adopt a resistor, or a transistor operating in a linear region, and a gate of the transistor is in phase with a driving signal of a source, so that a non-linear component does not exist in an equivalent conductance.
Optionally, the input unit 11 includes a first transistor and a second transistor operating in a linear region; the feedback unit 13 includes a third transistor and a fourth transistor operating in a linear region. The first transistor responds to a negative input signal in the input signals to enable the equivalent conductance of the first transistor to generate a negative nonlinear component, and the third transistor responds to a positive input signal in the input signals to enable the equivalent conductance of the third transistor to generate a positive nonlinear component; alternatively, the second transistor is responsive to a positive input signal of the input signals to generate a positive non-linear component in its equivalent conductance, and the fourth transistor is responsive to a negative input signal of the input signals to generate a negative non-linear component in its equivalent conductance. That is, by controlling the transistors of the input unit and the feedback unit to generate nonlinear components having opposite polarities, it is possible to generate various nonlinear harmonic components such as a 2 nd harmonic component and a 3 rd harmonic component of an input signal required for analog circuit processing at the output terminal of the operational amplifier unit 12.
Optionally, the operational amplifier unit 12 generates and outputs a nonlinear harmonic component of the input signal according to the first nonlinear component and/or the second nonlinear component. The operational amplification unit 12 may employ a fully differential input fully differential output operational amplifier (diff-op). The first transistor M1 and the second transistor M2 serve as input resistors of the operational amplifier, and the third transistor M3 and the third transistor M3 serve as feedback resistors of the operational amplifier. Since the open gain of the operational amplifier is large, the gain from the differential input to the differential output of the operational amplifier is equal to the feedback resistance divided by the input resistance, as can be seen from the feedback control principle. That is, by controlling only the transistor of the input unit to generate the nonlinear component, or controlling only the transistor of the feedback unit to generate the nonlinear component, or controlling both the transistor of the input unit and the transistor of the feedback unit to generate the nonlinear components having opposite polarities, various nonlinear harmonic components such as the 2 nd harmonic component and the 3 rd harmonic component of the input signal required for the analog circuit processing can be generated at the output terminal of the operational amplifier unit 12. These nonlinear harmonic components can compensate or shape the input signal, ensuring the direct current component, linearity, etc. of the input signal.
The utility model discloses nonlinear harmonic signal generating circuit generates input signal's 2 harmonic components based on input signal, and nonlinear harmonic components such as 3 harmonic components can compensate or the plastic to input signal, guarantees input signal's direct current component, linearity etc to improve analog circuit's comprehensive properties, and circuit structure is simple.
Referring to fig. 2, the working principle of the nonlinear harmonic signal generating circuit of the present invention is schematically illustrated.
The input unit 11 includes a first potential adjustment block LS1 and a first transistor M1, a second potential adjustment block LS2 and a second transistor M2; the feedback unit 13 includes a third potential adjustment block LS3 and a third transistor M3, a fourth potential adjustment block LS4 and a fourth transistor M4.
In this embodiment, the first to fourth transistors M1 to M4 are all NMOS transistors, and the corresponding first to fourth voltage adjusting modules LS1 to LS4 are all voltage down modules, which are used to lower (shift down) the voltage of the corresponding input signal by about the threshold voltage Vth of one NMOS transistor, so that the corresponding NMOS transistor operates in a linear region. In other embodiments, the first to fourth transistors M1 to M4 may be PMOS transistors, and the corresponding first to fourth voltage adjusting modules LS1 to LS4 are voltage adjusting modules for adjusting the voltage of the corresponding input signal to be higher (shift up) by about one threshold voltage of the PMOS transistor, so that the corresponding PMOS transistor operates in a linear region. The first to fourth level adjustment blocks LS1-LS4 may each employ a simple source follower to achieve the above-described effect.
Specifically, the source of the first transistor M1 receives a positive input signal of the input signals through the first voltage adjustment module LS1, and the drains thereof are electrically connected to the positive input terminal of the operational amplifier unit 12 and the drain of the third transistor M1, respectively; the source of the second transistor M2 receives the negative input signal of the input signals through the second level adjustment module LS2, and the drains thereof are electrically connected to the negative input terminal of the operational amplification unit 12, respectively. By controlling different coupling connection methods of the gate and the source of the input MOS transistor (the first transistor M1 and the second transistor M2), different driving voltages (as shown in the figure, the gate driving voltage vg1 of the first transistor M1 and the gate driving voltage vg2 of the second transistor M2) are obtained for the gate of the input MOS transistor, so that different nonlinear components can be generated on the input MOS transistor. For example, the gates of the first transistor M1 and the second transistor M2 are controlled to receive the negative input signal, so that the first transistor M1 responds to the negative input signal to generate a negative nonlinear component in the equivalent conductance thereof, and the equivalent conductance of the second transistor M2 has no nonlinear component (equivalent to being connected in a resistive manner); or, the gates of the first transistor M1 and the second transistor M2 are controlled to receive the positive input signal, so that the second transistor M2 responds to the positive input signal to generate a positive nonlinear component in its equivalent conductance, and the equivalent conductance of the first transistor M1 has no nonlinear component (equivalent to being connected in a resistive manner).
Specifically, the source of the third transistor M3 is connected to the negative output terminal of the operational amplification unit 12 through a third voltage adjustment module LS3, and the drain thereof is connected to the positive input terminal of the operational amplification unit 12; the source of the fourth transistor M4 is connected to the positive output terminal of the operational amplifier unit 12 through the fourth level adjustment module LS4, and the drain thereof is connected to the negative input terminal of the operational amplifier unit 12. By controlling different coupling connection methods of the gate and the source of the feedback MOS transistor (the third transistor M3 and the fourth transistor M4), different driving voltages (as shown in the figure, the gate driving voltage vg3 of the third transistor M3 and the gate driving voltage vg4 of the fourth transistor M4) can be obtained for the gate of the feedback MOS transistor, so that different nonlinear components can be generated on the feedback MOS transistor. For example, the gates of the third transistor M3 and the fourth transistor M4 are controlled to receive the positive input signal, so that the third transistor M3 responds to the positive input signal to generate a positive nonlinear component in its equivalent conductance, and the equivalent conductance of the fourth transistor M4 has no nonlinear component (equivalent to being connected in a resistive manner); or, the gates of the third transistor M3 and the fourth transistor M4 are controlled to receive the negative input signal, so that the fourth transistor M4 responds to the negative input signal to generate a negative nonlinear component in the equivalent conductance thereof, and the equivalent conductance of the third transistor M3 has no nonlinear component (equivalent to being connected in a resistance form).
The operational amplification unit 12 employs a fully differential input and fully differential output operational amplifier (diff-op). The first transistor M1 and the second transistor M2 serve as input resistors of the operational amplifier, and the third transistor M3 and the fourth transistor M4 serve as feedback resistors of the operational amplifier. Since the open gain of the operational amplifier is large, the gain from the differential input to the differential output of the operational amplifier is equal to the feedback resistance divided by the input resistance, as can be seen from the feedback control principle.
For small signal analysis, the following signals are first defined: x is an input differential small signal, xpAnd xnCorresponding to the positive/negative input small signals; y is the output differential small signal, ypAnd ynRespectively corresponding to the positive/negative output small signals; sigmaiIs the ideal conductance of the input MOS transistor, and σfIs the ideal conductance of the feedback MOS tube. g0Is an ideal gain of the closed-loop feedback amplifying circuit. The utility model discloses nonlinear harmonic signal generation circuit, operational amplifier's ideal gain sets to unity gain.
Since the input MOS transistor and the feedback MOS transistor operate in a linear region, the conductance formula of these MOS transistors can be expressed by the following formula:
σr＝σ(1±k*x) (1)
wherein σrThe actual conductance of the MOS tube is sigma which is the ideal conductance of the MOS tube, and k is the nonlinear component in the conductance of the MOS tube.
Through different coupling connection methods of the grid electrodes and the source electrodes of the input MOS tube and the feedback MOS tube, required nonlinear components can be generated on the input MOS tube or the feedback MOS tube respectively.
The utility model discloses closed loop feedback amplifier circuit's gain G can be expressed by following formula:
wherein σriTo the actual conductance of the input MOS transistor, sigmarfFor feedback of the actual conductance of the MOS transistor, kiFor a non-linear component in the conductance of the input MOS transistor, kfIs a nonlinear component in the conductance of the feedback MOS transistor.
It can be seen from the formula (2) that by controlling only the input MOS transistor to generate the nonlinear component, or controlling only the feedback MOS transistor to generate the nonlinear component, or controlling both the input MOS transistor and the feedback MOS transistor to generate the nonlinear components with opposite polarities, various nonlinear harmonic components such as 2 nd harmonic, 3 rd harmonic, etc. required by the analog circuit processing can be generated at the output terminal of the operational amplifier.
Referring to fig. 3, a schematic circuit diagram of a first embodiment of a nonlinear harmonic signal generating circuit according to the present invention is shown. In the present embodiment, the gates of the first transistor M1 and the second transistor M2 both receive the negative input signal xnThe gates of the third transistor M3 and the fourth transistor M4 receive the positive input signal xp. The nonlinear harmonic signal generation circuit in this embodiment is implemented by the first transistor M1 and the third transistor M3.
The conductance formula of the MOS transistor operating in the linear region can be expressed as follows:
σ1＝σi(1-k1x) (3)
σ3＝σf(1+k3x) (4)
wherein k is1Is a non-linear component in the conductance of the first transistor M1, and k3Is a non-linear component in the conductance of the third transistor M3.
The gain G1 of the closed-loop feedback amplifying circuit in this embodiment can be expressed by the following formula:
the gate of the first transistor M1 is driven by the negative input signal, and the source of the first transistor M1 is driven by the positive input signal with the reduced potential, so that the potential difference signal (which is a positive signal) between the gate and the source of the first transistor M1 is opposite to the input signal (i.e. the negative input signal) received by the gate, and a negative nonlinear component k is generated in the equivalent conductance of the first transistor M11. The gate of the second transistor M2 is in phase with the source drive signal, so there is no non-linear component (equivalent to being connected as a resistor) in the equivalent conductance of the second transistor M2. The positive input signal drives the gate of the third transistor M3, and the negative output signal drives the source of the third transistor M3, so that the potential difference signal (positive signal) between the gate and the source of the third transistor M3 is in the same phase as the input signal received by the gate (i.e. the positive input signal), and therefore the positive non-linear component k is generated in the equivalent conductance of the third transistor M33. The gate of the fourth transistor M4 is in phase with the source driving signal, so there is no non-linear component (equivalent to being connected in a resistive manner) in the equivalent conductance of the fourth transistor M4.
As can be seen from equation (5), by controlling the first transistor M1 and the third transistor M3 to generate the non-linear components with opposite polarities, the required non-linear harmonic components, including the negative 2 nd harmonic, the positive 3 rd harmonic, and the negative 4 th harmonic, are generated at the output of the operational amplifier. That is, in the present embodiment, the transistors of the input unit and the feedback unit are controlled simultaneously to generate the nonlinear components having opposite polarities. In other embodiments, the gate of the first transistor M1 can be driven by the positive input signal, and the source of the first transistor M1 can be driven by the positive input signal with the reduced potential, so that the gate of the first transistor M1 and the source of the first transistor M1 are in the same phase, and thus there is no non-linear component in the equivalent conductance, i.e. only the transistor of the feedback unit is controlled to generate a non-linear component (i.e. a positive non-linear component is generated in the equivalent conductance of the third transistor M3)The component of the property k3) (ii) a Or the gate of the third transistor M3 is driven by the negative input signal, and the source of the third transistor M3 is driven by the negative output signal with the adjusted potential, so that the gate of the third transistor M3 and the source of the third transistor M3 are in the same phase, and thus the equivalent conductance of the third transistor M3 has no non-linear component, i.e. only the transistor of the input unit is controlled to generate a non-linear component (i.e. the first transistor M1 generates the negative non-linear component k in the equivalent conductance)1)。
Referring to fig. 4, a schematic circuit diagram of a nonlinear harmonic signal generating circuit according to a second embodiment of the present invention is shown. The difference from the embodiment shown in fig. 3 is that in the present embodiment, the gates of the first transistor M1 and the second transistor M2 both receive the positive input signal xpThe gates of the third transistor M3 and the fourth transistor M4 receive the negative input signal xn. The nonlinear harmonic signal generation circuit in the present embodiment is implemented by the second transistor M2 and the fourth transistor M4.
The conductance formula of the MOS transistor operating in the linear region can be expressed as follows:
σ2＝σi(1+k2x) (6)
σ4＝σf(1-k4x) (7)
wherein k is2Is a non-linear component in the conductance of the second transistor M2, and k4Is a non-linear component in the conductance of the fourth transistor M4.
The gain G2 of the closed-loop feedback amplifying circuit in this embodiment can be expressed by the following formula:
the gate of the second transistor M2 is driven by the positive input signal, and the source of the second transistor M2 is driven by the negative input signal whose potential is reduced, so that the potential difference signal (which is a positive signal) between the gate and the source of the second transistor M2 is in the same phase as the input signal received by the gate thereof (i.e., the positive input signal), and therefore a positive nonlinear component k is generated in the equivalent conductance of the second transistor M22. First of allThe gate of the transistor M1 is in phase with the source driving signal, so there is no non-linear component in the equivalent conductance of the first transistor M1. The gate of the fourth transistor M4 is driven by the negative input signal, and the source of the fourth transistor M4 is driven by the positive output signal with the potential adjusted down, so that the potential difference signal (being a positive signal) between the gate and the source of the fourth transistor M4 is opposite to the input signal (i.e. the negative input signal) received by the gate, and therefore a negative nonlinear component k is generated in the equivalent conductance of the fourth transistor M44. The gate of the third transistor M3 is in phase with the source driving signal, so there is no non-linear component in the equivalent conductance of the third transistor M3.
As can be seen from equation (8), by controlling the second transistor M2 and the fourth transistor M4 simultaneously to generate nonlinear components with opposite polarities, various nonlinear harmonic components including positive 2 th harmonic, positive 3 rd harmonic, and positive 4 th harmonic are generated at the output end of the operational amplifier. That is, in the present embodiment, the transistors of the input unit and the feedback unit are controlled simultaneously to generate the nonlinear components having opposite polarities. In other embodiments, the gate of the second transistor M2 can be driven by the negative input signal, and the source of the second transistor M2 can be driven by the negative input signal with the down-regulated potential, so that the gate of the second transistor M2 and the source of the second transistor M2 are in phase, and thus there is no non-linear component in the equivalent conductance, i.e. only the transistor of the feedback unit is controlled to generate a non-linear component (i.e. only the transistor of the fourth transistor M4 generates a positive non-linear component k in the equivalent conductance)4) (ii) a Or the positive input signal drives the gate of the fourth transistor M4, and the positive output signal with the reduced potential drives the source of the fourth transistor M4, so that the gate of the fourth transistor M4 and the driving signal of the source are in the same phase, and thus the equivalent conductance of the fourth transistor M4 has no non-linear component, i.e. only the transistor of the input unit is controlled to generate a non-linear component (i.e. the non-linear component k generated in the equivalent conductance of the second transistor M2)2)。
Referring to fig. 5, the present invention is a schematic circuit diagram of amplitude adjustment for a nonlinear harmonic signal generating circuit. The difference between the embodiment shown in fig. 3 is that, in this embodiment, the circuit further includes a first multiplexer MUX1 and a second multiplexer MUX 2. In other embodiments, the circuit may also include any one of the first multiplexer MUX1 and the second multiplexer MUX 2.
A first input of the first multiplexer MUX1 receives a positive input signal xpA second input terminal of which receives a negative input signal xnAnd the output end of the first transistor M1 is connected with the grid of the second transistor M2. Selecting the positive input signal x by controlling the first multiplexer MUX1pOr a negative input signal xnThe polarity of the input signals to the gates of the first transistor M1 and the second transistor M2 can be adjusted for output. The first multiplexer MUX1 selects the positive input signal xpWhen outputting, the connection of the gates of the first transistor M1 and the second transistor M2 is equivalent to the connection of the gates of the first transistor M1 and the second transistor M2 in the embodiment shown in fig. 4. The first multiplexer MUX1 selects the negative input signal xnWhen outputting, the connection of the gates of the first transistor M1 and the second transistor M2 is equivalent to the connection of the gates of the first transistor M1 and the second transistor M2 in the embodiment shown in fig. 3.
A first input of the second multiplexer MUX1 receives a negative input signal xnA second input terminal of which receives a positive input signal xpAnd the output ends of the first transistor M3 and the second transistor M4 are connected with the gates of the third transistor M3 and the fourth transistor M4. Selecting the positive input signal x by controlling the second multiplexer MUX2pOr a negative input signal xnThe output can be performed by adjusting the polarity of the input signal inputted to the gates of the third transistor M3 and the fourth transistor M4. The second multiplexer MUX2 selects the positive input signal xpWhen outputting, the connection of the gates of the third transistor M3 and the fourth transistor M4 is equivalent to the connection of the gates of the third transistor M3 and the fourth transistor M4 in the embodiment shown in fig. 3. The second multiplexer MUX2 selects the negative input signal xnWhen outputting, the connection of the gates of the third transistor M3 and the fourth transistor M4 is equivalent to the third transistor M4 in the embodiment shown in fig. 4The gates of the transistor M3 and the fourth transistor M4 are connected.
Preferably, the first multiplexer MUX1 may perform a proportional division of the received positive input signal and the negative input signal, so as to adjust the proportion of the positive/negative input signal inputted to the gates of the first transistor M1 and the second transistor M2. For example, the multiplexer MUX1 is clocked by k: 1(sel < k: 1>) receives the positive/negative input signal and outputs it to the gate of the corresponding transistor, thereby adjusting the amplitude of the first nonlinear component. When one of the positive and negative input signals is 0 while the other is maximum, the polarities of the input signals to the gates of the first and second transistors M1 and M2 are also adjusted.
Preferably, the second multiplexer MUX2 may perform a ratio distribution of the received positive input signal and the negative input signal, so that the ratio of the positive/negative input signals input to the gates of the third transistor M3 and the fourth transistor M4 may be adjusted. For example, the multiplexer MUX1 is clocked by k: 1(sel < k: 1>) receives the positive/negative input signal and outputs the positive/negative input signal to the gate of the corresponding transistor, thereby adjusting the amplitude of the second nonlinear component. When one of the positive and negative input signals is 0 while the other is maximum, the polarities of the input signals input to the gates of the third and fourth transistors M3 and M4 are also adjusted.
As can be seen from the derivation analysis of fig. 3 and 4, the polarities of the nonlinear harmonics generated by the two implementations are opposite, as shown in equation (5) and equation (8). Therefore, by adjusting the proportional composition of the input signals of the first transistor M1 and the second transistor M2, and adjusting the proportional composition of the input signals of the third transistor M3 and the fourth transistor M4, the adjustment of the polarity of the output signal and the adjustment of the nonlinear harmonic amplitude of the output signal can be realized.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A nonlinear harmonic signal generation circuit, the circuit comprising: the feedback circuit comprises an input unit, a feedback unit and an operational amplification unit, wherein the operational amplification unit and the feedback unit form a closed-loop feedback amplification circuit;
the input end and the control end of the input unit are used for receiving input signals, and the output end of the input unit is electrically connected to the input end of the operational amplification unit;
the input end of the feedback unit is electrically connected to the input end of the operational amplification unit, the control end of the feedback unit is used for receiving the input signal, and the output end of the feedback unit is electrically connected to the output end of the operational amplification unit;
at least one of the input unit and the feedback unit responds to the input signal by adopting a transistor working in a linear interval to generate a nonlinear component of the input signal, wherein the polarity of the nonlinear component generated by the input unit is opposite to that of the nonlinear component generated by the feedback unit;
and the operational amplification unit generates and outputs a nonlinear harmonic component of the input signal according to the nonlinear component.
2. The circuit of claim 1, wherein the input cell comprises a first transistor and/or a second transistor operating in a linear region;
the first transistor is used for responding to a negative input signal in the input signals so as to generate a first nonlinear component with a negative direction in the equivalent conductance of the first transistor;
the second transistor is used for responding to a positive input signal in the input signals so as to generate a first nonlinear component in a positive direction in an equivalent conductance of the second transistor.
3. The circuit of claim 2, wherein the first transistor and the second transistor are both MOS transistors;
the source electrode of the first transistor receives the positive input signal through the first potential adjusting module, and the drain electrode of the first transistor is connected to the positive input end of the operational amplification unit;
the source electrode of the second transistor receives the negative input signal through a second potential adjusting module, and the drain electrode of the second transistor is connected to the negative input end of the operational amplifying unit;
the gates of the first transistor and the second transistor are used for receiving the negative input signal so as to generate a negative first nonlinear component only by the first transistor; or
The gates of the first transistor and the second transistor are both used for receiving the positive input signal, so that only the second transistor generates a first nonlinear component in a forward direction.
4. The circuit of claim 3, wherein the first transistor and the second transistor are both NMOS transistors, and the first potential adjustment module and the second potential adjustment module are both potential down-regulation modules; or the first transistor and the second transistor are both PMOS transistors, and the first potential adjusting module and the second potential adjusting module are both potential adjusting modules.
5. The circuit of claim 3, wherein the circuit further comprises a first multiplexer;
the first multiplexer has a first input end receiving the positive input signal, a second input end receiving the negative input signal, and an output end connected to the gates of the first transistor and the second transistor, for adjusting the ratio of the positive input signal to the negative input signal.
6. The circuit of claim 1, wherein the feedback unit comprises a third transistor and/or a fourth transistor operating in a linear region;
the third transistor is used for responding to a positive input signal in the input signals so as to generate a positive second nonlinear component in equivalent conductance of the input signals;
the fourth transistor is used for responding to a negative input signal in the input signals so as to generate a second nonlinear component with a negative direction in the equivalent conductance of the fourth transistor.
7. The circuit of claim 6, wherein the third transistor and the fourth transistor are both MOS transistors;
the source electrode of the third transistor is connected to the negative output end of the operational amplification unit through a third potential adjustment module, and the drain electrode of the third transistor is connected to the positive input end of the operational amplification unit;
the source electrode of the fourth transistor is connected to the positive output end of the operational amplification unit through a fourth potential adjustment module, and the drain electrode of the fourth transistor is connected to the negative input end of the operational amplification unit;
the gates of the third transistor and the fourth transistor are used for receiving the positive input signal so as to generate a second non-linear component in a forward direction only by the third transistor; or
The gates of the third transistor and the fourth transistor are used for receiving the negative input signal, so that only the fourth transistor generates a negative second nonlinear component.
8. The circuit of claim 7, wherein the third transistor and the fourth transistor are both NMOS transistors, and the third potential adjustment module and the fourth potential adjustment module are both potential down-regulation modules; or the third transistor and the fourth transistor are both PMOS transistors, and the third potential adjustment module and the fourth potential adjustment module are both potential up-adjustment modules.
9. The circuit of claim 7, wherein the circuit further comprises a second multiplexer;
the first input end of the second multiplexer receives the negative input signal, the second input end of the second multiplexer receives the positive input signal, and the output end of the second multiplexer is connected with the gates of the third transistor and the fourth transistor and is used for adjusting the proportion of the positive input signal and the negative input signal.
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