CN210157160U - Digital clock frequency multiplication circuit system - Google Patents
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- CN210157160U CN210157160U CN201920882983.4U CN201920882983U CN210157160U CN 210157160 U CN210157160 U CN 210157160U CN 201920882983 U CN201920882983 U CN 201920882983U CN 210157160 U CN210157160 U CN 210157160U
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Abstract
The utility model discloses a digital clock doubling circuit system, include: a duty ratio digital calibration circuit module or an OR gate circuit module; the duty ratio digital calibration circuit module comprises a pulse generator and a half-clock period delay circuit; the input clock signal passes through the duty ratio digital calibration circuit module or the OR gate circuit module to output a frequency-multiplied output clock signal. Adopt the utility model discloses digital clock doubling circuit system based on 50% duty cycle calibration has reduced the shake of output clock effectively, has saved circuit consumption and area, and input clock signal FIN reduces 33% to the response time between the output clock signal FOUT simultaneously, can support the high-speed response scene.
Description
Technical Field
The utility model relates to a digital circuit technical field, in particular to digital clock doubling circuit system and digital clock doubling signal generation method.
Background
The digital clock frequency multiplier circuit is a commonly used circuit module in integrated circuits such as Universal Asynchronous Receiver/Transmitter (UART) interfaces, Phase-locked loops (PLL) interfaces, and the like. For a Universal Asynchronous Receiver Transmitter (UART) interface, the digital clock frequency multiplier circuit can improve the transmission baud rate of the universal asynchronous receiver transmitter; for a phase-locked loop (PLL) circuit, the digital clock frequency multiplier circuit is added on an input path of a reference clock, so that the crystal oscillator frequency supported by the phase-locked loop (PLL) has more diversity, and the flexibility and reusability of the whole circuit system are improved.
In the prior art, there are various schemes for implementing a digital clock multiplier circuit, which can be implemented by, for example, a phase-locked loop frequency synthesizer with an internal division ratio equal to 2. The implementation scheme has the advantages that no special requirements are required on the waveform, duty ratio and the like of an input clock, and meanwhile, the characteristics of a closed-loop system are benefited, so that the output frequency is stable, the noise characteristic is good, and the influence of the process, the temperature, the power supply voltage and the like is small; but at the same time, the circuit area and power consumption cost in the implementation scheme are too large, and the complexity of the whole system is higher.
Referring to fig. 1, a digital clock frequency multiplication circuit system implemented based on an xor gate and a delay chain in the prior art is shown. The period of an input clock signal FIN of the system is T, a Delay signal FIN _ D is obtained after passing through a Delay chain (Delay-line), and the Delay amount of the Delay chain (Delay-line) is T; the input clock signal FIN and the delay signal FIN _ D are subjected to exclusive-or (XOR) operation to obtain a frequency-doubled output clock signal FOUT, and the pulse width of the output frequency-doubled clock signal FOUT is proportional to the length of the delay chain. The circuit system in the implementation scheme is composed of digital gate circuits, has a simple structure and good robustness, and is particularly suitable for the condition of low input frequency; but this implementation requires the duty cycle of the input clock to be exactly 50% otherwise the clock edge jitter problem as shown in figure 2 will occur. Therefore, before a signal is input into the digital clock multiplication circuit system shown in fig. 1, the input clock signal must undergo a calibration process with a 50% duty cycle. The 50% duty cycle calibration circuit may be implemented in an analog or digital manner; because the analog mode comprises a passive device, the area is large; the digital circuit mode has small area and better reliability, thereby being widely adopted.
Referring to fig. 3, a 50% duty cycle digital calibration (DCC) module, which is commonly used in the prior art, is shown in a dashed box. Firstly, a Pulse Generator (PG) is used by the 50% duty ratio digital calibration circuit module to convert an input clock signal with any duty ratio (x% T) into a narrow Pulse clock signal a; then accurately delaying the narrow pulse clock signal a by 1.5 input clock cycles through a Half clock Cycle Delay circuit (HCDL for short) to obtain a delayed narrow pulse clock signal b; the narrow pulse clocks a and b before and after the delay pass through a trigger reset LATCH (SR-LATCH) to obtain a clock signal c with a duty ratio of 50% and the same frequency as the input clock signal, the clock signal c passes through a digital clock frequency multiplier circuit implemented based on an xor gate and a delay chain as shown in fig. 1, and finally a stable double frequency clock signal FOUT can be output, and a timing diagram of the digital clock frequency multiplier circuit system with a 50% duty ratio Digital Calibration Circuit (DCC) module is shown in fig. 4.
Fig. 5 shows a typical circuit for implementing a triggered reset LATCH (SR-LATCH) in the prior art, fig. 6 shows a typical circuit for implementing an exclusive or gate (XOR) in the prior art, and fig. 7 shows a typical circuit for implementing a Delay-chain (Delay-line) in the prior art. The trigger reset LATCH (SR-LATCH) is composed of a gate (MUX) and a D-type trigger (DFF) to ensure that the input paths of the S and R input signals are matched; an exclusive or gate (XOR) comprises 5 unit gate circuits; and the Delay chain (Delay-line) is formed by cascading a plurality of stages of Delay units (delta) so as to ensure that the output clock has a reliable pulse width.
However, the inventor has found that, although the digital clock frequency doubling circuit system calibrated based on 50% duty ratio in the prior art can implement the frequency doubling function, the circuit structure is still complex, and particularly, the circuit implementation shown in fig. 5, 6, and 7 has large circuit area and dynamic power consumption and long clock path. For a clock signal, each level of gate circuit in its path accumulates phase noise, increasing the jitter of the clock edge, and thus causing the system performance to deteriorate. In order to reduce clock jitter, the adopted improvement method is to increase the gate width and the gate length of MOS tubes of each stage of circuit on a clock path in equal proportion and reduce the flicker noise contribution, but the circuit area is increased in a square relation; or the driving capability of each stage circuit is increased to suppress clock jitter, but the circuit power consumption is significantly increased. Therefore, the clock jitter is seriously deteriorated by the overlong clock path of the digital clock frequency multiplier circuit, and the power consumption and the area cost of the circuit are increased. Secondly, since there is a delay of 1.5 input clock cycles between the input signal a and the output signal b of the half-clock-cycle delay circuit (HCDL), which determines the start-up time of the digital clock multiplier circuit system, the delay from the first edge of the input clock signal FIN to the first edge of the output clock signal FOUT is 1.5 input clock cycles, as shown in fig. 4, the output clock signal FOUT needs to wait for 1.5 input clock cycles before being output normally, which is not acceptable for the application scenario requiring high-speed response.
SUMMERY OF THE UTILITY MODEL
Based on this, for solving the technical problem among the prior art, the utility model particularly provides a digital clock doubling circuit system:
the digital clock frequency multiplication circuit system comprises a duty ratio digital calibration circuit module and an OR gate circuit module; the duty ratio digital calibration circuit module comprises a pulse generator and a half-clock period delay circuit; the output end of the pulse generator is connected to the input end of the half-clock-period delay circuit and the first input end of the OR gate circuit module; the output end of the half-clock period delay circuit is connected to the second input end of the OR gate circuit module;
the pulse generator receives a digital clock signal with any duty ratio as an input clock signal, converts the input clock signal into a narrow pulse signal and outputs the narrow pulse signal;
the half clock period delay circuit receives the narrow pulse signal generated by the pulse generator, and generates and outputs a delayed narrow pulse signal after delaying the narrow pulse signal by 1.5 input clock periods;
the or gate circuit module receives the narrow pulse signal generated by the pulse generator and the delayed narrow pulse signal generated by the half-clock-period delay circuit, and the or gate circuit module performs logical or operation on the narrow pulse signal and the delayed narrow pulse signal to obtain a double-frequency clock signal serving as an output clock signal and outputs the double-frequency clock signal.
In one embodiment, the narrow pulse signal and the delayed narrow pulse signal have the same frequency and a phase difference of 3 pi.
In one embodiment, the digital clock frequency multiplication circuit system includes one or more cascaded extended frequency multiplication units, each extended frequency multiplication unit including a half-clock-period delay circuit of the extended frequency multiplication unit and an or gate circuit module of the extended frequency multiplication unit.
In one embodiment, when the digital clock frequency doubling circuit system includes a cascaded extended frequency doubling unit, a frequency doubling clock signal output by the or gate circuit module is divided into two paths and input to the extended frequency doubling unit, wherein one path is input to the half-clock period delay circuit of the extended frequency doubling unit, the other path is input to the first input end of the or gate circuit module of the extended frequency doubling unit, and an output signal of the half-clock period delay circuit of the extended frequency doubling unit is input to the second input end of the or gate circuit module of the extended frequency doubling unit; and the OR gate circuit module of the extended frequency multiplication unit outputs a quadruple frequency clock signal.
In one embodiment, when the digital clock frequency doubling circuit system includes a plurality of cascaded extended frequency doubling units, an output clock signal of a previous extended frequency doubling unit is divided into two paths and input to the current extended frequency doubling unit, wherein one path is input to a half-clock-period delay circuit of the current extended frequency doubling unit, the other path is input to a first input end of an or gate circuit module of the current extended frequency doubling unit, and an output signal of the half-clock-period delay circuit of the current extended frequency doubling unit is input to a second input end of the or gate circuit module of the current extended frequency doubling unit; the OR gate circuit module of the current-stage expanded frequency multiplication unit outputs frequency multiplication clock signals.
In addition, in order to solve the technical problems in the prior art, a method for generating a digital clock frequency multiplication signal is provided, which includes:
step one, inputting a digital clock signal with any duty ratio as an input clock signal to a pulse generator, converting the input clock signal by the pulse generator to generate a narrow pulse signal and outputting the narrow pulse signal;
step two, the narrow pulse signal generated by the pulse generator is input into a half-clock period delay circuit, and the half-clock period delay circuit delays the input narrow pulse signal by 1.5 input clock periods to generate and output a delayed narrow pulse signal;
and inputting the narrow pulse signal generated by the pulse generator and the delayed narrow pulse signal generated by the half-clock-period delay circuit into an OR gate circuit module, and performing logical OR operation on the narrow pulse signal and the delayed narrow pulse signal by the OR gate circuit module to obtain a double-frequency clock signal serving as an output clock signal and outputting the double-frequency clock signal.
In one embodiment, the narrow pulse signal and the delayed narrow pulse signal have the same frequency and a phase difference of 3 pi.
In one embodiment, the output of the or gate circuit module is connected to one or more cascaded extended frequency doubling units, and each extended frequency doubling unit includes a half-clock-period delay circuit of the extended frequency doubling unit and an or gate circuit module of the extended frequency doubling unit.
In one embodiment, when the digital clock frequency doubling circuit system includes a cascaded extended frequency doubling unit, a frequency doubling clock signal output by the or gate circuit module is divided into two paths and input to the extended frequency doubling unit, wherein one path is input to the half-clock period delay circuit of the extended frequency doubling unit, the other path is input to the first input end of the or gate circuit module of the extended frequency doubling unit, and an output signal of the half-clock period delay circuit of the extended frequency doubling unit is input to the second input end of the or gate circuit module of the extended frequency doubling unit; and the OR gate circuit module of the extended frequency multiplication unit outputs a quadruple frequency clock signal.
In one embodiment, when the digital clock frequency doubling circuit system includes a plurality of cascaded extended frequency doubling units, an output clock signal of a previous extended frequency doubling unit is divided into two paths and input to the current extended frequency doubling unit, wherein one path is input to a half-clock-period delay circuit of the current extended frequency doubling unit, the other path is input to a first input end of an or gate circuit module of the current extended frequency doubling unit, and an output signal of the half-clock-period delay circuit of the current extended frequency doubling unit is input to a second input end of the or gate circuit module of the current extended frequency doubling unit; the OR gate circuit module of the current-stage expanded frequency multiplication unit outputs frequency multiplication clock signals.
Implement the embodiment of the utility model provides a, will have following beneficial effect:
the technical scheme of the utility model among, trigger reset LATCH (SR-LATCH), Delay chain (Delay-line) and exclusive OR gate (XOR) among the clock path of digital clock doubling circuit system only replace with one OR gate (OR), have simplified circuit structure greatly, have shortened the clock path.
The utility model provides a digital clock doubling circuit system based on 50% duty cycle calibration has reduced the shake of output clock effectively through simplifying circuit structure, shortening the clock route, has saved circuit consumption and area, and the response time of input clock signal between to the output clock signal reduces 33% simultaneously, can support the high-speed response scene.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Wherein:
FIG. 1 is a schematic diagram of a digital clock frequency multiplier circuit system implemented based on an XOR gate and a delay chain in the prior art;
FIG. 2 is a diagram illustrating a digital clock multiplier circuit system with jitter on clock edges in the prior art;
FIG. 3 is a schematic diagram of a digital clock multiplier circuit system incorporating a 50% duty cycle digital calibration circuit module according to the prior art;
FIG. 4 is a timing diagram of a prior art digital clock multiplier circuit system incorporating a 50% duty cycle digital calibration circuit module;
FIG. 5 is a circuit schematic of a prior art triggered reset latch;
FIG. 6 is a circuit diagram of an XOR gate in the prior art;
FIG. 7 is a circuit diagram of a prior art delay chain;
FIG. 8 is a schematic diagram of a digital clock frequency multiplier circuit system according to the present invention;
fig. 9 is a timing diagram of the digital clock frequency-doubled signal according to the present invention;
fig. 10 is a schematic diagram of multiple frequency multiplication expansion of the digital clock frequency multiplier circuit system according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The utility model provides a digital clock doubling signal generation method, including following step:
step one, inputting a digital clock signal FIN with any duty ratio (x% T) as an input clock signal to a Pulse Generator (PG), and converting the input clock signal into a narrow pulse signal a by the Pulse Generator (PG) and outputting the narrow pulse signal a;
step two, the narrow pulse signal a generated by the conversion of the Pulse Generator (PG) is input to a half-clock cycle delay circuit (HCDL), and the half-clock cycle delay circuit (HCDL) delays the input narrow pulse signal a by 1.5 input clock cycles (1.5T) to generate and output a delayed narrow pulse signal b;
the narrow pulse signal a and the delayed narrow pulse signal b have the same frequency and the phase difference of 3 pi;
step three, the narrow pulse signal a generated by the Pulse Generator (PG) and the delayed narrow pulse signal b generated by the half clock cycle delay circuit (HCDL) are simultaneously input to an OR gate (OR) circuit module, and the OR gate (OR) circuit module performs logical OR operation on the narrow pulse signal a and the delayed narrow pulse signal b to obtain a double frequency clock signal FOUT as an output clock signal and outputs the FOUT; fig. 9 is a timing chart of the digital clock frequency multiplication signal generation method.
And further, the method can be expanded to obtain multiple frequency clock signals. The output of the OR gate (OR) circuit module is connected to one OR more cascaded expanded frequency doubling units, and each expanded frequency doubling unit comprises a half-clock-period delay circuit of the expanded frequency doubling unit and an OR gate circuit module of the expanded frequency doubling unit.
When the output of the OR gate (OR) circuit module is connected to an extended frequency doubling unit, a double-frequency clock signal output by the OR gate (OR) circuit module is divided into two paths to be input to the extended frequency doubling unit, wherein one path is input to a half-clock period delay circuit of the extended frequency doubling unit, the other path is input to a first input end of an OR gate circuit module of the extended frequency doubling unit, and an output signal of the half-clock period delay circuit of the extended frequency doubling unit is input to a second input end of the OR gate circuit module of the extended frequency doubling unit; and the OR gate circuit module of the extended frequency multiplication unit outputs a quadruple frequency clock signal.
Further expanding and acquiring multiple frequency clock signals, when the output of the OR gate circuit module is connected to a plurality of cascaded expanded frequency doubling units, the output clock signal of the previous expanded frequency doubling unit is divided into two paths and input to the current expanded frequency doubling unit, wherein one path is input to the half-clock period delay circuit of the current expanded frequency doubling unit, the other path is input to the first input end of the OR gate circuit module of the current expanded frequency doubling unit, and the output signal of the half-clock period delay circuit of the current expanded frequency doubling unit is input to the second input end of the OR gate circuit module of the current expanded frequency doubling unit; the OR gate circuit module of the current-stage expanded frequency multiplication unit outputs frequency multiplication clock signals.
Referring to fig. 8, the present invention further provides a digital clock frequency doubling circuit system, which comprises a duty ratio digital calibration circuit module and an OR gate (OR) circuit module; the duty ratio digital calibration circuit module comprises a Pulse Generator (PG) and a half-clock period delay circuit (HCDL); an output of the Pulse Generator (PG) is connected to an input of the half-clock-cycle delay circuit (HCDL) and to a first input of the OR-gate (OR) circuit block; an output terminal of the half-clock period delay circuit (HCDL) is connected to a second input terminal of the OR gate (OR) circuit block;
the Pulse Generator (PG) receives a digital clock signal FIN with any duty ratio (x% T) as an input clock signal, converts the input clock signal into a narrow pulse signal and outputs the narrow pulse signal;
the half clock cycle delay circuit (HCDL) receives the narrow pulse signal a generated by the Pulse Generator (PG), and generates and outputs a delayed narrow pulse signal b after delaying the narrow pulse signal a by 1.5 input clock cycles (1.5T);
the narrow pulse signal a and the delayed narrow pulse signal b have the same frequency and the phase difference of 3 pi;
the OR gate (OR) circuit module receives the narrow pulse signal a generated by the Pulse Generator (PG) and the delayed narrow pulse signal b generated by the half-clock-cycle delay circuit (HCDL), and performs a logical OR operation on the narrow pulse signal a and the delayed narrow pulse signal b to obtain a double frequency clock signal FOUT as an output clock signal and outputs the FOUT. The OR gate (OR) circuit module can be designed and implemented in various ways according to the system application requirements, and as shown in fig. 8, the OR gate (OR) circuit module is formed by connecting nor gates and not gates.
Although there is still an inherent delay of 1.5 input clock cycles (1.5T) between the input signal and the output signal of the half-clock cycle delay circuit (HCDL), since the OR circuit module directly synthesizes the input signal and the output signal into the double frequency clock signal FOUT through the logical OR operation, the double frequency clock signal FOUT as the output clock signal is already stabilized from the second edge of the input narrow pulse signal a, and thus the delay from the input clock signal FIN to the output clock signal FOUT is only 1 input clock cycle (T).
The digital clock frequency multiplication circuit system also comprises one or more cascaded expanded frequency multiplication units, and each expanded frequency multiplication unit comprises a half-clock period delay circuit of the expanded frequency multiplication unit and an OR gate circuit module of the expanded frequency multiplication unit.
When the digital clock frequency doubling circuit system comprises a cascaded extended frequency doubling unit, a frequency doubling clock signal output by an OR gate (OR) circuit module is divided into two paths and input to the extended frequency doubling unit, wherein one path is input to a half-clock period delay circuit of the extended frequency doubling unit, the other path is input to a first input end of an OR gate circuit module of the extended frequency doubling unit, and an output signal of the half-clock period delay circuit of the extended frequency doubling unit is input to a second input end of the OR gate circuit module of the extended frequency doubling unit; and the OR gate circuit module of the extended frequency multiplication unit outputs a quadruple frequency clock signal.
When the digital clock frequency doubling circuit system comprises a plurality of cascaded extended frequency doubling units, an output clock signal of a previous extended frequency doubling unit is divided into two paths and is input to a current extended frequency doubling unit, wherein one path is input to a half-clock period delay circuit of the current extended frequency doubling unit, the other path is input to a first input end of an OR gate circuit module of the current extended frequency doubling unit, and an output signal of the half-clock period delay circuit of the current extended frequency doubling unit is input to a second input end of the OR gate circuit module of the current extended frequency doubling unit; the OR gate circuit module of the current-stage expanded frequency multiplication unit outputs frequency multiplication clock signals.
The technical scheme of the utility model thereby can expand and obtain multiple frequency clock signal, as shown in fig. 10. Because the output frequency doubling clock signal 2 FIN is a narrow pulse clock signal, the frequency doubling frequency can be directly expanded continuously without a Pulse Generator (PG) at the later stage. Continuously inputting the output double-frequency clock signal to a half-clock-period delay circuit (HCDL) and an OR (OR) circuit module, thereby doubling the clock signal to obtain a quadruple-frequency clock signal 4 x FIN; and continuously inputting the output quadruple frequency clock signal into a half-clock-period delay circuit (HCDL) and an OR (OR) circuit module, thereby continuously doubling the clock signal to obtain an octave frequency clock signal 8 FIN, and so on until the working frequency reaches the upper limit of the process. In fig. 10, the delay amount of the half-clock cycle delay circuit (HCDL2) from the double-frequency clock signal 2 × FIN to the quadruple-frequency clock signal 4 × FIN is 1.5 cycles of 2 × FIN; if the frequency octave circuit is expanded to the octave circuit, the frequency octave circuit has 1.5 4 FIN periods, and the like in the following steps.
Implement the embodiment of the utility model provides a, will have following beneficial effect:
the technical scheme of the utility model, removed the trigger reset LATCH (SR-LATCH), Delay chain (Delay-Line) and exclusive OR gate (XOR) circuit module that contain among the prior art digital clock frequency doubling circuit, and the input/output signal of half clock cycle Delay circuit (HCDL) is directly done OR (OR) operation obtains two frequency doubling clock signals. Compared with the prior art, the technical scheme of the utility model the circuit structure has been simplified greatly to shorten the clock route, promoted output clock phase noise performance when saving area and consumption, the chronogenesis delay from input to output is only 1 input clock cycle moreover, more is applicable to high-speed response system.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (6)
1. A digital clock frequency multiplier circuit system is characterized in that,
the digital clock frequency multiplication circuit system comprises a duty ratio digital calibration circuit module and an OR gate circuit module; the duty ratio digital calibration circuit module comprises a pulse generator and a half-clock period delay circuit; the output end of the pulse generator is connected to the input end of the half-clock-period delay circuit and the first input end of the OR gate circuit module; the output end of the half-clock period delay circuit is connected to the second input end of the OR gate circuit module;
the pulse generator receives a digital clock signal with any duty ratio as an input clock signal, converts the input clock signal into a narrow pulse signal and outputs the narrow pulse signal;
the half clock period delay circuit receives the narrow pulse signal generated by the pulse generator, and generates and outputs a delayed narrow pulse signal after delaying the narrow pulse signal by 1.5 input clock periods;
the or gate circuit module receives the narrow pulse signal generated by the pulse generator and the delayed narrow pulse signal generated by the half-clock-period delay circuit, and the or gate circuit module performs logical or operation on the narrow pulse signal and the delayed narrow pulse signal to obtain a double-frequency clock signal serving as an output clock signal and outputs the double-frequency clock signal.
2. The digital clock doubling circuitry of claim 1,
the narrow pulse signal and the delayed narrow pulse signal have the same frequency and the phase difference of 3 pi.
3. The digital clock doubling circuit system of claim 1 or 2,
the digital clock frequency multiplication circuit system comprises one or more cascaded expanded frequency multiplication units, and each expanded frequency multiplication unit comprises a half-clock-period delay circuit of the expanded frequency multiplication unit and an OR gate circuit module of the expanded frequency multiplication unit.
4. The digital clock doubling circuitry of claim 3,
when the digital clock frequency doubling circuit system comprises a cascaded extended frequency doubling unit, a double-frequency clock signal output by the OR gate circuit module is divided into two paths and input to the extended frequency doubling unit, wherein one path is input to a half-clock-period delay circuit of the extended frequency doubling unit, the other path is input to a first input end of the OR gate circuit module of the extended frequency doubling unit, and an output signal of the half-clock-period delay circuit of the extended frequency doubling unit is input to a second input end of the OR gate circuit module of the extended frequency doubling unit; and the OR gate circuit module of the extended frequency multiplication unit outputs a quadruple frequency clock signal.
5. The digital clock doubling circuitry of claim 3,
when the digital clock frequency doubling circuit system comprises a plurality of cascaded extended frequency doubling units, an output clock signal of a previous-stage extended frequency doubling unit is divided into two paths and is input into the extended frequency doubling units, wherein one path is input into a half-clock-period delay circuit of the extended frequency doubling units, the other path is input into a first input end of an OR gate circuit module of the extended frequency doubling units, and an output signal of the half-clock-period delay circuit of the extended frequency doubling units is input into a second input end of the OR gate circuit module of the extended frequency doubling units; and the OR gate circuit module of the extended frequency multiplication unit outputs frequency multiplication clock signals.
6. The digital clock doubling circuitry of claim 4,
when the digital clock frequency doubling circuit system comprises a plurality of cascaded extended frequency doubling units, an output clock signal of a previous-stage extended frequency doubling unit is divided into two paths and is input into the extended frequency doubling units, wherein one path is input into a half-clock-period delay circuit of the extended frequency doubling units, the other path is input into a first input end of an OR gate circuit module of the extended frequency doubling units, and an output signal of the half-clock-period delay circuit of the extended frequency doubling units is input into a second input end of the OR gate circuit module of the extended frequency doubling units; and the OR gate circuit module of the extended frequency multiplication unit outputs frequency multiplication clock signals.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110166028A (en) * | 2019-06-13 | 2019-08-23 | 珠海微度芯创科技有限责任公司 | Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method |
| CN112445121A (en) * | 2021-02-01 | 2021-03-05 | 南京邮电大学 | Time register and time domain operation circuit for time-digital converter |
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2019
- 2019-06-13 CN CN201920882983.4U patent/CN210157160U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110166028A (en) * | 2019-06-13 | 2019-08-23 | 珠海微度芯创科技有限责任公司 | Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method |
| CN112445121A (en) * | 2021-02-01 | 2021-03-05 | 南京邮电大学 | Time register and time domain operation circuit for time-digital converter |
| CN112445121B (en) * | 2021-02-01 | 2021-04-16 | 南京邮电大学 | Time register and time domain operation circuit for time-digital converter |
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