CN112445121A - Time register and time domain operation circuit for time-digital converter - Google Patents
Time register and time domain operation circuit for time-digital converter Download PDFInfo
- Publication number
- CN112445121A CN112445121A CN202110133385.9A CN202110133385A CN112445121A CN 112445121 A CN112445121 A CN 112445121A CN 202110133385 A CN202110133385 A CN 202110133385A CN 112445121 A CN112445121 A CN 112445121A
- Authority
- CN
- China
- Prior art keywords
- time
- time register
- register
- gate
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to a time register and a time domain arithmetic circuit used for a time-to-digital converter, which adopt the time register based on a delay chain structure to save input time signals, solve the contradiction between a large range and the realization of low power consumption of a chip and the control of the area of the chip, simultaneously improve the stability and the noise resistance of the time register during working, adopt different connection modes of the time register to form the time domain arithmetic circuit, provide input signals for a later-stage time-to-digital converter (TDC), finish the functions of saving, adding, subtracting and integrating the time signals and improve the processing efficiency of the time signals.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a time register and a time domain operation circuit for a time-to-digital converter.
Background
Time-to-Digital converters (TDCs) are key components in many application circuits, including Time of Flight (TOF) measurements, jitter measurements, all-Digital phase-locked loops, and so on. In recent years, with the development of automatic driving and Artificial Intelligence (AI) technologies and the improvement of clock frequencies of large-scale digital circuits, higher requirements are put forward on TDC, and not only is the time signal measured more quickly and accurately, but also certain processing of the time signal is required.
A conventional method of storing the time signal is to store the time signal by charge storage using a capacitor. The method has the advantage of simple circuit structure, the storage of the time signal is finished through the charging of the capacitor, and the output of the time signal is finished through the discharging of the capacitor, but the range of the structure is limited by the power supply voltage and the size of the capacitor, and the power supply voltage or the size of the capacitor is required to be increased when the range is required to be increased; meanwhile, when the time signal is stored based on the capacitor, the capacitor voltage may be changed due to charge leakage inside the circuit and coupling noise of the parasitic capacitor, which may cause an error in the final output time signal. Therefore, the mode of storing the time signal by using the capacitor is difficult to solve the contradiction between the large range and the realization of low power consumption of the chip and the control of the chip area; and errors are easy to generate during storage.
Disclosure of Invention
In order to solve the above technical problem, the present invention provides a time register, which is based on a delay chain structure, and can ensure stability for storing a time signal and implement time domain operation while satisfying a large range.
The invention relates to a time register, which adopts the technical scheme that: comprising a delay chain, an or gate and a pulse generator, wherein: the input time signal IN is connected with the input end of the OR gate, the clock signal CLK is connected with the other input end of the OR gate and is connected with one input end of the pulse generator, the output end of the OR gate is connected with the enable end EN of the delay chain, the high level signal SET is connected with the input end of the delay chain, the output end of the delay chain is connected with the other input end of the pulse generator, and the output end of the pulse generator is used as the output end OUT of the time register.
As a preferred technical scheme of the invention: the delay chain is formed by cascading a plurality of delay units.
As a preferred technical scheme of the invention: the delay unit comprises a first PMOS transistor Mp1A second PMOS transistor Mp2A third PMOS transistor Mp3A fourth PMOS transistor Mp4A first NMOS transistor Mn1A second NMOS transistor Mn2A third NMOS transistor Mn3A fourth NMOS transistor Mn4Wherein:
first PMOS transistor Mp1Is connected with a power supply Vdd, and a first PMOS transistor Mp1And the third PMOS transistor Mp3Is connected to the source of a second PMOS transistor Mp2Source of the PMOS transistor is connected with a power supply Vdd, drain of the PMOS transistor is connected with a fourth PMOS transistor Mp4Is connected with the source of the first PMOS transistor M, the enable signal ENb is connected with the first PMOS transistor Mp1Gate of (D), second PMOS transistor Mp2The grid electrodes are connected;
signal input terminal of delay unit and third PMOS transistor Mp3First NMOS transistor Mp1Is connected to the gate of a third PMOS transistor Mp3Is connected to the first NMOS transistor Mn1And the drain of the fourth PMOS transistor Mp4Gate of (d), second NMOS transistor Mn2Is connected to the gate of a fourth PMOS transistor Mp4Is connected to the second NMOS transistor Mn2And serves as a signal output terminal of the delay unit;
first NMOS transistor Mn1Is connected to the third NMOS transistor Mn3Drain of (1), second NMOS transistor Mn2Is connected with the fourth NMOS transistor Mn4The enable signal EN is connected to the third NMOS transistor Mn3And the fourth NMOS transistor Mn4Is connected to the gate of the third NMOS transistor Mn3Is grounded, the fourth NMOS transistor Mn4Is grounded.
The time register based on the delay chain structure is adopted to complete the storage of the input time signal, different connection modes of the time register are adopted to form a time domain operation circuit, the input signal is provided for a later-stage time-to-digital converter (TDC), and the functions of storage, addition, subtraction and integration of the time signal are completed.
The time domain arithmetic circuit with the time saving function, which is formed by adopting the time register, comprises a time register 1, a time register 2, an OR gate and a delay module, wherein:
the input time signal A is connected with one input end of the OR gate, the input time signal B is connected with the input end of the delay module, the output end of the delay module is connected with the other input end of the OR gate, the output end of the OR gate is connected with the time signal input end of the time register 1, the clock signal CLK1 is connected with the clock signal input end of the time register 1, the output end of the time register 1 is connected with the time signal input end of the time register 2, the clock signal CLK2 is connected with the clock signal input end of the time register 2, and the output end of the time register 2 outputs the time signal Y.
As a preferred technical scheme of the invention: the time domain arithmetic circuit with the time adding function, which is formed by adopting the time register, comprises a time register 1, a time register 2, an OR gate and a delay module, wherein:
the input time signal A is connected with one input end of the OR gate, the input time signal B is connected with the input end of the delay module, the output end of the delay module is connected with the other input end of the OR gate, the output end of the OR gate is connected with the time signal input end of the time register 1, the clock signal CLK1 is connected with the clock signal input end of the time register 1, the output end of the time register 1 is connected with the time signal input end of the time register 2, the clock signal CLK2 is connected with the clock signal input end of the time register 2, and the output end of the time register 2 outputs the time signal Y.
As a preferred technical scheme of the invention: the time domain arithmetic circuit with the time subtraction function, which is formed by adopting the time register, comprises a time register 1, a time register 2, an OR gate and a delay module, wherein:
the input time signal A is connected with the time signal input end of the time register 1, the clock signal CLK1 is connected with the clock signal input end of the time register 1, the output end of the time register 1 is connected with one input end of an OR gate, the input time signal B is connected with the input end of a delay module, the output end of the delay module is connected with the other input end of the OR gate, the output end of the OR gate is connected with the input end of the time register 2, the clock signal CLK2 is connected with the clock signal input end of the time register 2, and the output end of the time register 2 outputs the time signal Y.
As a preferred technical scheme of the invention: the time domain arithmetic circuit with the time integration function, which is formed by adopting the time register, comprises a time register 1, a time register 2, an OR gate and a delay module, wherein:
the input time signal A is connected with one input end of the OR gate, the output signal Y is connected with the input end of the delay module, the output end of the delay module is connected with the other input end of the OR gate, the output end of the OR gate is connected with the time signal input end of the time register 1, the clock signal CLK1 is connected with the clock signal input end of the time register, the output end of the time register 1 is connected with the time signal input end of the time register 2, the clock signal CLK2 is connected with the clock signal input end of the time register 2, and the output end of the time register 2 outputs the time signal Y.
The beneficial technical effects of the invention are as follows: the time register adopts a delay chain structure, realizes the storage of the time signal by controlling the transmission of the time signal through the enable signal, solves the contradiction between a large range and the realization of low power consumption of a chip and the area of a control chip, simultaneously improves the stability and the anti-noise performance of the time register during working, adopts the time register to form a time domain operation circuit, realizes the functions of storage, addition, subtraction and integration of the time signal, and improves the processing efficiency of the time signal.
Drawings
FIG. 1 is a block diagram of a time domain arithmetic circuit for a time-to-digital converter according to the present invention;
FIG. 2 is a block diagram of a time domain arithmetic circuit with a time keeping function according to the present invention;
FIG. 3 is a block diagram of a time domain arithmetic circuit with time adding function according to the present invention;
FIG. 4 is a block diagram of a time domain arithmetic circuit with a time subtraction function according to the present invention;
fig. 5 is a block diagram of a time domain arithmetic circuit with a time integration function according to the present invention:
FIG. 6 is a block diagram of a clock register circuit according to the present invention:
fig. 7 is a schematic circuit diagram of a delay unit according to the present invention.
Detailed Description
The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.
As shown IN fig. 6, a time register according to the present invention includes a delay chain, an or gate, and a pulse generator, wherein an input time signal IN is connected to an input terminal of the or gate, a clock signal CLK is connected to another input terminal of the or gate and to one input terminal of the pulse generator, an output terminal of the or gate is connected to an enable terminal EN of the delay chain, a high level signal SET is connected to an input terminal of the delay chain, an output terminal of the delay chain is connected to another input terminal of the pulse generator, and an output terminal of the pulse generator serves as a time signal output terminal OUT.
The delay chain is composed of a plurality of delay units in cascade connection, the structure is shown in fig. 7, and the delay unit comprises a first PMOS transistor Mp1A second PMOS transistor Mp2A third PMOS transistor Mp3A fourth PMOS transistor Mp4A first NMOS transistor Mn1A second NMOS transistor Mn2A third NMOS transistor Mn3A fourth NMOS transistor Mn4Wherein the first PMOS transistor Mp1Is connected with a power supply Vdd, and a first PMOS transistor Mp1And the third PMOS transistor Mp3Is connected to the source of a second PMOS transistor Mp2Source of the PMOS transistor is connected with a power supply Vdd, drain of the PMOS transistor is connected with a fourth PMOS transistor Mp4Is connected with the source of the first PMOS transistor M, the enable signal ENb is connected with the first PMOS transistor Mp1Gate of (D), second PMOS transistor Mp2Is connected to the gate of the delay unit, the signal input terminal of the delay unit is connected to the third PMOS transistor Mp3First NMOS transistor Mp1Is connected to the gate of a third PMOS transistor Mp3Is connected to the first NMOS transistor Mn1And the drain of the fourth PMOS transistor Mp4Gate of (d), second NMOS transistor Mn2Is connected to the gate of a fourth PMOS transistor Mp4Is connected to the second NMOS transistor Mn2And serves as a signal output terminal of the delay unit, a first NMOS transistor Mn1Is connected to the third NMOS transistor Mn3Drain of (1), second NMOS transistor Mn2Is connected with the fourth NMOS transistor Mn4The enable signal EN is connected to the third NMOS transistor Mn3And the fourth NMOS transistor Mn4Is connected to the gate of the third NMOS transistor Mn3Is grounded, the fourth NMOS transistor Mn4Is grounded.
In the practical application process of the time domain operation circuit for the time-to-digital converter, as shown in fig. 1, a time signal is connected with an input end of the time domain operation circuit, a time signal Deltat output by the time domain operation circuit is connected with an input end of a TDC, and the TDC outputs a digital signal Dout.
In practical applications, the present invention provides a specific design for a time domain arithmetic circuit with a time saving function, as shown in fig. 2, the time domain arithmetic circuit with the time saving function includes a time register 1 and a time register 2, wherein an input time signal a is connected to a time signal input terminal of the time register 1, a clock signal CLK1 is connected to a clock signal input terminal of the time register, an output terminal of the time register 1 is connected to a time signal input terminal of the time register 2, a clock signal CLK2 is connected to a clock signal input terminal of the time register 2, and an output terminal of the time register 2 outputs a time signal Y.
In practical applications, the present invention provides a specific design for a time domain arithmetic circuit with a time adding function, as shown in fig. 3, the time domain arithmetic circuit with the time adding function includes a time register 1, a time register 2, an or gate and a delay module, wherein an input time signal a is connected to one input end of the or gate, an input time signal B is connected to an input end of the delay module, an output end of the delay module is connected to the other input end of the or gate, an output end of the or gate is connected to a time signal input end of the time register 1, a clock signal CLK1 is connected to a clock signal input end of the time register 1, an output end of the time register 1 is connected to a time signal input end of the time register 2, a clock signal CLK2 is connected to a clock signal input end of the time register 2, and an output end of the.
In practical applications, the present invention provides a specific design for a time domain arithmetic circuit with a time subtraction function, as shown in fig. 4, the time domain arithmetic circuit with the time subtraction function includes a time register 1, a time register 2, an or gate and a delay module, wherein an input time signal a is connected to a time signal input terminal of the time register 1, a clock signal CLK1 is connected to a clock signal input terminal of the time register 1, an output terminal of the time register 1 is connected to one input terminal of the or gate, an input time signal B is connected to an input terminal of the delay module, an output terminal of the delay module is connected to the other input terminal of the or gate, an output terminal of the or gate is connected to an input terminal of the time register 2, a clock signal CLK2 is connected to a clock signal input terminal of the time register 2, and an output terminal of the.
In practical applications, the present invention provides a specific design for a time domain arithmetic circuit with a time integration function, as shown in fig. 5, the time domain arithmetic circuit with the time integration function includes a time register 1, a time register 2, an or gate and a delay module, wherein an input time signal a is connected to one input end of the or gate, an output signal Y is connected to an input end of the delay module, an output end of the delay module is connected to the other input end of the or gate, an output end of the or gate is connected to a time signal input end of the time register 1, a clock signal CLK1 is connected to a clock signal input end of the time register, an output end of the time register 1 is connected to a time signal input end of the time register 2, a clock signal CLK2 is connected to a clock signal input end of the time register 2, and an output end of the time.
In summary, the time register and the time domain operation circuit for the time-to-digital converter designed by the invention are based on the delay chain structure, the range of the time register can be improved by increasing the length of the delay chain, the dependence on the power supply voltage and the chip area is small, the influence of charge leakage and circuit internal noise on the time register is small, the contradiction between large range and realization of low power consumption of the chip and control of the chip area is solved, and the stability and the anti-noise performance during time storage are improved; the time register is adopted to form a time domain operation circuit, so that the functions of storing, adding, subtracting and integrating time signals are realized, and the processing efficiency of the time signals is improved.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (7)
1. A time register comprising a delay chain, an or gate and a pulse generator, wherein: the input time signal IN is connected with the input end of the OR gate, the clock signal CLK is connected with the other input end of the OR gate and is connected with one input end of the pulse generator, the output end of the OR gate is connected with the enable end EN of the delay chain, the high level signal SET is connected with the input end of the delay chain, the output end of the delay chain is connected with the other input end of the pulse generator, and the output end of the pulse generator is used as a time signal output end OUT.
2. A time register as claimed in claim 1, characterized in that the delay chain is formed by a cascade of several delay cells.
3. A time register as claimed in claim 2, characterized in that the delay unit comprises a first PMOS transistor Mp1A second PMOS transistor Mp2A third PMOS transistor Mp3A fourth PMOS transistor Mp4A first NMOS transistor Mn1A second NMOS transistor Mn2A third NMOS transistor Mn3A fourth NMOS transistor Mn4Wherein:
first PMOS transistor Mp1Is connected with a power supply Vdd, and a first PMOS transistor Mp1And the third PMOS transistor Mp3Is connected to the source of a second PMOS transistor Mp2Source of the PMOS transistor is connected with a power supply Vdd, drain of the PMOS transistor is connected with a fourth PMOS transistor Mp4Is connected with the source of the first PMOS transistor M, the enable signal ENb is connected with the first PMOS transistor Mp1Gate of (D), second PMOS transistor Mp2The grid electrodes are connected;
signal input terminal of delay unit and third PMOS transistor Mp3First NMOS transistor Mp1Is connected to the gate of a third PMOS transistor Mp3Is connected to the first NMOS transistor Mn1And the drain of the fourth PMOS transistor Mp4Gate of (d), second NMOS transistor Mn2Is connected to the gate of a fourth PMOS transistor Mp4Is connected to the second NMOS transistor Mn2And serves as a signal output terminal of the delay unit;
first NMOS transistor Mn1Is connected to the third NMOS transistor Mn3Drain of (1), second NMOS transistor Mn2Is connected with the fourth NMOS transistor Mn4The enable signal EN is connected to the third NMOS transistor Mn3And the fourth NMOS transistor Mn4Is connected to the gate of the third NMOS transistor Mn3Is grounded, the fourth NMOS transistor Mn4Is grounded.
4. A time domain arithmetic circuit for a time-to-digital converter using the time register of any one of claims 1 to 3, characterized in that: the time domain arithmetic circuit comprises a time register 1 and a time register 2, wherein an input time signal A is connected with a time signal input end of the time register 1, a clock signal CLK1 is connected with a clock signal input end of the time register 1, an output end of the time register 1 is connected with a time signal input end of the time register 2, a clock signal CLK2 is connected with a clock signal input end of the time register 2, and an output end of the time register 2 outputs a time signal Y, so that the time domain arithmetic circuit with a time saving function is formed.
5. A time domain arithmetic circuit for a time-to-digital converter using the time register of any one of claims 1 to 3, characterized in that: the time domain arithmetic circuit comprises a time register 1, a time register 2, an OR gate and a delay module, wherein an input time signal A is connected with one input end of the OR gate, an input time signal B is connected with the input end of the delay module, the output end of the delay module is connected with the other input end of the OR gate, the output end of the OR gate is connected with the time signal input end of the time register 1, a clock signal CLK1 is connected with the clock signal input end of the time register 1, the output end of the time register 1 is connected with the time signal input end of the time register 2, a clock signal CLK2 is connected with the clock signal input end of the time register 2, and the output end of the time register 2 outputs a time signal Y.
6. A time domain arithmetic circuit for a time-to-digital converter formed by using the time register of any one of claims 1 to 3, comprising a time register 1, a time register 2, an or gate and a delay block, wherein an input time signal a is connected to a time signal input terminal of the time register 1, a clock signal CLK1 is connected to a clock signal input terminal of the time register 1, an output terminal of the time register 1 is connected to one input terminal of the or gate, an input time signal B is connected to an input terminal of the delay block, an output terminal of the delay block is connected to the other input terminal of the or gate, an output terminal of the or gate is connected to an input terminal of the time register 2, a clock signal CLK2 is connected to a clock signal input terminal of the time register 2, and an output terminal of the time register 2 outputs a time signal Y, thereby forming a time domain.
7. A time domain arithmetic circuit for a time-to-digital converter constituted by using the time register according to any one of claims 1 to 3, it is characterized by that it includes time register 1, time register 2, OR gate and delay module, the input time signal A is connected with one input end of OR gate, the output signal Y is connected with input end of delay module, the output end of delay module is connected with another input end of OR gate, the output end of the or gate is connected with the time signal input end of the time register 1, the clock signal CLK1 is connected with the clock signal input end of the time register, the output end of the time register 1 is connected with the time signal input end of the time register 2, the clock signal CLK2 is connected with the clock signal input end of the time register 2, and the output end of the time register 2 outputs the time signal Y, so that the time domain arithmetic circuit with the time integration function is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110133385.9A CN112445121B (en) | 2021-02-01 | 2021-02-01 | Time register and time domain operation circuit for time-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110133385.9A CN112445121B (en) | 2021-02-01 | 2021-02-01 | Time register and time domain operation circuit for time-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112445121A true CN112445121A (en) | 2021-03-05 |
| CN112445121B CN112445121B (en) | 2021-04-16 |
Family
ID=74740102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110133385.9A Active CN112445121B (en) | 2021-02-01 | 2021-02-01 | Time register and time domain operation circuit for time-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112445121B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020033725A1 (en) * | 2000-09-19 | 2002-03-21 | Mitsubishi Denki Kabushiki Kaisha | Clock generating circuit |
| CN101577549A (en) * | 2008-04-04 | 2009-11-11 | 英飞凌科技股份有限公司 | Multiple output time-to-digital converter |
| CN104300970A (en) * | 2014-09-28 | 2015-01-21 | 东南大学 | Voltage-control ring vibration type two-section type time digital conversion circuit based on DLL |
| US20150069994A1 (en) * | 2011-03-11 | 2015-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Timing Skew Characterization Apparatus and Method |
| CN205334926U (en) * | 2016-01-28 | 2016-06-22 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| CN106168753A (en) * | 2016-06-28 | 2016-11-30 | 中国科学院微电子研究所 | Time-to-digit converter |
| WO2019000373A1 (en) * | 2017-06-30 | 2019-01-03 | 深圳市大疆创新科技有限公司 | Circuit, method and related chip for time measurement, system, and device |
| CN210157160U (en) * | 2019-06-13 | 2020-03-17 | 珠海微度芯创科技有限责任公司 | Digital clock frequency multiplication circuit system |
| US10784874B1 (en) * | 2020-02-05 | 2020-09-22 | Intel Corporation | All-digital voltage monitor (ADVM) with single-cycle latency |
| US20200395849A1 (en) * | 2019-06-14 | 2020-12-17 | Arm Limited | Performance Regulation Techniques |
-
2021
- 2021-02-01 CN CN202110133385.9A patent/CN112445121B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020033725A1 (en) * | 2000-09-19 | 2002-03-21 | Mitsubishi Denki Kabushiki Kaisha | Clock generating circuit |
| CN101577549A (en) * | 2008-04-04 | 2009-11-11 | 英飞凌科技股份有限公司 | Multiple output time-to-digital converter |
| US20150069994A1 (en) * | 2011-03-11 | 2015-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Timing Skew Characterization Apparatus and Method |
| CN104300970A (en) * | 2014-09-28 | 2015-01-21 | 东南大学 | Voltage-control ring vibration type two-section type time digital conversion circuit based on DLL |
| CN205334926U (en) * | 2016-01-28 | 2016-06-22 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| CN106168753A (en) * | 2016-06-28 | 2016-11-30 | 中国科学院微电子研究所 | Time-to-digit converter |
| WO2019000373A1 (en) * | 2017-06-30 | 2019-01-03 | 深圳市大疆创新科技有限公司 | Circuit, method and related chip for time measurement, system, and device |
| CN210157160U (en) * | 2019-06-13 | 2020-03-17 | 珠海微度芯创科技有限责任公司 | Digital clock frequency multiplication circuit system |
| US20200395849A1 (en) * | 2019-06-14 | 2020-12-17 | Arm Limited | Performance Regulation Techniques |
| US10784874B1 (en) * | 2020-02-05 | 2020-09-22 | Intel Corporation | All-digital voltage monitor (ADVM) with single-cycle latency |
Non-Patent Citations (1)
| Title |
|---|
| 王磊 等: "脉冲式激光测距***中时间测量模块设计与实现", 《伊犁师范学院学报（自然科学版）》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112445121B (en) | 2021-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8030982B2 (en) | Systems and methods using improved clock gating cells | |
| CN107241098B (en) | Offset calibration circuit of comparator in asynchronous successive approximation type analog-to-digital converter | |
| CN101268616B (en) | Single threshold and single conductivity type logic | |
| CN102437836B (en) | Low-power-consumption pulse type D trigger | |
| JPH07326957A (en) | Cmos circuit | |
| EP1777818B1 (en) | Master-slave flip-flop, trigger flip-flop and counter | |
| CN105144579A (en) | Low power architectures | |
| CN114567297B (en) | D-flip-flop, processor and computing device including the same | |
| KR100922696B1 (en) | Clock based data storage element and dual pulse generation element and data storage element | |
| US20080001628A1 (en) | Level conversion circuit | |
| CN112445121B (en) | Time register and time domain operation circuit for time-digital converter | |
| CN110034762A (en) | A kind of adjustable analog-digital converter of sample frequency | |
| TWI428921B (en) | Charge pump and method for operating the same | |
| Sharma et al. | An area and power efficient design of single edge triggered D-flip flop | |
| CN105720948B (en) | A kind of clock control flip-flops based on FinFET | |
| Shaker et al. | A clock gated flip-flop for low power applications in 90 nm CMOS | |
| CN111445936A (en) | Wide voltage SRAM timing tracking circuit | |
| CN106788345A (en) | Using the ramp signal generator of electric resistance structure | |
| TWI685827B (en) | Shift register circuit and method of driving the same | |
| Bondoq et al. | A d-type flip-flop with enhanced timing using low supply voltage | |
| Shaker et al. | Novel clock gating techniques for low power flip-flops and its applications | |
| US8482333B2 (en) | Reduced voltage swing clock distribution | |
| Angelov et al. | Ring-oscillator-based timing generator for ultralow-power applications | |
| Sriram et al. | A novel dual edge triggered near-threshold state retentive latch design | |
| CN105577141B (en) | A kind of low power consumption high-precision oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20210305 Assignee: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS NANTONG INSTITUTE Co.,Ltd. Assignor: NANJING University OF POSTS AND TELECOMMUNICATIONS Contract record no.: X2021980011617 Denomination of invention: Time register and time domain operation circuit for time to digital converter Granted publication date: 20210416 License type: Common License Record date: 20211029 |
|
| EC01 | Cancellation of recordation of patent licensing contract | ||
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS NANTONG INSTITUTE Co.,Ltd. Assignor: NANJING University OF POSTS AND TELECOMMUNICATIONS Contract record no.: X2021980011617 Date of cancellation: 20230904 |