CN209823721U - Circuit for controlling signal overshoot of numerical control attenuator - Google Patents
Circuit for controlling signal overshoot of numerical control attenuator Download PDFInfo
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- CN209823721U CN209823721U CN201920224251.6U CN201920224251U CN209823721U CN 209823721 U CN209823721 U CN 209823721U CN 201920224251 U CN201920224251 U CN 201920224251U CN 209823721 U CN209823721 U CN 209823721U
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Abstract
The utility model relates to a circuit for controlling overshoot of numerical control attenuator signals, which comprises a radio frequency attenuation module, a drive control module and a logic control module, wherein the radio frequency attenuation module is formed by cascading a plurality of attenuation modules with different attenuation amounts, each attenuation module comprises a resistor and a control switch, and two working states, namely an attenuation state and a reference state, are provided; the logic control module outputs a control signal to the drive control module; the driving control module converts the control signal into an opposite phase control signal, and the combination of the working states of the attenuation modules is controlled through the opposite phase control signal to obtain different total attenuation quantities. The advantages are that: a driving control circuit is inserted between the logic control module and the radio frequency attenuation module, the problem of signal overshoot of the numerical control attenuator in the state switching process can be solved by changing the time delay of the rising edge and the falling edge of a control signal without adding an additional logic control circuit, and the circuit is simple in structure and obvious in effect.
Description
Technical Field
The utility model relates to a circuit for controlling overshoot of numerical control attenuator signal belongs to integrated circuit design technical field.
Background
With the rapid development of wireless communication technology, the prospect of wireless radio frequency application is better and better, especially the development of integrated circuit industry, the technological level is continuously promoted, and the miniaturization and integration of wireless transceiver modules become a trend. Research on wireless communication chips suitable for radio frequency bands has become a focus of attention. In the communication field, the amplitude of a signal received by a receiver in a receiving system can change along with the distance from a signal source, and a signal amplitude control module is required to be added in order to ensure that an internal channel is not blocked by a signal with overlarge amplitude; the transmitting power needs to be accurately adjusted in the transmitting system, and the gain can be accurately controlled by adding the amplitude control module in front of the power amplifier, so that the requirement of controllable transmitting power is met.
The attenuator can accurately control the signal amplitude, has low power consumption, high linearity and wide working bandwidth, and has wide application. The numerical control attenuator controls the on and off of each stage of switch by utilizing codes, selects a corresponding attenuation module and realizes the stepping or superposition of attenuation. However, signal overshoot occurs in the switching process of different attenuation amounts of the numerical control attenuator, namely, the attenuation amount of the numerical control attenuator is smaller than the initial value and the final set value in the switching process. When the amplitude of the signal overshoot is large and the duration is long during the switching process, the subsequent circuits, such as the filter in the receiving link and the power amplifier in the transmitting link, may be damaged, and the operational reliability of the system is greatly reduced.
Disclosure of Invention
The utility model provides a circuit for controlling overshoot of numerical control attenuator signal, its aim at to numerical control attenuator the problem that the signal overshoots appears in the decay state switching process, has provided a circuit that can be used to control overshoot of numerical control attenuator signal, changes load transistor's width to length ratio, can realize the time control that the signal rises along and descend the edge to solve the problem that the signal overshoots
The technical solution of the utility model is as follows:
the circuit for controlling the overshoot of the signal of the numerical control attenuator comprises a radio frequency attenuation module 101, a drive control module 102 and a logic control module 103, wherein the radio frequency attenuation module 101 is formed by cascading a plurality of attenuation modules with different attenuation amounts, each attenuation module comprises a resistor and a control switch, and the attenuation modules have two working states, namely an attenuation state and a reference state; the control signal output end of the logic control module 103 is connected with the control signal input end of the drive control module 102, and outputs a control signal D to the drive control module 102; the reverse phase control signal output end of the driving control module 102 is connected with the reverse phase control signal input end of the radio frequency attenuation module 101, the driving control module 102 converts the control signal D into reverse phase control signals CP and CN, and different total attenuation amounts are obtained by combining the working states of the attenuation modules controlled by the reverse phase control signals CP and CN.
The attenuation module comprises a series resistor R1, a parallel resistor R2, a series switch 201 and a parallel switch 202, the series resistor R1 and the series switch 201 are connected in parallel to form a series circuit, the parallel resistor R2 and the parallel switch 202 are connected in series to form a parallel circuit, one end of the parallel circuit is connected with the series circuit, and the other end of the parallel circuit is grounded;
the series switch 201 and the parallel switch 202 are respectively controlled by the inverted control signals CP and CN, when the control signal CP is at a high level and CN is at a low level, the series switch 201 is turned on, the parallel switch 202 is turned off, and at this time, the attenuation module is in a reference state; when the control signal CP is at a low level and CN is at a high level, the series switch 201 is turned off, the parallel switch 202 is turned on, and the attenuation module is in an attenuation state.
The series switch 201 is composed of a field effect transistor M17 and a grid electrode series resistor R3, the parallel switch 202 is composed of a field effect transistor M18 and a grid electrode series resistor R4, the grid electrode voltage change of the field effect transistor is consistent with the response of the control voltage change, and the total grid width and the grid electrode series resistor of the field effect transistors in different attenuation modules are in inverse proportion.
The driving control module 102 comprises an input single-ended-to-inverting circuit, a level shift circuit and an output driving circuit; the input end of the single-ended to inverting phase circuit is connected with the logic control module, the first output end is connected with the first input end of the level shift circuit, and the second output end is connected with the second input end of the level shift circuit, so that the single-ended input signal is converted into the inverting phase signal to be output.
The level shift circuit comprises a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M15 and an NMOS transistor M16. The gate of the PMOS transistor M9 is connected to the Vin _ P input port, and the drain is connected to the source of the PMOS transistor M10. The gate of the PMOS transistor M13 is connected to the input port Vin _ N, and the drain is connected to the source of the PMOS transistor M14. The drain of the NMOS transistor M11 is connected to the drain of the PMOS transistor M10, the source is connected to the drain of the NMOS transistor M12, and the gate is connected to the input Bias V _ Bias. The drain of the NMOS transistor M15 is connected to the drain of the PMOS transistor M14, the source is connected to the drain of the NMOS transistor M16, and the gate is connected to the input Bias V _ Bias. The gate of the NMOS transistor M12 is connected to the drain of the NMOS transistor M16, and the drain is connected to the gate of the PMOS transistor M16.
The output driving circuit comprises a PMOS transistor M1, a PMOS transistor M3, a PMOS transistor M5, a PMOS transistor M7, an NMOS transistor M2, an NMOS transistor M4, an NMOS transistor M6 and an NMOS transistor M8. The gate of the PMOS transistor M7 is connected to the input port Vin _ P, and the drain is connected to the gate of the PMOS transistor M5. The drain of the PMOS transistor M5 is connected to the output port Vout _ N, the drain of the NMOS transistor M6, and the gate is connected to the gate of the NMOS transistor M6. The gate of the NMOS transistor M8 is connected to the drain of the NMOS transistor M16, and the drain is connected to the source of the NMOS transistor M6. The gate of the PMOS transistor M3 is connected to the input port Vin _ N, and the drain is connected to the gate of the PMOS transistor M1. The drain of the PMOS transistor M1 is connected to the output port Vout _ P, the drain of the NMOS transistor M2, and the gate is connected to the gate of the NMOS transistor M2. The gate of the NMOS transistor M4 is connected to the drain of the NMOS transistor M12, and the drain is connected to the source of the NMOS transistor M2.
The level shift circuit carries out level shift on the inverted signal of the input end and inputs the inverted signal to a second input port of the driving circuit; the output driving circuit consists of input transistors M3, M4, M7 and M8 and load transistors M1, M2, M5 and M6 for controlling signal edges. Increasing the width-to-length ratio of the load transistors M1 and M5, i.e., decreasing the on-resistances of the load transistors M1 and M5, may decrease the time of the rising edge of the control signal. Increasing the width-to-length ratio of the load transistors M2 and M6, i.e., decreasing the on-resistances of the load transistors M1 and M5, may decrease the time for the control signal to fall.
The driving control module 102 changes rising and falling edges of the control signal, so that rising time of the control signal is longer than falling time, and thus time for the attenuation module to switch from the attenuation state to the reference state is longer than time for the attenuation module to switch from the reference state to the attenuation state.
The rf attenuation module 101 includes a 0.5dB attenuation module 110, a 1dB attenuation module 111, a 2dB attenuation module 112, a 4dB attenuation module 113, an 8dB attenuation module 114, and a 16dB attenuation module 115.
The utility model has the advantages that:
1) a driving control circuit is inserted between the logic control module and the radio frequency attenuation module, and the problem of signal overshoot of the numerical control attenuator in the state switching process is solved by changing the time delay of the rising edge and the falling edge of a control signal.
2) The overshoot problem of switching between any states can be solved without adding an additional logic control circuit, and the circuit is simple in structure and obvious in effect.
Drawings
FIG. 1 is a system block diagram of a numerical control attenuator
FIG. 2 is a schematic view of the structure of an attenuation module
FIG. 3 is a schematic circuit diagram of an attenuation module
FIG. 4 is a timing diagram of the switching of decay state one to decay state two
FIG. 5 is a timing diagram of the switching of decay state two to decay state one
FIG. 6 is a waveform of an output signal for state switching under control of a conventional control signal
FIG. 7 is a waveform of an output signal for state switching under the control of a driving control module
FIG. 8 is a schematic diagram of a level shift circuit and an output driver circuit
FIG. 9 is a schematic circuit diagram of a single-ended inverted signal conversion circuit
In the figure, 101 is a radio frequency attenuation module, 102 is a driving control module, 103 is a logic control module, 110, 111, 112, 113, 114, 115 is an attenuation module, D0, D1, D2, D3, D4, D5 are control signals, C0.5P, C1P, C2P, C4P, C8P, C16P, C0.5N, C1N, C2N, C4N, C8N, C16N are inverse control signals, R1, R2, R3 are resistors, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16 are field effect transistors.
Detailed Description
The technical scheme of the utility model is further explained by combining the attached drawings
As shown in FIG. 1, a block diagram of a 6-bit digital attenuator. The rf attenuation module 101 is formed by cascading attenuation modules with different attenuation amounts, such as a 0.5dB attenuation module 110, a 1dB attenuation module 111, a 2dB attenuation module 112, a 4dB attenuation module 113, an 8dB attenuation module 114, and a 16dB attenuation module 115. The attenuation module has two working states of an attenuation state and a reference state. The set total attenuation can be obtained by controlling the signal to select the combination of the working states of the attenuation modules. The logic control module 103 outputs the parallel control signals D0-D5 to the driving control module 102, and the driving control module 102 outputs the inverted control signals C0.5P, C0.5N, C1P, C1N, etc. to control the operation states of the attenuation module 110 and 115, respectively.
As shown in fig. 2, the schematic diagram of the 1dB attenuation module 111 is composed of a series resistor R1, a parallel resistor R2, a series switch 201 and a parallel switch 202. The series switch 201 and the parallel switch 202 are controlled by inverted control signals C1P, C1N, respectively. When the control signal C1P is at a high level and the control signal C1N is at a low level, the switch 201 is turned on and the switch 202 is turned off, and the attenuation module is at the reference state. When the control signal C1P is at a low level and the control signal C1N is at a high level, the switch 201 is turned off, the switch 202 is turned on, and the attenuation module is in an attenuation state with an attenuation value of 1 dB.
As shown in fig. 3, which is a schematic diagram of the circuit structure of the 1dB attenuation module 111, the series switch 201 is composed of a field effect transistor M17 and a gate series resistor R3, and the parallel switch 202 is composed of a field effect transistor M18 and a gate series resistor R4.
In one aspect, when the attenuation state is switched from the first attenuation state to the second attenuation state, the driving control module 102 changes the rising and falling edges of the control signal such that the rising time of the control signal is longer than the falling time, and thus the time for the attenuation module to switch from the attenuation state to the reference state is longer than the time for the attenuation module to switch from the reference state to the attenuation state. During the switching, the attenuation amount is an intermediate state greater than the attenuation initial state and the final state. Therefore, the reference state of the numerical control attenuator can not appear in the switching process of different attenuation states, and the signal overshoot of the numerical control attenuator in the switching process of different attenuation states is avoided. The drive control module controls the edge of the control signal, and signal overshoot in the state switching process can be controlled without an additional logic circuit.
On the other hand, the gate voltage changes of the field effect transistors in different attenuation modules need to be kept consistent in response to the control voltage changes. The overall gate width and gate series resistance of the field effect transistors in the different attenuation modules thus maintain an inverse relationship.
Take the example of switching the attenuation state between two states, 1dB and 2 dB. When the numerical control attenuator is in the attenuation state one, the total radio frequency attenuation is 1dB, the attenuation module 112 is in the reference state, the attenuation module 111 is in the attenuation state, the control signal D1 is at the high level, and the control signal D2 is at the low level; when the controllable attenuator is in the second attenuation state, the total rf attenuation is 2dB, the attenuation module 111 is in the reference state, the attenuation module 112 is in the attenuation state, and the control signal D2 is at the high level and D1 is at the low level.
As shown in fig. 4, during the process of switching the digitally controlled attenuator from the attenuation state one to the attenuation state two, the driving control module 102 converts the control signal D1 into the inverted control signals C1P and C1N, and converts the control signal D2 into the inverted control signals C2P and C2N. Before time t1, the control signal D1 is at a high level, the control signal D2 is at a low level, the control signal C1P is at a low level, the control signal C2P is at a high level, the attenuation module 111 is in an attenuation state, the attenuation module 112 is in a reference state, and the digital controlled attenuator is in an attenuation state one. At t1, the control signal D1 changes from high to low, the control signal D2 changes from low to high, the control signal C1P changes from low, and the control signal C2P changes from high to low. At this time, the attenuation module 111 and the attenuation module 112 are in an attenuation state at the same time, the numerical control attenuator is in an intermediate state, and the total attenuation of the numerical control attenuator is the sum of the attenuation state I and the attenuation state II. At t2, the control signal C1P is at a high level, the control signal C2P is at a low level, the attenuation module 111 is in a reference state, the attenuation module 112 is in an attenuation state, and the digitally controlled attenuator is in an attenuation state two. Between t1 and t2, the series switch of the attenuation module 111 is turned off, the parallel switch is turned off, the series switch of the attenuation module 112 is turned off, the parallel switch is turned off, and the digitally controlled attenuator is in an intermediate state. The total attenuation of the numerical control attenuator is a value between the first attenuation state and the second attenuation state.
As shown in fig. 5, during the process of switching from the attenuation state two to the attenuation state one, the driving control module 102 converts the control signal D1 into the inverted control signals C1P and C1N, and converts the control signal D2 into the inverted control signals C2P and C2N. Before time t1, the control signal D1 is at a low level, the control signal D2 is at a high level, the control signal C1P is at a high level, the control signal C2P is at a low level, the attenuation module 111 is in a reference state, the attenuation module 112 is in an attenuation state, and the digital controlled attenuator is in an attenuation state two. At t1, the control signal D1 changes from low to high, the control signal D2 changes from high to low, the control signal C2P changes from low, and the control signal C1P changes from high to low. At this time, the attenuation module 111 and the attenuation module 112 are in an attenuation state at the same time, the numerical control attenuator is in an intermediate state, and the total attenuation of the numerical control attenuator is the sum of the attenuation state I and the attenuation state II. At t2, the control signal C2P is at a high level, the control signal C1P is at a low level, the attenuation module 111 is in an attenuation state, the attenuation module 112 is in a reference state, and the digitally controlled attenuator is in an attenuation state one. Between t1 and t2, the parallel switch of the attenuation module 111 is turned off, the series switch is turned off, the parallel switch of the attenuation module 112 is turned off, the series switch is turned off, and the digitally controlled attenuator is in an intermediate state. At this time, the attenuation of the numerical control attenuator is a value between the first attenuation state and the second attenuation state.
In the process of switching the attenuation state I and the attenuation state II, the attenuation amount of the numerical control attenuator is not smaller than that of the attenuation amount of the numerical control attenuator in the initial state and the final state, so that signal overshoot is not generated in the state switching process.
As shown in fig. 6, is an output waveform of the attenuator state switching under the control of the conventional control signal. The time delay of the rising edge and the falling edge of the control signal is the same, at the moment, signal overshoot exists in the output signal, the length of the signal overshoot is 12ns, and the amplitude is 50 mV.
As shown in fig. 7, in order to change the delayed signal output waveform of the rising edge and the falling edge of the control signal, the delay of the rising edge of the control signal is 15ns slower than that of the falling edge. There is no signal overshoot in the output signal at this time.
As shown in FIGS. 8 and 9, a circuit schematic for changing the rising and falling edges of a control signal is implemented, which comprises a level shift circuit and a driving stage circuit, wherein the level shift circuit is used for converting the control signal of 0 ~ VDD input voltage into voltage output of VDD ~ VDD, inverted input signals Vin _ P and Vin _ N are input to the gates of field effect transistors M4 and M8 in the driving stage circuit through the level shift circuit, the driving stage circuit can provide certain driving capability for the latter stage circuit and can control the rising and falling edges of the output voltage, the gates of the field effect transistors M4 and M8 are connected to ground, when Vin _ N is high, M1 is turned on to operate in a linear region corresponding to a resistor, M2 is turned off, when Vout _ P is high, because the latter stage circuit of an attenuation module is a switching tube, the load of the switching tube can be equivalent to a turn-off capacitor of the switching tube when Vin _ N is changed from low to high, the response of the network is relatively large, the charge-off voltage of the output voltage of the switching tube is relatively small, the charge-off voltage of the charging network, the output voltage of the output resistor is changed from low voltage, the charge-discharge network, the charge-on voltage of the output resistor is changed relatively more quickly, the charge-on voltage of the output resistor, the output transistor is changed relatively slowly, the output resistor, the charge-on voltage of the output transistor is changed relatively short-on voltage of the output transistor, the output resistor, the charge-on voltage of the charge-transistor is changed relatively short-transistor, the charge-on voltage of the charge-transistor, the charge-on transistor, the charge-transistor, the.
Claims (5)
1. The circuit for controlling the overshoot of the signal of the numerical control attenuator is characterized by comprising a radio frequency attenuation module (101), a driving control module (102) and a logic control module (103), wherein the radio frequency attenuation module (101) is formed by cascading a plurality of attenuation modules with different attenuation amounts, and each attenuation module comprises a resistor and a control switch; the control signal output end of the logic control module (103) is connected with the control signal input end of the drive control module (102); the inverted control signal output end of the drive control module (102) is connected with the inverted control signal input end of the radio frequency attenuation module (101).
2. The circuit for controlling the overshoot of the signal of the digitally controlled attenuator according to claim 1, wherein the attenuation module comprises a series resistor (R1), a parallel resistor (R2), a series switch (201), and a parallel switch (202), the series resistor (R1) is connected in parallel with the series switch (201) to form a series circuit, the parallel resistor (R2) is connected in series with the parallel switch (202) to form a parallel circuit, and one end of the parallel circuit is connected to the series circuit and the other end is grounded.
3. A circuit for controlling the overshoot of a digitally controlled attenuator signal as claimed in claim 2, characterised in that the series switch (201) is comprised of a field effect transistor (M17) and a gate series resistor (R3), and the parallel switch (202) is comprised of a field effect transistor (M18) and a gate series resistor (R4).
4. The circuit for controlling the overshoot of the digitally controlled attenuator signal of claim 1, wherein the drive control block (102) comprises an input single-ended to inverting circuit, a level shifting circuit, and an output drive circuit; the input end of the single-ended to inverting circuit is connected with the logic control module, the first output end is connected with the first input end of the level shift circuit, and the second output end is connected with the second input end of the level shift circuit, so that a single-ended input signal is converted into an inverting signal to be output; the level shift circuit comprises a first PMOS transistor (M9), a second PMOS transistor (M10), a third PMOS transistor (M13) and a fourth PMOS transistor (M14), a first NMOS transistor (M11), a second NMOS transistor (M12), a third NMOS transistor (M15) and a fourth NMOS transistor (M16); wherein the gate of the first PMOS transistor (M9) is connected to the Vin _ P input port, the drain is connected to the source of the second PMOS transistor (M10), the gate of the third PMOS transistor (M13) is connected to the Vin _ N input port, the drain is connected to the source of the fourth PMOS transistor (M14), the drain of the first NMOS transistor (M11) is connected to the drain of the second PMOS transistor (M10), the source is connected to the drain of the second NMOS transistor (M12), the gate is connected to the V _ Bias input Bias, the drain of the third NMOS transistor (M15) is connected to the drain of the fourth PMOS transistor (M14), the source is connected to the drain of the fourth NMOS transistor (M16), the gate is connected to the V _ Bias input Bias, the gate of the second NMOS transistor (M12) is connected to the drain of the fourth NMOS transistor (M16), and the drain is connected to the gate of the fourth NMOS transistor (M16);
the output driving circuit comprises a fifth PMOS transistor (M1), a sixth PMOS transistor (M3), a seventh PMOS transistor (M5) and an eighth PMOS transistor (M7), a fifth NMOS transistor (M2), a sixth NMOS transistor (M4), a seventh NMOS transistor (M6) and an eighth NMOS transistor (M8); a gate of the eighth PMOS transistor (M7) is connected to the Vin _ P input port, a drain is connected to the gate of the seventh PMOS transistor (M5), a drain of the seventh PMOS transistor (M5) is connected to the Vout _ N output port, a drain of the seventh NMOS transistor (M6), a gate is connected to the gate of the seventh NMOS transistor (M6), a gate of the eighth NMOS transistor (M8) is connected to the drain of the fourth NMOS transistor (M16), a drain is connected to the source of the seventh NMOS transistor (M6), a gate of the sixth PMOS transistor (M3) is connected to the Vin _ N input port, a drain is connected to the gate of the fifth PMOS transistor (M1), a drain of the fifth PMOS transistor (M1) is connected to the Vout _ P output port, a drain of the fifth NMOS transistor (M2), a gate is connected to the gate of the fifth NMOS transistor (M2), a gate of the sixth NMOS transistor (M4) is connected to the drain of the second NMOS transistor (M12), the drain is connected to the source of the fifth NMOS transistor (M2).
5. The circuit for controlling the overshoot of the digitally controlled attenuator signal of claim 1, wherein the radio frequency attenuation module (101) comprises a 0.5dB attenuation module (110), a 1dB attenuation module (111), a 2dB attenuation module (112), a 4dB attenuation module (113), an 8dB attenuation module (114), and a 16dB attenuation module (115).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920224251.6U CN209823721U (en) | 2019-02-22 | 2019-02-22 | Circuit for controlling signal overshoot of numerical control attenuator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920224251.6U CN209823721U (en) | 2019-02-22 | 2019-02-22 | Circuit for controlling signal overshoot of numerical control attenuator |
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| CN209823721U true CN209823721U (en) | 2019-12-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112787722A (en) * | 2021-03-12 | 2021-05-11 | 苏州大学 | Self-adaptive dimming visible light communication system and modulation and demodulation method |
| CN113794463A (en) * | 2021-09-07 | 2021-12-14 | 西安博瑞集信电子科技有限公司 | Novel single-chip numerical control attenuator chip |
-
2019
- 2019-02-22 CN CN201920224251.6U patent/CN209823721U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112787722A (en) * | 2021-03-12 | 2021-05-11 | 苏州大学 | Self-adaptive dimming visible light communication system and modulation and demodulation method |
| CN113794463A (en) * | 2021-09-07 | 2021-12-14 | 西安博瑞集信电子科技有限公司 | Novel single-chip numerical control attenuator chip |
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Address after: 210016 No.166, zhengfangzhong Road, moling street, Jiangning District, Nanjing City, Jiangsu Province Patentee after: Nanjing Guobo Electronics Co.,Ltd. Address before: 210016 No.166, zhengfangzhong Road, moling street, Jiangning District, Nanjing City, Jiangsu Province Patentee before: NANJING GUOBO ELECTRONICS Co.,Ltd. |
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