CN208937875U - 阵列基板及具有该阵列基板的液晶显示装置 - Google Patents
阵列基板及具有该阵列基板的液晶显示装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 39
- 239000011229 interlayer Substances 0.000 claims description 8
- 239000010408 film Substances 0.000 description 61
- 239000011159 matrix material Substances 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 19
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
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Abstract
本实用新型涉及阵列基板、具有该阵列基板的液晶显示装置,能够提高开口率,获得高清或者高亮度的液晶显示装置。该阵列基板在基板之上具有:栅极配线;源极配线,其隔着绝缘膜与栅极配线正交;源极电极,其与源极配线连接;半导体层,其形成于源极电极的下层;漏极电极,其在半导体层之上与源极电极相对,具有延伸部;以及像素电极,其直接层叠于漏极电极的延伸部之上,漏极电极的延伸部的端边与像素电极的端边对齐。
Description
技术领域
本实用新型涉及构成液晶显示装置的阵列基板。
背景技术
液晶显示装置具有液晶层和一对基板,该一对基板是彼此相对而配置的,该液晶层设置在上述两个基板之间。一对基板中的一个形成有与液晶显示装置的像素对应的像素电极、将信号电压传送至像素电极的薄膜晶体管等开关元件、与开关元件连接的配线等,有时称为阵列基板或有源矩阵基板。另一个基板有时称为相对基板。
通常,作为形成在阵列基板之上的像素电极,由透过可见光的透明导电膜形成,作为材料,使用氧化铟锡(Indium-Tin-Oxide)、氧化铟锌(Indium-Zinc-Oxide)。另一方面,作为像素电极与薄膜晶体管之间的电连接部件,通常使用金属膜,但由于金属膜反射可见光,因此不会透过可见光。
近年来,就液晶显示装置而言,要求高清的画质,因此像素电极的尺寸也不得不变小,因此阵列基板的每个像素的透光量也会减少。或者,有时要求高亮度的液晶显示装置,因此,无论是哪种要求,为了确保显示所需的光量,都需要尽可能减小如上述的像素电极与薄膜晶体管之间的连接部件那样不透过可见光的区域,增加像素电极中的透光区域。
作为上述区域,还会举出薄膜晶体管的电极、将信号传送至薄膜晶体管的配线,但由于原本就存在对于电极、配线使用金属膜,以将电阻减小这样的背景,因此将上述区域缩小会导致电阻的增大,引起显示不良。
因此,想到了将由上述连接部件使像素电极中的透光面积减小的程度最小化的对策。在这里,通常就上述连接而言,已知有如下构造,即,使薄膜晶体管的漏极电极的一部分沿像素电极延伸而与像素电极直接层叠。(专利文献1)
专利文献1:日本特开2010-191410号公报
实用新型内容
在该构造中,漏极电极由金属膜形成,因此与像素电极层叠而连接的区域也不透过可见光。由此,像素的开口率降低。如果减少层叠的区域的面积则能够抑制开口率的降低,但另一方面,像素电极与漏极电极之间的电阻增大,有可能妨碍信号电位的传送。本实用新型的目的在于,在液晶显示装置中,通过将像素电极与漏极电极的连接构造、配置优化,从而提高开口率。
本实用新型的阵列基板在基板之上具有:栅极配线;源极配线,其隔着绝缘膜与所述栅极配线正交;源极电极,其与所述源极配线连接;半导体层,其形成于所述源极电极的下层;漏极电极,其在所述半导体层之上与所述源极电极相对,具有延伸部;以及像素电极,其直接层叠于所述漏极电极的延伸部之上,所述漏极电极的延伸部的端边与所述像素电极的端边对齐。
实用新型的效果
根据本实用新型,能够将像素电极与漏极电极的连接构造、配置优化,能够提高开口率,获得高清或者高亮度的液晶显示装置。
附图说明
图1是本实施方式1涉及的液晶显示面板的俯视图。
图2是有源矩阵基板的像素的俯视图,该有源矩阵基板构成本实施方式1涉及的液晶显示面板。
图3是沿图2中的A-A线的剖视图。
图4是有源矩阵基板的像素的俯视图,该有源矩阵基板构成本实施方式2涉及的液晶显示面板。
图5是沿图4中的B-B线的剖视图。
图6是有源矩阵基板的像素的剖视图。
图7是有源矩阵基板的像素的剖视图。
图8是有源矩阵基板的像素的剖视图。
图9是有源矩阵基板的像素的俯视图,该有源矩阵基板构成本实施方式3涉及的液晶显示面板。
标号的说明
1 基板
2 栅极配线
3 栅极绝缘膜
4 半导体层
4a 端边
5 漏极电极
5a 漏极电极延伸部
5b 端边
5c 端边
6 源极配线
6a 源极电极
7 像素电极
7a 端边
8 层间绝缘膜
9 公共电极
9a 狭缝
9b 开口部
10 抗蚀层
11 第二金属膜
12 第一透明导电膜
20 有源矩阵基板
30 相对基板
51 显示区域
52 边框区域
53 引出配线
54 栅极驱动电路
55 源极驱动电路
56 外部端子
120 液晶显示面板
具体实施方式
实施方式1.
下面,基于附图对本实用新型的实施方式进行详细说明。此外,本实用新型并不限定于以下的各实施方式。在图1中,示出本实用新型涉及的液晶显示面板的俯视图。
液晶显示面板120呈俯视观察时在有源矩阵基板20之上隔着液晶层而贴合有相对基板30的构造。相对基板30小于有源矩阵基板20,因此具有有源矩阵基板20露出的区域,但通常在该区域形成后述的驱动电路等。
以下,对有源矩阵基板20进行说明。有源矩阵基板20分成显示区域51和作为其周边区域的边框区域52,该显示区域51与液晶显示面板的显示画面对应。在显示区域51内,栅极配线2与源极配线6交叉,由这两种配线分割出的区域与像素对应。也可以说显示区域51由像素的集合体构成。与这两种配线连接的开关元件即薄膜晶体管(Thin FilmTransistor)TFT设置在各像素内,各TFT分别与各像素内的像素电极7连接。
在边框区域52延伸有与栅极配线2或源极配线6相连的引出配线53,引出配线53分别与栅极驱动电路54、源极驱动电路55连接。通常,这两个驱动电路和相对基板30如图所示不重叠。
相对电极(公共电极、共通电极)形成在显示区域51的整个面,通过外部端子56维持在共通电位。后面也会进行叙述,针对各像素,相同的共通电位与施加于各像素的像素电极的信号电压之差被施加于液晶层(未图示),由此对液晶分子进行驱动而在每个像素进行显示。
接下来,使用图2和图3,对本实用新型涉及的液晶显示面板的实施方式进行说明。图2是有源矩阵基板的像素的俯视图,该有源矩阵基板构成本实施方式1涉及的液晶显示面板。图3是沿图2中的A-A线的部位处的剖视图。
使用图2、图3,对有源矩阵基板20的基本构造和制造方法进行说明,然后,对与本实用新型的效果相关的构造进行说明。在玻璃基板、树脂基板等第1透明基板1之上形成沿第1方向而延伸的栅极配线2。栅极配线2由厚度100~500nm左右的Al、Mo、Ti、Cr、Ta、Cu等第一金属膜进行图案化而形成。以将栅极配线2覆盖的方式设置由氧化硅、氮化硅等绝缘膜构成的栅极绝缘膜3。
在栅极绝缘膜3之上,以至少一部分与栅极配线2重叠的方式,以100~300nm左右的膜厚形成有半导体层4,该半导体层4由硅、In-Ga-Zn-O等氧化物半导体材料构成。在栅极绝缘膜3的上层形成与栅极线2相交而沿第2方向延伸的源极配线6。多条栅极配线2和多条源极配线6相交而分割出的区域相当于像素。
源极配线6具有在半导体层4之上作为源极电极6a而延伸的区域。在半导体层4之上以与源极电极6a相对的方式形成有漏极电极5,源极电极6a与漏极电极5相对的区域也称为沟道区域。从漏极电极5延伸出后述的用于与像素电极连接的区域即漏极电极延伸部(漏极杆)5a。
源极电极6a和漏极电极5由厚度100~500nm左右的Al、Mo、Ti、Cr、Ta、Cu等金属膜、合金膜的单层或层叠构造即第二金属膜进行图案化而形成。虽然未图示,但在半导体层4由硅构成的情况下,也可以以夹持于半导体层4与漏极电极5之间的方式,形成在硅中添加了磷等杂质的欧姆层,在该情况下,需要将漏极电极5与源极电极6a相对的区域即沟道区域之上的欧姆层去除。由以上的要素构成开关元件即薄膜晶体管TFT。
在薄膜晶体管TFT之上,像素电极7设置为对应于每个像素而配置成矩阵状。在图2中,以反映出像素形状的矩形形状的图案一部分凸出的形状图示出各像素电极7。各像素电极7由膜厚50~150nm左右的第一透明导电膜构成,形成为俯视观察时至少一部分与漏极电极5重叠。作为透明导电膜的材料,也可以使用ITO(Indium-Tin-Oxide)、IZO(Indium-Zinc-Oxide)。
在这里,与后述的制法也有关,但漏极电极5和漏极电极延伸部5a仅形成在像素电极7和半导体层4这两者都存在的区域。换言之,漏极电极5和漏极电极延伸部5a在像素电极7与半导体层4重叠的区域以由两者从上层和下层夹持的方式形成。
以将薄膜晶体管TFT、像素电极7覆盖的方式,形成有层间绝缘膜8。作为层间绝缘膜8,也可以使用氧化硅、氮化硅等无机绝缘膜。
在层间绝缘膜8之上,以俯视观察时与各像素电极7重叠的方式形成有公共电极9。公共电极9由膜厚50~150nm左右的第二透明导电膜构成,作为透明导电膜的材料,也可以使用ITO(Indium-Tin-Oxide)、IZO(Indium-Zinc-Oxide)。并且,如前所述,公共电极9形成在显示区域51内的大致整个面,但在各像素处形成有狭缝9a和TFT之上的开口部9b。
狭缝9a和开口部9b是未形成公共电极9的区域,在上述区域,作为基底的层间绝缘膜8露出。在图2中,图示出在除狭缝9a、开口部9b以外的区域,公共电极9扩展至整个面的形态。
并且,以将公共电极9覆盖的方式,形成有用于使液晶分子取向的取向膜(未图示)。此外,在相对基板30,在与液晶层接触侧也形成有取向膜。
图2和图3中图示出的阵列构造是FFS(Fringe Field Switching)方式的一个形态,但在FFS方式中,通过在狭缝9a的边缘部,在各像素电极7与公共电极9之间产生的边缘电场,使液晶层的液晶分子得到驱动而进行各像素的显示。因此,在各像素,在像素电极7与公共电极9重叠的区域透过的可见光有助于显示。
接下来,对图2和图3示出的阵列构造的制造方法进行说明。在透明基板1之上使用溅射等而将第一金属膜成膜,通过图案化而形成栅极配线2、栅极配线2与栅极驱动电路54之间的引出配线53。然后,通过等离子体CVD连续地将栅极绝缘膜3、半导体膜4成膜,接下来,使用溅射等将第二金属膜11成膜。
然后,在图6中,示出在经过照相制版工序之后,将半导体膜4和第二金属膜11进行图案化之后的剖面构造。在图6中,半导体膜4形成为所期望的图案,但针对第二金属膜11,尚未将源极电极6a和漏极电极5分离。
接下来,在图7中,示出使用溅射等而将第一透明导电膜12成膜,利用照相制版工序通过图案化而形成了抗蚀层10时的剖面构造。将第一透明导电膜12覆盖的抗蚀图案10的形成区域在显示区域内,与源极配线6、源极电极6a、漏极电极5、漏极电极延伸部5a、像素电极7等的形成区域对应。
特别地,在形成漏极电极延伸部5a的区域存在半导体膜4与第二金属膜11的层叠图案,但在实施方式1中,在后述的蚀刻之后,以该层叠图案的端部侧面和第一透明导电膜12的端部侧面在俯视观察时大体对齐的方式形成有抗蚀层10。
然后,通过将从抗蚀层10露出的透明导电膜11进行蚀刻去除,从而形成像素电极7。并且,通过将露出的第二金属膜11进行蚀刻去除,从而通过图案化而形成源极电极6a、漏极电极5、漏极电极延伸部5a。
在这里,在漏极电极延伸部5a,半导体膜4与第二金属膜11、第一透明导电膜12的端部侧面彼此对齐。并且,利用上述制法,能够通过两次照相制版工序实现半导体层4、第二金属膜11、第一透明导电膜12这3层的图案化。
然后,通过等离子体CVD形成层间绝缘膜8,开设所需的接触孔。然后,将第二透明导电膜成膜,利用照相制版工序通过图案化而形成公共电极9。
接下来,对与本实用新型的效果相关的构造进行说明。在本实用新型的构造中,漏极电极延伸部5a中最远离像素电极7中央的边、换言之与栅极配线2最近的漏极电极延伸部的端边5b在俯视观察时与像素电极7中最靠近栅极配线2的端边7a大体对齐。以往,与漏极电极延伸部的端边5b相比,像素电极7的端边7a配置得更靠近栅极配线2,因此与此对应地漏极电极延伸部5a配置在像素中央部的方向。但是,通过设为本实用新型这样的配置,从而能够使漏极电极延伸部5a与以往相比更靠近栅极配线2,由此能够在像素电极7处增加透过可见光的区域。
实施方式2.
使用图4和图5,对本实用新型涉及的液晶显示面板的实施方式进行说明。图4是有源矩阵基板的像素的俯视图,该有源矩阵基板构成本实施方式2涉及的液晶显示面板。图5是沿图4中的B-B线的部位处的剖视图。
在实施方式2中,与实施方式1不同之处仅在于漏极电极延伸部5a,因此对其进行说明。在图4、5中,漏极电极延伸部的端边5b与像素电极7的端边7a的侧面大体对齐这一点与实施方式1相同。不同之处在于,下层的半导体膜4从漏极电极延伸部5a朝向栅极配线2侧伸出。
在实施方式1中,由于电阻低的漏极电极延伸部5a靠近栅极配线2,因此两者之间的电容增大,有可能对信号传送造成影响。但是,在实施方式2中,与栅极配线最近的区域是高电阻的半导体层4,因此能够抑制寄生电容的增大。因此,与实施方式1相比,实现能够使漏极电极延伸部更近地靠近栅极配线2的效果。
接下来,对图4、5所示的实施方式2涉及的构造的制造方法进行说明。直至在实施方式1中说明的图6为止,在实施方式2中也是相同的,因此对这之后的制造工序进行说明。如此前所说明的那样,在图6中,半导体膜4形成为所期望的图案,但对于第二金属膜11,是源极电极6与漏极电极5尚未分离的状况。
在实施方式1中,在图6中示出的构造之后的照相制版工序中,转变为图7中示出的构造,但在实施方式2中,转变为图8中示出的构造。图7与图8的不同是将第一透明导电膜12覆盖的抗蚀层10的形成区域。在形成漏极电极延伸部5a的区域,形成有第二金属膜11与半导体膜4的层叠图案,但实施方式2中的抗蚀层10没有完全将该层叠图案覆盖。因此,在接下来进行的第一透明导电膜12与第二金属膜11的蚀刻之后,半导体层4的端边和漏极电极延伸部的端边5b在俯视观察时并未对齐,其结果,成为如图4所示俯视观察时半导体层4伸出的构造。
在实施方式1中,漏极电极延伸部与以往相比更靠近栅极配线2侧,由此根据图案配置的精度,有可能会过度靠近栅极配线2,与栅极配线2之间的寄生电容增大,从而导致信号传送的延迟化。但是,在实施方式2中,与栅极配线最近的区域是高电阻的半导体层4,因此能够抑制寄生电容的增大。因此,与实施方式1相比,实现能够使漏极电极延伸部更近地靠近栅极配线2的效果。
实施方式3.
使用图9,对本实用新型涉及的液晶显示面板的实施方式进行说明。图9是有源矩阵基板的像素的俯视图,该有源矩阵基板构成本实施方式3涉及的液晶显示面板。就图9所示的漏极电极延伸部5a而言,被像素电极7覆盖侧的端边5c不是直线,被加工成锯齿状的凹凸的方式。在图中图示出的是呈锯齿形的形态,但只要是凹凸形状即可,不限于此,也可以包含曲线。
通过设为上述形状,像素电极7将漏极电极延伸部5a覆盖的距离延长而提高包覆性,因此像素电极7与漏极电极5的电连接电阻减少。由此,实现能够改善信号电位向像素电极7的传送这样的效果。此外,图9中示出的形状也能够应用于实施方式1的构造。
此外,在本实用新型的实施方式中,将FFS型的有源矩阵基板作为例子进行了说明,但并不限定于该形态。也能够适用于如下的液晶显示面板,该液晶显示面板使用了公共电极形成在相对基板30之上的所谓TN型的有源矩阵基板。也能够适用于顶栅型薄膜晶体管。另外,在相对基板30通常形成RGB、RGBW等多个颜色的滤色器,但也可以在有源矩阵基板之上形成滤色器。
就实施方式1~3中说明的液晶显示面板而言,通过将偏光板贴于其两面,安装驱动电路,与具有LED等光源、反射片材的背光组合,由此构成液晶显示模块,通过进一步组装至框体内、进行连接,由此构成液晶显示装置。
Claims (6)
1.一种阵列基板,其特征在于,
在基板之上具有:
栅极配线;
源极配线,其隔着绝缘膜与所述栅极配线正交;
源极电极,其与所述源极配线连接;
半导体层,其形成于所述源极电极的下层;
漏极电极,其在所述半导体层之上与所述源极电极相对,具有延伸部;以及
像素电极,其直接层叠于所述漏极电极的延伸部之上,
所述漏极电极的延伸部的端边与所述像素电极的端边对齐。
2.根据权利要求1所述的阵列基板,其特征在于,
在所述漏极电极的延伸部,所述半导体层伸出至未被像素电极覆盖的端边之外。
3.根据权利要求1或2所述的阵列基板,其特征在于,
在所述漏极电极的延伸部,被像素电极覆盖的端边为锯齿状或凹凸形状。
4.根据权利要求1或2所述的阵列基板,其特征在于,
具有将所述源极配线、所述像素电极覆盖的层间绝缘膜,
在所述层间绝缘膜之上具有以与所述像素电极重叠的方式形成的公共电极。
5.根据权利要求3所述的阵列基板,其特征在于,
具有将所述源极配线、所述像素电极覆盖的层间绝缘膜,
在所述层间绝缘膜之上具有以与所述像素电极重叠的方式形成的公共电极。
6.一种液晶显示装置,其具有:
权利要求1至5中任一项所述的阵列基板。
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JP4551049B2 (ja) * | 2002-03-19 | 2010-09-22 | 三菱電機株式会社 | 表示装置 |
JP5646162B2 (ja) * | 2009-01-23 | 2014-12-24 | 三菱電機株式会社 | 薄膜トランジスタアレイ基板、その製造方法、及び液晶表示装置 |
KR101768615B1 (ko) * | 2010-08-12 | 2017-08-17 | 엘지디스플레이 주식회사 | 액정표시장치용 어레이기판 및 그 제조방법 |
US8760595B2 (en) * | 2011-09-09 | 2014-06-24 | Lg Display Co., Ltd. | Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same |
JP5907697B2 (ja) * | 2011-11-09 | 2016-04-26 | 三菱電機株式会社 | 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 |
JP6112886B2 (ja) * | 2013-02-01 | 2017-04-12 | 三菱電機株式会社 | 薄膜トランジスタアレイ基板およびその製造方法 |
JP6278633B2 (ja) * | 2013-07-26 | 2018-02-14 | 三菱電機株式会社 | 薄膜トランジスタアレイ基板およびその製造方法、並びに、液晶表示装置およびその製造方法 |
JP2015114568A (ja) | 2013-12-13 | 2015-06-22 | 三菱電機株式会社 | 液晶表示パネルおよび液晶表示装置 |
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US10444584B2 (en) | 2019-10-15 |
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US20190033674A1 (en) | 2019-01-31 |
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