CN208508966U - More light network interface communication equipments based on FPGA - Google Patents
More light network interface communication equipments based on FPGA Download PDFInfo
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- CN208508966U CN208508966U CN201821411248.7U CN201821411248U CN208508966U CN 208508966 U CN208508966 U CN 208508966U CN 201821411248 U CN201821411248 U CN 201821411248U CN 208508966 U CN208508966 U CN 208508966U
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Abstract
The utility model relates to a kind of, and more light network interface communication equipments based on FPGA are used to communicate with wall or process layer set on digital relay protection tester.More light network interface communication equipments of FPGA include: FPGA module, at least two MAC chips are integrated with, for realizing the function of ethernet mac layer；Ports physical module, including at least two independent PHY chips, each PHY chip connect one to one with the MAC chip respectively, to realize the physical link function of Ethernet；At least two optical modules are communicated to connect with each independent PHY chip difference piece, for the optical signal received from process layer or bay device to be converted to electric signal transmission to the ports physical module；Clock module, for providing clock signal to the FPGA module and the PHY chip.The light network interface quantity of the utility model is easy to extend and cut out, and real-time communication and dispersion are increased to Nano grade.
Description
Technical field
The utility model relates to the communication equipments for digital relay protection tester, are based on more particularly to one kind
The more light network interface communication equipments of FPGA.
Background technique
With the development of smart grid, the construction step of digital transformer substation is getting faster, and IEC61850 specification is in China
It is widely used, the digital transformer substation of this standard also occurs, saying in station is to have information by digital transformer substation
Digitlization is carried out, is carrier by network, builds communications platform and realize the sharing functionality of information, is realized between advanced application
Mutually interaction.Digital transformer substation uses electronic mutual inductor and intelligent terminal, is connect by optical fiber with protection, measuring device.
Therefore to the network hardware, more stringent requirements are proposed.
Since protection and test device propose increasingly higher demands, the report such as SMV, GOOSE, IEEE1588 to network interface quantity
Text is all to walk optical-fiber network, and test equipment, which can be also followed by, digital test instrument occurs, and optical port quantity is also in the continuous improvement.Tradition
Mode CPU usually only integrates one to two MAC cores, much can not meet the demand of Digitized transformation station equipment, while also meeting
The not demand of digital relay protection tester, even if by extension so that CPU energy band multi-path network port, but due to CPU's
Multitask is temporally dispatched, so seeming insufficient in terms of real-time and Multi-netmouth synchronism.
Utility model content
Based on this, it is necessary to not be able to satisfy the demand of digital transformer substation equipment, and transmission signal for network interface quantity
Real-time and Multi-netmouth synchronism deficiency problem, provide a kind of based on the more light network interface communication equipments of FPGA.
A kind of more light network interface communication equipments based on FPGA are set to digital relay protection tester, which is characterized in that institute
The more light network interface communication equipments based on FPGA stated include:
FPGA module is integrated at least two MAC chips, for realizing the function of ethernet mac layer；
Ports physical module, including at least two independent PHY chips, each PHY chip respectively with the MAC chip
It connects one to one, to realize the physical link function of Ethernet；
At least two optical modules, with each independent PHY core difference piece communication connection, being used for will be from process layer or interval
The optical signal that layer equipment receives is converted to electric signal transmission to the ports physical module；
The ports physical module can also be communication equipment dosage；
Clock module, for providing clock signal to the FPGA module and the PHY chip.
Above-mentioned more light network interface communication equipments based on FPGA solve light network interface quantity and are easy to extend and cut out, and communication is real-time
Property and dispersion are increased to nanosecond rank.
The clock module includes: in one of the embodiments,
The high stability crystal oscillator of clock source is provided；
The clock distributor being connected with the high stability crystal oscillator, the clock for being provided according to the high stability crystal oscillator
The source clock signal synchronous with each independent PHY chip offer to the FPGA module.
The clock distributor is 5PB1106PGGI chip in one of the embodiments,.
The MAC chip is connected by MII or RGMII interface with the PHY chip in one of the embodiments,.
It is integrated with high speed SERDES interface in each independent PHY chip in one of the embodiments, and passes through institute
High speed SERDES interface is stated directly to communicate to connect with the optical module.
Each independent PHY chip is 88EXXX chip in one of the embodiments,.
The optical module is hot-swappable module in one of the embodiments,.
The FPGA module is also connect with CPU by PCIE interface direct communication in one of the embodiments,.
The FPGA module is A7 chip in one of the embodiments,.
Detailed description of the invention
Fig. 1 is based on the more light network interface communication equipment schematic diagrames of FPGA；
Fig. 2 is to distribute schematic diagram based on the clock in the more light network interface communication equipments of FPGA.
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
The technical solution of the utility model embodiment is clearly and completely described in the attached drawing of type embodiment.Obviously, described
Embodiment is a part of the embodiment of the utility model, instead of all the embodiments.Based on described the utility model
Embodiment, those of ordinary skill in the art's every other embodiment obtained under the premise of being not necessarily to creative work, all belongs to
In the range of the utility model protection.
The utility model is used in the communication equipment in the digital relay protection tester in digital transformer substation, number
Changing relay-protection tester can transmit messages text to the equipment of wall, and the message that can also be come out with collection process layer equipment analyze it
Correctness.Since the protection and measuring device that are in wall propose increasingly higher demands, Digitized transformation to network interface quantity
The message data stood is transmitted by optical fiber, accordingly for the communication equipment network interface number in digital relay protection tester
The requirement of amount is also increasing.In digital transformer substation, it is carrier by network, builds communications platform, and realize being total to for information
Function is enjoyed, realizes the mutual interaction of each equipment room.It is received in the communication equipment of digital relay protection tester or output is logical
Letter data is the physical medium of MAC layer connection physical layer in the lower half portion by seven layer protocol data link layer of OSI come real
Existing.The communication equipment of traditional approach is that one to two MAC cores are integrated by CPU, by corresponding ports physical module with
Optical module is connected, and much can not meet the demand of Digitized transformation station equipment, even if can not meet data demand by extension,
But the multitask time-division processing characteristic of CPU, cause the message of digital transformer substation real-time, synchronization cannot export and is filled to protection
It sets.
As shown in Figure 1, a kind of more light network interface communication equipments based on FPGA, are set to digital relay protection tester, it should
More light network interface communication equipments based on FPGA include: FPGA module 100, ports physical module 200, at least two optical modules 300
And clock module 400.
In the present embodiment, in FPGA module 100, at least integrated there are two MAC modules, in the present embodiment, MAC module
For MAC chip 101.The quantity of MAC integrated chip can according to the demand of light network interface quantity by the setting to FPGA module 100 come
It realizes the increase and decrease of light network interface quantity, can satisfy the protection and measurement of wall to realize that light network interface quantity is easy to extend and cut out
Demand of the device to digitlization relay-protection tester network interface.Ports physical module 200, including at least two independent PHY cores
Piece 201, each independent PHY chip 201 connect one to one with MAC chip 101 respectively, to realize the physical link function of Ethernet
Energy.Independent 201 quantity of PHY chip is identical as 101 quantity of MAC chip integrated in FPGA module 100.The independent PHY of multi-disc
Chip 201, transmitting data in parallel is to realize its real-time.At least two optical modules 300 are communicated with each independent PHY chip 201
Connection, gives ports physical module for the optical signal received from process layer or bay device to be converted to electric signal transmission
200.Clock module 400, for providing clock signal to FPGA module 100 and each independent PHY chip 201.
As shown in Fig. 2, clock module 400 further includes high stability crystal oscillator 401 and clock distributor 402.Clock module 400
It is communicated to connect respectively with FPGA module 100 and each independent PHY chip 200.High stability degree crystal oscillator 401 gives ports physical simultaneously
Each independent PHY chip 201 and FPGA module 100 in module 200 provide a stabilization, reliable clock source.Clock point
Sending out device 402 can be 1 point 2,1 point 4,1 point 8 etc., provides identical clock source to multiple and different modules.
In the present embodiment, high stability crystal oscillator 401 provides the clock source that frequency is 25MHz.Inside each PHY chip
Frequency multiplication or frequency divider show that the high frequency oscillation signal of 125MHz, counter reach the resolution of 8ns according to 25MHz clock source
Power.It is 100MHz that 25MHz clock source is accompanied frequency by 100 inside of FPGA module, and counter can reach 10ns resolving power.Keep message real-time
Property and dispersion be increased to nanosecond rank, increase communication equipment in digital relay protection tester and receive message data
Speed, the efficiency of raising.
In the present embodiment, clock distributor 402 can determine to mention high stability crystal oscillator 401 according to the quantity of light network interface
The clock source of confession is distributed extension, provides to FPGA module 100 and each independent PHY chip respectively and comes from the same clock source
Clock signal, with ensure the road Liao Mei message data receive clock and 100 clock of FPGA module stringent synchronization, to ensure that
The synchronism of communication equipment.
As shown in Fig. 2, in the present embodiment, clock distributor 402 is 5PB1106PGGI chip, high stability crystal oscillator 401
For M11A-R319-25.00MHz.The pin of the clkin of the output pin and clock distributor 402 of high stability crystal oscillator 401
It is connected, clock distributor 402 is distributed by Y0-Y5 pin gives FPGA module 100 and each independence at 6 identical clock sources
PHY chip.
In the present embodiment, at least two MAC chips integrated in FPGA module 100 pass through MII or RGMII interface and phase
The SGMII interface of corresponding each independent PHY chip is connected.MAC chip passes through MII interface and PHY chip to realize rate
The data exchange of 100M, MAC chip side, which is connect by TXD [3:0] with PHY chip side, realizes that data, MAC chip side pass through RXD
[3:0] is connect with PHY chip side realizes data receiver；MAC chip passes through RGMII interface and PHY chip to realize rate
The data of 1000M, exchange MAC chip side, which is connect by TXD [3:0] with PHY chip side, realizes that data, MAC chip side pass through RXD
[3:0] is connect with PHY chip side realizes data receiver.
In the present embodiment, it is integrated with high speed SERDES interface in each independent PHY chip 201, and passes through high speed
SERDES interface is directly communicated to connect with optical module 300, realizes 1000Base-X sonet standard.
In the present embodiment, each independent PHY chip is the Alaska series 88XXX chip of Marvell company, the chip
Support 10M, 100M, 1000M rate supports a variety of MAC interface modes, there is GMII/MII, RGMII, SGMII etc..
In the present embodiment, FPGA module 100 is also connect with CPU by PCIE interface direct communication, does not need to pass through storage
Storage, the message data that FPGA module 100 is received from physical port module 200 directly carry out data interaction, real-time with CPU
It is higher.
In the present embodiment, FPGA module 100 is the A7 chip of XILINX company.For FPGA module 100 and MAC chip
Versatility and stability, it is preferred that the core that FPGA manufacturer that the core in MAC chip 101 also uses provides.
In the present embodiment, it is used in the communication apparatus of digital relay protection tester, during the work time, firstly,
The quantity that the setting selection inside FPGA module 100 needs optical module 300 is first passed through, corresponding optical module 300 is allowed to devote oneself to work.
When receiving data, more optical modules 300 are converted into received data by optical signal being transferred to port object after electric signal
Each independent PHY chip 201 being connect in reason module 200 with corresponding optical module 300, then be transferred to by each independent PHY chip 201
The MAC chip being integrated in FPGA module is corresponded, then the synchronous PCIE interface that passes through of the multiple data received is directly passed
It is defeated by CPU, to guarantee the timeliness of CPU processing data.
When sending data, a plurality of data are directly transferred to the MAC core being integrated in FPGA module via PCIE interface by CPU
Piece, each MAC chip transfer data to corresponding each independent PHY chip 201 in ports physical module 200 respectively, then by each
Independent PHY chip 201 is transferred to each corresponding optical module 300, by optical module 300 by the data received by electric signal again
Optical signal is converted into send through optical fiber.
When communication apparatus receives data and sends data, by high stability crystal oscillator 401 and clock distributor 402 to
FPGA module 100 and each independent PHY chip provide accurately, stablize and the clock signal of stringent synchronization is ensure that every is come
From the synchronism of the data of optical module 300.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
Above-described embodiments merely represent several embodiments of the utility model, the description thereof is more specific and detailed,
But it cannot be understood as the limitations to utility model patent range.It should be pointed out that for the common skill of this field
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
The protection scope of the utility model.Therefore, the scope of protection shall be subject to the appended claims for the utility model patent.
Claims (9)
1. a kind of more light network interface communication equipments based on FPGA, be set to digital relay protection tester, it is characterized in that, institute
The more light network interface communication equipments based on FPGA stated include:
FPGA module is integrated at least two MAC chips, for realizing the function of ethernet mac layer；
Ports physical module, including at least two independent PHY chips, each PHY chip respectively with the MAC chip one by one
It is correspondingly connected with, to realize the physical link function of Ethernet；
At least two optical modules are communicated to connect with each independent PHY chip, respectively for that will set from process layer or wall
The standby optical signal received is converted to electric signal transmission to the ports physical module；
Clock module, for providing clock signal to the FPGA module and the PHY chip.
2. more light network interface communication equipments according to claim 1 based on FPGA, which is characterized in that the clock module packet
It includes:
The high stability crystal oscillator of clock source is provided；
The clock distributor being connected with the high stability crystal oscillator, clock source for being provided according to the high stability crystal oscillator to
The FPGA module clock signal synchronous with each independent PHY chip offer.
3. more light network interface communication equipments according to claim 2 based on FPGA, which is characterized in that the clock distributor
For 5PB1106PGGI chip.
4. more light network interface communication equipments according to claim 1 based on FPGA, which is characterized in that the MAC chip is logical
Spend being connected for MII or RGMII interface and the PHY chip.
5. more light network interface communication equipments according to claim 1 based on FPGA, which is characterized in that described each independent
It is integrated with high speed SERDES interface in PHY chip, and is directly communicated with the optical module by the high speed SERDES interface
Connection.
6. more light network interface communication equipments according to claim 1 based on FPGA, which is characterized in that described each independent
PHY chip is 88EXXX chip.
7. more light network interface communication equipments according to claim 1 based on FPGA, which is characterized in that the optical module is heat
Plug module.
8. more light network interface communication equipments according to claim 1 based on FPGA, which is characterized in that the FPGA module is also
It is connect with CPU by PCIE interface direct communication.
9. more light network interface communication equipments according to claim 1 based on FPGA, which is characterized in that the FPGA module is
A7 chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821411248.7U CN208508966U (en) | 2018-08-30 | 2018-08-30 | More light network interface communication equipments based on FPGA |
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| CN201821411248.7U CN208508966U (en) | 2018-08-30 | 2018-08-30 | More light network interface communication equipments based on FPGA |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113945866A (en) * | 2021-12-14 | 2022-01-18 | 北京中铁建电气化设计研究院有限公司 | Testing device and testing method for multiple types of transmission lines |
| CN115065436A (en) * | 2022-08-16 | 2022-09-16 | 南方电网数字电网研究院有限公司 | Clock shunt multiplexing circuit special for electric power |
| CN115208805A (en) * | 2022-07-01 | 2022-10-18 | 中国电子科技集团公司第五十四研究所 | System and method for testing multi-path Ethernet physical layer transceiver |
-
2018
- 2018-08-30 CN CN201821411248.7U patent/CN208508966U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113945866A (en) * | 2021-12-14 | 2022-01-18 | 北京中铁建电气化设计研究院有限公司 | Testing device and testing method for multiple types of transmission lines |
| CN115208805A (en) * | 2022-07-01 | 2022-10-18 | 中国电子科技集团公司第五十四研究所 | System and method for testing multi-path Ethernet physical layer transceiver |
| CN115065436A (en) * | 2022-08-16 | 2022-09-16 | 南方电网数字电网研究院有限公司 | Clock shunt multiplexing circuit special for electric power |
| CN115065436B (en) * | 2022-08-16 | 2022-11-25 | 南方电网数字电网研究院有限公司 | Clock shunt multiplexing circuit special for electric power |
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| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230823 Address after: 510000 No. 75, Meihua Road, Yuexiu District, Guangzhou City, Guangdong Province (office building only) Patentee after: ELECTRICAL POWER DISPATCHING & CONTROL CENTER OF GUANGDONG POWER GRID Co.,Ltd. Address before: 510030 No. 75, Meihua Road, Yuexiu District, Guangzhou City, Guangdong Province (for office building functions only) Patentee before: ELECTRICAL POWER DISPATCHING & CONTROL CENTER OF GUANGDONG POWER GRID Co.,Ltd. Patentee before: GUANGDONG ONLLY ELECTRICAL & AUTOMATION CO.,LTD. |
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| TR01 | Transfer of patent right |