CN102594454A - Universal interface method for 10 GEPON (Gigabit Passive Optical Network) or XG-PON (XG-Passive Optical Network) OLT (Optical Line Terminal) or ONU (Optical Network Unit) SERDES (Serializer-Deserializer) - Google Patents
Universal interface method for 10 GEPON (Gigabit Passive Optical Network) or XG-PON (XG-Passive Optical Network) OLT (Optical Line Terminal) or ONU (Optical Network Unit) SERDES (Serializer-Deserializer) Download PDFInfo
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Abstract
The invention relates to the field of fibre-optical communication, in particular to a universal interface method for 10 GEPON (Gigabit Passive Optical Network) or XG-PON OLT (XG-Passive Optical Network) or ONU (Optical Network Unit) SERDES (Serializer-Deserializer). The method comprises the following two steps of: defining an interface function and designing a universal SERDES interface module according to the defining of the interface function, wherein the interface function is specifically defined by the following steps of: defining interface signals of 10 GEPON and XG-PON system multiplexing, and all the signals are 10 GEPON system and XG-PON system multiplexing; in the designing of the universal SERDES interface module according to the defining of the interface function, dividing all circuit units into a receiving side circuit, a sending side circuit, a loopback and detection circuit as well as a serial control interface circuit according to the defining of the interface function. The invention provides the universal interface used between 10 GSERDES and different ONMAC, so that the SERDES can be applied to different systems and equipment.
Description
Technical field
The present invention relates to fiber optic communication field, is the general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES specifically.Especially refer to be used for the key interface parts of 10GEPON and XG-PON system---10G SERDES (Serializer-Deserializer, series connection/deserializer also are called parallel series and staticizer, or serializer/and change device) the general-purpose interface method.
Background technology
Ethernet passive optical network (EPON) is to utilize the topological structure of EPON (PON) to realize a kind of latticed form that the ethernet signal of carrying multiple business transmits.Adopt point to multipoint configuration, the passive fiber transmission means provides multiple business on Ethernet.At present, IP/Ethernet uses and to account for more than 90% of whole local area network communication, and EPON is structure efficiently owing to use above-mentioned economy, thereby becomes connection access network end user's a kind of effective communication means.As the evolution technology of EPON, 10GEPON compares with existing EPON has tangible technical advantage, is embodied in higher transmission rate, higher shunt ratio, stronger networking capability and better compatibility.
Similarly; Gigabit passive optical network (GPON) also is to adopt point to transmit multi-service data to the passive fiber transmission means of multiple spot; Be with the difference of EPON; Adopt GFP (interchangeable frame agreement), can the business (Ethernet, TDM, ATM etc.) of any kind and any speed have been carried out original form encapsulation after by the PON transmission, be a kind of brand-new effective solution of Optical Access Network.Same, as the evolution technology of GPON, XG-PON compares with existing GPON also has tangible technical advantage.
The typical GEPON/GPON of one cover system is made up of the optical line terminal that is positioned at local side (OLT) and several optical network units (ONU) that is positioned at far-end; Connect by passive light distribution network (ODN) between OLT and the ONU; Adopt the topological structure of point, see Fig. 1 to multiple spot (P2MP).In OLT and ONU equipment; PON MAC chip is used to realize the PON mac-layer protocol; Pmd layer (physical medium be correlated with sublayer) function is realized by the optical transceiver module at two ends; Series connection/deserializer SERDES is used for connecting PON MAC layer acp chip and optical transceiver module (being the optical module of Fig. 2), mainly realizes the function of PMA layer (physical medium connection sublayer), like functions such as string and conversion, clock recoveries.See Fig. 2.
OLT or ONU for 10GEPON and XG-PON system; The interface of SERDES and optical module one side all is the HSSI High-Speed Serial Interface of 1.25G, 2.5G or 10G; And the operation principle of a lot of circuit is same or analogous, so there is the possibility of exploitation unified interface.But the SERDES of OLT or ONU (10G SERDES) is a parallel interface with the interface of PON MAC chip, is discrepant between the different systems.
For 10GEPON equipment (OLT or ONU); Two kinds of forms such as symmetrical and asymmetric are arranged; Up/downstream rate is respectively 10Gbps/10Gbps and 10Gbps/1.25Gbps, and for the transfer rate of 10G, the parallel interface width is 16Bit; For the transfer rate of 1.25G, parallel interface is TBI (Ten-Bit-interface) interface of 10Bit.
For XG-PON equipment (OLT or ONU); Two kinds of forms of XG-PON1 and XG-PON2 are arranged; Up/downstream rate is respectively 10Gbps/2.5Gbps and 10Gbps/10Gbps, and for the transfer rate of 10G, the parallel interface width is 16Bit; For the transfer rate of 2.5G, the parallel interface width is 8Bit.
In order to realize the compatibility of 10G SERDES in two kinds of different systems (10GEPON and XG-PON), two kinds of distinct devices (OLT and ONU), developing a kind of general-purpose interface method just becomes inevitable choice.
Summary of the invention
To the defective that exists in the prior art; The object of the present invention is to provide the general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES; A kind of general-purpose interface between 10G SERDES and the different PON MAC is provided, makes SERDES in different systems and equipment, to be applied.
For reaching above purpose, the technical scheme that the present invention takes is:
Be used for the general-purpose interface method of 10GEPON or XG-PON OLT or ONU SERDES, it is characterized in that, comprise two steps: the interface function definition, and according to the general SERDES interface module of interface function definition design,
Interface function definition is specific as follows: the interface signal of definition 10GEPON and XG-PON system multiplexing, and all signals are 10GEPON and XG-PON system multiplexing, and each interface signal of definition is respectively:
1) with the serial line interface signal of optical module, have 2,
SIN_3G and SOUT_3G: adopt the transmission circuit of 3G, be used to send or receive the high-speed differential signal of 1.25Gbps and 2.5Gbps,
SIN_10G and SOUT_10G: adopt the transmission circuit of 10G, be used to send or receive the high-speed differential signal of 10Gbps,
2) control signal has 8,
Mode select signal MODE_SEL: be used for 10GEPON or XG-PON model selection,
OLT or ONU select signal OLT_ONU_SEL: be used for OLT or ONU model selection, promptly select to work in OLT or ONU mode,
Operating rate is selected signal RATE_SEL: be used for rate selection,
LLEB: line loopback enables control,
DLEB: the diagnosis loopback enables control,
RESET: the control that resets,
TEST_MODE: chip operation is set under test pattern,
TX_EN: transmission enables,
Through setting to control signal MODE_SEL, OLT_ONU_SEL and RATE_SEL, realize being provided with the various working methods of interface,
3) reference clock has 2,
RX_REFCLK: the receiver side reference clock, under the 10GEPON pattern, be 644MHz or 125MHz, under the XG-PON pattern, be 622MHz or 155MHz,
TX_REFCLK: the transmitter side reference clock, under the 10GEPON pattern, be 644MHz or 125MHz, under the XG-PON pattern, be 622MHz or 155MHz,
4) state indication has 4,
TX_LOCK: the indication of transmitter side pll lock,
RX_LOCK: the indication of receiver side pll lock,
RX_LOS: the Received Loss Of Signal indication,
TEST_OK: test is through indication, is used for chip and detects automatically and accomplish indication, and chip internal has PRBS generator and BERT, after getting into test pattern, carries out from detecting, detect through will providing this indication,
5) parallel interface data and clock signal have 4,
DOUT: the output of parallel interface data,
DIN: the input of parallel interface data,
RXCLK: parallel interface receiver side clock,
TXCLK: parallel interface transmitter side clock,
Different according to control signal MODE_SEL, OLT_ONU_SEL and RATE_SEL, the data bit width of parallel interface data and clock signal is different with frequency, realizes satisfying the various requirement of different system and distinct device,
6) serial control interface signal is used for the control of microcomputer mouth to SERDES, has 2,
SDA: the Serial Control data wire,
SCL: Serial Control clock line.
On the basis of technique scheme; Said definition designs in the general SERDES interface module according to interface function, by the interface function definition each circuit unit is divided into: receiver side circuit, transmitter side circuit, loopback and test circuit and serial control interface circuit.
On the basis of technique scheme, said receiver side circuit comprises: 10G receiving circuit unit 10G-RX, and 3G receiving circuit unit 3G-RX, and the serial-parallel conversion circuit cells D EMUX that is connected with 10G-RX circuit unit, 3G-RX circuit unit,
Comprise ce circuit unit and signal deteching circuit in said 10G-RX circuit unit, the 3G-RX circuit unit,
Said ce circuit unit is used for locking phase; From the serial data that receives, extract serial clock, and make this clock and receive data sync, for 10GEPON and XG-PON pattern; The circuit of this part is consistent basically; Difference is that under different patterns REFCLK is different, and VCO frequency VCXO is also different; For different speed; Phase-locked loop circuit in the ce circuit unit will be according to mode of operation and rate selection indication; Select corresponding VCO frequency and Clock Multiplier Factor, to obtain the serial clock of various frequencies such as 1.25G, 2.488G, 9.952G, 10.3125G; After the locking of receiver side phase-locked loop circuit, then will provide the RX_LOCK indication,, will provide the RX_LOS indication if signal deteching circuit detects less than signal at receiving terminal;
The major function of DEMUX unit is to convert serial data into parallel data, according to selected mode of operation and speed, will provide the parallel data of 8Bit, 10Bit, 16Bit.
On the basis of technique scheme, said transmitter side circuit comprises: 10G transtation mission circuit unit 10G-TX, and 3G transtation mission circuit unit 3G-TX, and the parallel-to-serial converter unit MUX that is connected with 10G-TX circuit unit, 3G-TX circuit unit,
Comprise clock synthesis unit CMU in 10G-TX circuit unit, the 3G-TX circuit unit; For 10GEPON and XG-PON pattern; The circuit that serial clock produces part is consistent basically; All need the CMU unit to generate the serial tranmitting data register, difference is that just two kinds of tranmitting data register signal TX_REFCLK under the pattern are different; For different transmission rates; Clock circuit will be selected indication according to mode of operation and transmission rate; Select corresponding VCO frequency and Clock Multiplier Factor; To obtain the serial clock of various frequencies such as 1.25G, 2.488G, 9.952G, 10.3125G, after the locking of transmitter side phase-locked loop circuit, will provide the TX_LOCK indication;
The MUX circuit unit is accomplished the conversion of parallel data to serial data, according to selected mode of operation and speed, will carry out and goes here and there conversion the parallel data of 8Bit, 10Bit or 16Bit, converts serial data to and sends.
On the basis of technique scheme, said loopback and test circuit comprise: loopback control circuit and test circuit,
The loopback control circuit is controlled through LLEB and DLEB and is selected circuit loopback mode or diagnosis loopback mode;
Said test circuit comprises: PRBS generator and BERT, this part circuit are only effective when TEST_MODE is " 1 "; Wherein:
The PRBS generator is used to produce the required random data input of self-test, under test pattern, and as the parallel data input, after internal loopback, from DEMUX output,
The bert circuitry design with detecting the completeness of PRBS data behind the chip internal loopback, if mistake do not occur, will provide the TEST_OK indication in the DEMUX unit.
On the basis of technique scheme, said serial control interface circuit serial interface needs the cpu peripheral control unit, is used for the built-in register through CPU visit SERDES, realizes control and state read-write capability to SERDES,
2 signals of SCL and SDA connect the serial clock and the serial data pin of CPU control unit respectively.
The general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES of the present invention provides a kind of general-purpose interface between 10G SERDES and the different PON MAC, makes SERDES in different systems and equipment, to be applied.
The general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES of the present invention; Realized a kind of unified SERDES interface; The application scenario of special-purpose SERDES is expanded greatly; Inherited can be shared in the SERDES design part, made things convenient for the SERDES designer according to different demands adjustment designing requirement.
The present invention has realized a kind of general SERDES interface module; The application scenario of special-purpose SERDES is expanded greatly; Inherited can be shared in the SERDES design part; Made things convenient for the SERDES designer according to different demand adjustment designing requirement, common interface module can satisfy the requirement of 10GEPON or various interface modes such as XG-PON OLT or ONU equipment, and has accomplished signal and multiplexing functions to greatest extent.
Description of drawings
The present invention has following accompanying drawing:
Fig. 1 is the PON system construction drawing,
Fig. 2 is SERDES and optical module and PON MAC chip interface figure,
Fig. 3 is interface function definition figure,
Fig. 4 is the interface function option table,
Fig. 5 is the loopback test sketch map,
Fig. 6 is a SERDES interface module structure chart.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further explain.
In order to solve the compatibility in different system and equipment, have following technical problem to need to solve:
1) arbitrary moment can only be defined as 10GEPON pattern or XG-PON pattern, and both can only get one of which.
When 2) working in different mode, can be according to system for use in carrying and device therefor different, the selection wire trackside sends, receiving velocity.
3) can make that the circuit interface characteristic after the conversion can adapt to the demand of different system and equipment, thereby guarantee the stability of interface work according to the bit wide of the different transmissions in line side, receiving velocity selection string and the transmission of conversion back, reception data.
4) should carry out multiplexingly for signal, interface definition is simplified as far as possible with identical electric attribute.
5) interface should have measurability preferably, can adapt to the test request of different system and equipment.
The general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES of the present invention; Relate to OLT or ONU in the 10GEPON system, and OLT in the XG-PON system or ONU, be equipped with series connection/deserializer SERDES among said OLT, the ONU; And said series connection/deserializer SERDES refers to 10G SERDES especially; This method comprises two steps: the interface function definition, and according to the general SERDES interface module of interface function definition design
The interface function definition is specific as follows:
The interface signal of definition 10GEPON and XG-PON system multiplexing shown in the interface function definition figure of Fig. 3, can see that all signals are 10GEPON and XG-PON system multiplexing, and each interface signal of definition is respectively:
1) with the serial line interface signal of optical module, have 2,
SIN_3G and SOUT_3G: adopt the transmission circuit of 3G, be used to send or receive the high-speed differential signal of 1.25Gbps and 2.5Gbps,
SIN_10G and SOUT_10G: adopt the transmission circuit of 10G, be used to send or receive the high-speed differential signal of 10Gbps,
2) control signal has 8,
Mode select signal MODE_SEL: be used for 10GEPON or XG-PON model selection,
OLT or ONU select signal OLT_ONU_SEL: be used for OLT or ONU model selection, promptly select to work in OLT or ONU mode,
Operating rate is selected signal RATE_SEL: be used for rate selection,
LLEB: line loopback enables control,
DLEB: the diagnosis loopback enables control,
RESET: the control that resets,
TEST_MODE: chip operation is set under test pattern,
TX_EN: transmission enables,
Through setting to control signal MODE_SEL, OLT_ONU_SEL and RATE_SEL, realize being provided with the various working methods of interface, specific embodiment is seen Fig. 4,
3) reference clock has 2,
RX_REFCLK: the receiver side reference clock, under the 10GEPON pattern, be 644MHz or 125MHz, under the XG-PON pattern, be 622MHz or 155MHz,
TX_REFCLK: the transmitter side reference clock, under the 10GEPON pattern, be 644MHz or 125MHz, under the XG-PON pattern, be 622MHz or 155MHz,
4) state indication has 4,
TX_LOCK: the indication of transmitter side pll lock,
RX_LOCK: the indication of receiver side pll lock,
RX_LOS: the Received Loss Of Signal indication,
TEST_OK: test is used for chip and detects the completion indication automatically through indication, and chip internal has PRBS (pseudo-random binary sequence) generator and BERT (Error detection circuit); After getting into test pattern; Carry out through providing this indication from detecting
5) parallel interface data and clock signal have 4,
DOUT: the output of parallel interface data,
DIN: the input of parallel interface data,
RXCLK: parallel interface receiver side clock,
TXCLK: parallel interface transmitter side clock,
Different according to control signal MODE_SEL, OLT_ONU_SEL and RATE_SEL, the data bit width of parallel interface data and clock signal is different with frequency, realizes satisfying the various requirement of different system and distinct device, and specific embodiment is seen Fig. 4,
6) serial control interface signal is used for the control of microcomputer mouth to SERDES, has 2,
SDA: the Serial Control data wire,
SCL: Serial Control clock line.
On the basis of technique scheme; Said according in interface function definition SERDES interface module design, general; Its structure is as shown in Figure 6, by the interface function definition each circuit unit is divided into: receiver side circuit, transmitter side circuit, loopback and test circuit and serial control interface circuit.
Said receiver side circuit comprises: 10G receiving circuit unit 10G-RX, 3G receiving circuit unit 3G-RX, and the serial-parallel conversion circuit cells D EMUX (signal is separated multiplex circuit) that is connected with 10G-RX circuit unit, 3G-RX circuit unit.
Comprise ce circuit unit and signal deteching circuit in said 10G-RX circuit unit, the 3G-RX circuit unit,
Said ce circuit unit is used for locking phase; From the serial data that receives, extract serial clock, and make this clock and receive data sync, for 10GEPON and XG-PON pattern; The circuit of this part is consistent basically; Difference is that under different patterns REFCLK is different, and VCO frequency VCXO is also different; For different speed; Phase-locked loop circuit in the ce circuit unit will be according to mode of operation and rate selection indication; Select corresponding VCO frequency and Clock Multiplier Factor, to obtain the serial clock of various frequencies such as 1.25G, 2.488G, 9.952G, 10.3125G; After the locking of receiver side phase-locked loop circuit, then will provide the RX_LOCK indication,, will provide the RX_LOS indication if signal deteching circuit detects less than signal at receiving terminal;
The major function of DEMUX unit is to convert serial data into parallel data, according to selected mode of operation and speed, will provide the parallel data of 8Bit, 10Bit, 16Bit.
Said transmitter side circuit comprises: 10G transtation mission circuit unit 10G-TX, 3G transtation mission circuit unit 3G-TX, and the parallel-to-serial converter unit MUX (signal multiplexing circuit) that is connected with 10G-TX circuit unit, 3G-TX circuit unit.
Comprise clock synthesis unit CMU in 10G-TX circuit unit, the 3G-TX circuit unit; The topmost circuit of TX side is clock synthesis unit CMU; For 10GEPON and XG-PON pattern; The circuit that serial clock produces part is consistent basically, all needs the CMU unit to generate the serial tranmitting data register, and difference is that just two kinds of tranmitting data register signal TX_REFCLK under the pattern are different; For different transmission rates; Clock circuit will be selected indication according to mode of operation and transmission rate; Select corresponding VCO frequency and Clock Multiplier Factor; To obtain the serial clock of various frequencies such as 1.25G, 2.488G, 9.952G, 10.3125G, after the locking of transmitter side phase-locked loop circuit, will provide the TX_LOCK indication;
The MUX circuit unit is accomplished the conversion of parallel data to serial data, according to selected mode of operation and speed, will carry out and goes here and there conversion the parallel data of 8Bit, 10Bit or 16Bit, converts serial data to and sends.
Said loopback and test circuit comprise: loopback control circuit and test circuit.
The loopback control circuit is controlled through LLEB and DLEB and is selected circuit loopback mode or diagnosis loopback mode;
Said test circuit comprises: PRBS generator and BERT, this part circuit are only effective when TEST_MODE is " 1 "; Wherein:
The PRBS generator is used to produce the required random data input of self-test, under test pattern, and as the parallel data input, after internal loopback, from DEMUX output,
The bert circuitry design with detecting the completeness of PRBS data behind the chip internal loopback, if mistake do not occur, will provide the TEST_OK indication in the DEMUX unit.
Said serial control interface circuit serial interface needs the cpu peripheral control unit, is used for the built-in register through CPU visit SERDES, realizes control and state read-write capability to SERDES.
2 signals of SCL and SDA connect the serial clock and the serial data pin of CPU control unit respectively.
Each circuit unit of Fig. 6 all can adopt existing general module to realize from operation principle; But its unique distinction is arranged again in realization:, need support various frequencies such as 1.25G, 2.488G, 9.952G, 10.3125G in the CDR unit of 10G-RX or 3G-RX inside and the CMU unit of 10G-TX or 3G-TX inside owing to will support 2 kinds of different speed grade of system of 10GEPON and XGPON.Specifically:
1, defining mode selects signal MODE_SEL to select 10G EPON pattern or XG-PON pattern, and definition OLT or ONU select signal OLT_ONU_SEL to select to work in OLT or ONU mode, and definition RATE_SEL selects signal to select operating rate.
2, because there are bigger difference in the serial transmission circuit of 10G speed and the serial transmission circuit below the 2.5G speed on key technology, so do not consider the multiplexing of this part circuit.But the 10G multirate serial transmission circuit of 10GEPON and XGPON can be multiplexing, realizes with 10G-TX and 10G-RX transceiver module respectively; 2.5G it is multiplexing that the serial transmission circuit of speed and 1.25G speed carries out, and realizes with 3G-TX and 3G-RX transceiver module respectively.
3, for 10G EPON system, consider the versatility of SERDES, need to consider the symmetrical system of 10G/10Gbps and the asymmetric system of 10G/1.25Gbps.
4, for the XG-PON system, consider the versatility of SERDES, need to consider the XG-PON2 symmetrical system of 10G/10Gbps and the XG-PON1 asymmetric system of 10G/2.5Gbps.
Can find out from above analysis that 5, the data-interface that is used for 2 kinds of different system SERDES can be multiplexing.At serial port, the high-speed-differential line of 10G speed can be multiplexing, and the high-speed-differential line of 2.5G and 1.25G speed also can be multiplexing; At LPT: the maximum data width is 16 Bit; Different according to system for use in carrying and device therefor; 3 kinds of width such as 16Bit, 10Bit, 8Bit can be arranged; The speed of LPT can have 4 kinds of speed such as 644Mbps, 622Mbps, 311Mbps, 125Mbps, sees the interface function option table of Fig. 4 for details.
6, the control pin that is used to test can be shared, like function signals such as loopback test and test patterns.
Loop-back test signal can be provided with line loopback and diagnosis loopback, is convenient to fault location.Fig. 5 is seen in the function signal.
Test pattern indication is set, when batch testing, can starts inner test function, test through the time will provide test and accomplish signal.
7, serial control interface can be shared as the general controls interface.
The external interface that focuses on of the present invention has just been realized the unified external interface of 2 kinds of systems such as 10GEPON and XGPON, when concrete the use, only need be configured according to employed occasion and speed and gets final product.
The above is merely preferred embodiment of the present invention, is not limited to the present invention, all any modifications of within the present invention spirit and principle, being made, is equal to and replaces and improvement etc., all is contained within protection scope of the present invention.
The content of not doing in this specification to describe in detail belongs to this area professional and technical personnel's known prior art.
Claims (6)
1. be used for the general-purpose interface method of 10GEPON or XG-PON OLT or ONU SERDES, it is characterized in that, comprise two steps: the interface function definition, and according to the general SERDES interface module of interface function definition design,
Interface function definition is specific as follows: the interface signal of definition 10GEPON and XG-PON system multiplexing, and all signals are 10GEPON and XG-PON system multiplexing, and each interface signal of definition is respectively:
1) with the serial line interface signal of optical module, have 2,
SIN_3G and SOUT_3G: adopt the transmission circuit of 3G, be used to send or receive the high-speed differential signal of 1.25Gbps and 2.5Gbps,
SIN_10G and SOUT_10G: adopt the transmission circuit of 10G, be used to send or receive the high-speed differential signal of 10Gbps,
2) control signal has 8,
Mode select signal MODE_SEL: be used for 10GEPON or XG-PON model selection,
OLT or ONU select signal OLT_ONU_SEL: be used for OLT or ONU model selection, promptly select to work in OLT or ONU mode,
Operating rate is selected signal RATE_SEL: be used for rate selection,
LLEB: line loopback enables control,
DLEB: the diagnosis loopback enables control,
RESET: the control that resets,
TEST_MODE: chip operation is set under test pattern,
TX_EN: transmission enables,
Through setting to control signal MODE_SEL, OLT_ONU_SEL and RATE_SEL, realize being provided with the various working methods of interface,
3) reference clock has 2,
RX_REFCLK: the receiver side reference clock, under the 10GEPON pattern, be 644MHz or 125MHz, under the XG-PON pattern, be 622MHz or 155MHz,
TX_REFCLK: the transmitter side reference clock, under the 10GEPON pattern, be 644MHz or 125MHz, under the XG-PON pattern, be 622MHz or 155MHz,
4) state indication has 4,
TX_LOCK: the indication of transmitter side pll lock,
RX_LOCK: the indication of receiver side pll lock,
RX_LOS: the Received Loss Of Signal indication,
TEST_OK: test is through indication, is used for chip and detects automatically and accomplish indication, and chip internal has PRBS generator and BERT, after getting into test pattern, carries out from detecting, detect through will providing this indication,
5) parallel interface data and clock signal have 4,
DOUT: the output of parallel interface data,
DIN: the input of parallel interface data,
RXCLK: parallel interface receiver side clock,
TXCLK: parallel interface transmitter side clock,
Different according to control signal MODE_SEL, OLT_ONU_SEL and RATE_SEL, the data bit width of parallel interface data and clock signal is different with frequency, realizes satisfying the various requirement of different system and distinct device,
6) serial control interface signal is used for the control of microcomputer mouth to SERDES, has 2,
SDA: the Serial Control data wire,
SCL: Serial Control clock line.
2. the general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES as claimed in claim 1; It is characterized in that: said definition designs in the general SERDES interface module according to interface function, by the interface function definition each circuit unit is divided into: receiver side circuit, transmitter side circuit, loopback and test circuit and serial control interface circuit.
3. the general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES as claimed in claim 2; It is characterized in that; Said receiver side circuit comprises: 10G receiving circuit unit 10G-RX; 3G receiving circuit unit 3G-RX, and the serial-parallel conversion circuit cells D EMUX that is connected with 10G-RX circuit unit, 3G-RX circuit unit
Comprise ce circuit unit and signal deteching circuit in said 10G-RX circuit unit, the 3G-RX circuit unit,
Said ce circuit unit is used for locking phase; From the serial data that receives, extract serial clock, and make this clock and receive data sync, for 10GEPON and XG-PON pattern; The circuit of this part is consistent basically; Difference is that under different patterns REFCLK is different, and VCO frequency VCXO is also different; For different speed; Phase-locked loop circuit in the ce circuit unit will be according to mode of operation and rate selection indication; Select corresponding VCO frequency and Clock Multiplier Factor, to obtain the serial clock of various frequencies such as 1.25G, 2.488G, 9.952G, 10.3125G; After the locking of receiver side phase-locked loop circuit, then will provide the RX_LOCK indication,, will provide the RX_LOS indication if signal deteching circuit detects less than signal at receiving terminal;
The major function of DEMUX unit is to convert serial data into parallel data, according to selected mode of operation and speed, will provide the parallel data of 8Bit, 10Bit, 16Bit.
4. the general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES as claimed in claim 2; It is characterized in that; Said transmitter side circuit comprises: 10G transtation mission circuit unit 10G-TX; 3G transtation mission circuit unit 3G-TX, and the parallel-to-serial converter unit MUX that is connected with 10G-TX circuit unit, 3G-TX circuit unit
Comprise clock synthesis unit CMU in 10G-TX circuit unit, the 3G-TX circuit unit; For 10GEPON and XG-PON pattern; The circuit that serial clock produces part is consistent basically; All need the CMU unit to generate the serial tranmitting data register, difference is that just two kinds of tranmitting data register signal TX_REFCLK under the pattern are different; For different transmission rates; Clock circuit will be selected indication according to mode of operation and transmission rate; Select corresponding VCO frequency and Clock Multiplier Factor; To obtain the serial clock of various frequencies such as 1.25G, 2.488G, 9.952G, 10.3125G, after the locking of transmitter side phase-locked loop circuit, will provide the TX_LOCK indication;
The MUX circuit unit is accomplished the conversion of parallel data to serial data, according to selected mode of operation and speed, will carry out and goes here and there conversion the parallel data of 8Bit, 10Bit or 16Bit, converts serial data to and sends.
5. the general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES as claimed in claim 2 is characterized in that said loopback and test circuit comprise: loopback control circuit and test circuit,
The loopback control circuit is controlled through LLEB and DLEB and is selected circuit loopback mode or diagnosis loopback mode;
Said test circuit comprises: PRBS generator and BERT, this part circuit are only effective when TEST_MODE is " 1 "; Wherein:
The PRBS generator is used to produce the required random data input of self-test, under test pattern, and as the parallel data input, after internal loopback, from DEMUX output,
The bert circuitry design with detecting the completeness of PRBS data behind the chip internal loopback, if mistake do not occur, will provide the TEST_OK indication in the DEMUX unit.
6. the general-purpose interface method that is used for 10GEPON or XG-PON OLT or ONU SERDES as claimed in claim 2; It is characterized in that; Said serial control interface circuit serial interface needs the cpu peripheral control unit; Be used for built-in register, realize control and state read-write capability SERDES through CPU visit SERDES
2 signals of SCL and SDA connect the serial clock and the serial data pin of CPU control unit respectively.
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| CN2012100337923A CN102594454A (en) | 2012-02-15 | 2012-02-15 | Universal interface method for 10 GEPON (Gigabit Passive Optical Network) or XG-PON (XG-Passive Optical Network) OLT (Optical Line Terminal) or ONU (Optical Network Unit) SERDES (Serializer-Deserializer) |
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