CN208444287U - A kind of emulator handling chip - Google Patents
A kind of emulator handling chip Download PDFInfo
- Publication number
- CN208444287U CN208444287U CN201821138788.2U CN201821138788U CN208444287U CN 208444287 U CN208444287 U CN 208444287U CN 201821138788 U CN201821138788 U CN 201821138788U CN 208444287 U CN208444287 U CN 208444287U
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- Prior art keywords
- pin
- emulator
- jtag interface
- interface
- jtag
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- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model discloses a kind of emulators for handling chip, its key points of the technical solution are that including the J-link emulator with the first jtag interface and SWD interface, SWD interface is used to connect with external PC machine, it further include pinboard, the pinboard includes the second jtag interface for connecting with external system plate and the third jtag interface for connecting with the first JTAG, second jtag interface is 10P pin, third jtag interface and the first jtag interface are 20P pin and are connected by 20P winding displacement, first pin of second jtag interface connects the first power supply by row's needle of 2P pin with second pin, it powers to realize to its interface, and safety and convenience in debugging process.
Description
Technical field
The utility model relates to emulator fields, particularly, are related to a kind of emulator for handling chip.
Background technique
J-link emulator is the general JTAG emulator for the support ARM core chip that SEGGER company releases.?
Plant under program with J.Link emulator under IAREWARM Integrated Development Environment, failed download phenomenon often occurs.To this into
One of the problem of row research is found wherein is since J-link emulator wiring goes wrong.
It, cannot be in the case where powering to system board again with J-Link emulator to being when emulator works downloading program
Plate of uniting is powered, and otherwise system board may be made to be burnt.And existing J-link emulator is to be defaulted under operating conditions to system
Plate power supply, makes to be powered under J-link default situations if necessary, needs to reequip J-link emulator.
Utility model content
In view of this, the utility model aim is to provide a kind of emulator for handling chip, mainly to existing J-
Link emulator is reequiped, to realize to the safety and convenience in the power supply of its interface and debugging process.
In order to solve the above-mentioned technical problem, the technical solution of the utility model is: a kind of emulator handling chip, including
J-link emulator with the first jtag interface and SWD interface, SWD interface are used to connect with external PC machine, further include turning
Fishplate bar, the pinboard include the second jtag interface for connecting with external system plate and for connecting with the first JTAG
Three jtag interfaces, the second jtag interface are 10P pin, and third jtag interface and the first jtag interface are 20P pin and pass through
The connection of 20P winding displacement, the first pin of second jtag interface connect the first power supply by row's needle of 2P pin with second pin,
Jumper cap is provided on row's needle.
Preferably, two pins on row's needle are connected separately with voltmeter.
Preferably, the first pin of second jtag interface by capacity earth and connection the first power supply, third, five,
Seven, nine pins are grounded, second pin TMS, and the 4th pin is TCK pin, and the 6th pin is TDO pin, and the 8th pin is TDI
Pin, the tenth pin are RESET pin.
Preferably, the capacitance of the capacitor is 100uf.
The utility model has the technical effect that following aspect: can pass through the jumper cap of row's needle on control pinboard
Realize whether the power end on emulator is connected to the power end on control panel, consequently facilitating test and control.In downloading journey
It when sequence, can be powered, can also be powered to system board by the J-link emulator after repacking directly to system board.If
It is powered using J-link emulator, needs to open on J-link emulator shell, the jumper cap of the inside is connected on the first power supply,
Namely on 3.3V voltage, VTref is 3.3V after repacking, can be used for powering to system board, this voltage not will cause circuit overloads.
The interface communication of 20P or 10P can be useful in increase the ports-Extending of emulator by being provided with pinboard.
Detailed description of the invention
Fig. 1 is the input interface of existing J-link emulator and the schematic diagram of output interface；
Fig. 2 is that improved structural system uses schematic diagram in embodiment；
Fig. 3 is pinboard line assumption diagram in embodiment.
Appended drawing reference: 1, the first jtag interface；2, SWD interface；3, J-link emulator；4, pinboard；41, the 2nd JTAG
Interface；42, third jtag interface；5, the first power supply；6, needle is arranged；7, voltmeter；8, capacitor.
Specific embodiment
Below in conjunction with attached drawing, specific embodiment of the present utility model is described in further detail, so that the utility model skill
Art scheme is more readily understood and grasps.
Embodiment:
A kind of emulator handling chip, refering to what is shown in Fig. 1, including the J- with the first jtag interface 1 and SWD interface 2
Link emulator 3, SWD interface 2 are used to connect with external PC machine.It is using existing and to it for J-link emulator 3
It improves, and improvement is on interface, so not illustrated to internal circuit.And existing J-link emulator
3 can be JLINK V8 emulator J-LINK ARM emulator, and Taobao etc. can choose in the market, and it is using existing
The pin setting of some jtag interfaces and SWD interface 2, interface is illustrated, and details are not described herein.
20P mentioned herein is illustrated as the abbreviation of 20Pin, looks like for 20 pins, is those skilled in the art's skill
General statement in art.Fig. 1 illustrates that emulator interface structure in the market.On the basis of the above, it is transformed completion originally
The purpose of invention.
Refering to what is shown in Fig. 2, the emulator of this programme further includes pinboard 4, pinboard 4 includes for connecting with external system plate
The second jtag interface 41 connect and the third jtag interface 42 for being connected with the first JTAG.
Refering to what is shown in Fig. 3, the second jtag interface 41 is 10P pin, third jtag interface 42 and the first jtag interface 1 are
It 20P pin and is connected by 20P winding displacement, the first pin and second pin of the second jtag interface 41 pass through row's needle 6 of 2P pin
The first power supply 5 is connected, arranges and is provided with jumper cap on needle 6.Two pins on row's needle 6 are connected separately with voltmeter 7.Voltmeter 7
It can be in order to testing the voltage at both ends.
First pin of the second jtag interface 41 is grounded by capacitor 8 and connects the first power supply 5, and third, five, seven, nine draw
Foot ground connection, second pin TMS, the 4th pin are TCK pin, and the 6th pin is TDO pin, and the 8th pin is TDI pin, the
Ten pins are RESET pin.The capacitance of capacitor 8 is 100uf.Capacitor 8 can effectively remove some noise signals, enable to imitate
True device work is relatively reliable.
JTAG interface circuit, wherein TMS, TCK, TDO, TDl are respectively the external pin 2,4,6,8 of jtag interface, these
Pin is separately connected system board.In wiring, the pin on J-link emulator 3 must be corresponding with jtag interface on system board,
Otherwise lead to program failed download.The operating voltage of system board is 3.3V.Pin 3,5,7,9 is grounded, and has pin 1 in some cases
It may be shorted with the pin of ground connection, cause system board that can not power, power supply indicator does not work in system version, so as to cause under program
Carry failure.It, can be by the jumper cap at control 4 row's needle 6 of pinboard, to decide whether to adopt after having reequiped J-link emulator 3
It is powered with J-link emulator 3 to system board.
Firstly, this emulator is connected with PC machine, if emulator indicator light is bright, emulator fault-free；It is surveyed with multimeter
The first pin current potential on pinboard 4 is measured, which should be 3.
3V or so, otherwise pinboard 4 is faulty.Finally, checking the wiring on pinboard 4 and system board between jtag interface, guarantee to turn
1,5,7,9,13,15 pins are corresponded with 1,8,2,4,6,10 pin of jtag interface on system board respectively on fishplate bar 4.More than if
Inspection is all normal, then this emulator line is not faulty, it may be possible to which driving installation or configuration go wrong.
Certainly, the representative instance of above only the utility model, in addition to this, the utility model can also have other a variety of
Specific embodiment, all technical solutions formed using equivalent substitution or equivalent transformation all fall within the requires of the utility model protection
Within the scope of.
Claims (4)
1. a kind of emulator for handling chip, including the J-link emulator with the first jtag interface and SWD interface, SWD is connect
Mouth with external PC machine for connecting, characterized in that further includes pinboard, the pinboard includes for connecting with external system plate
The second jtag interface connect is 10P pin, third with the third jtag interface for connecting with the first JTAG, the second jtag interface
Jtag interface and the first jtag interface are 20P pin and are connected by 20P winding displacement, the first pin of second jtag interface
The first power supply is connected by row's needle of 2P pin with second pin, is provided with jumper cap on row's needle.
2. the emulator of processing chip as described in claim 1, characterized in that two pins on row's needle are separately connected
There is voltmeter.
3. the emulator of processing chip as described in claim 1, characterized in that the first pin of second jtag interface is logical
Capacity earth and the first power supply of connection, third, five, seven, nine pins ground connection are crossed, second pin TMS, the 4th pin draws for TCK
Foot, the 6th pin are TDO pin, and the 8th pin is TDI pin, and the tenth pin is RESET pin.
4. the emulator of processing chip as claimed in claim 3, characterized in that the capacitance of the capacitor is 100uf.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821138788.2U CN208444287U (en) | 2018-07-18 | 2018-07-18 | A kind of emulator handling chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821138788.2U CN208444287U (en) | 2018-07-18 | 2018-07-18 | A kind of emulator handling chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208444287U true CN208444287U (en) | 2019-01-29 |
Family
ID=65085616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821138788.2U Expired - Fee Related CN208444287U (en) | 2018-07-18 | 2018-07-18 | A kind of emulator handling chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208444287U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112084001A (en) * | 2020-07-22 | 2020-12-15 | 北京杰创永恒科技有限公司 | Simulator based on STM32 chip |
-
2018
- 2018-07-18 CN CN201821138788.2U patent/CN208444287U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112084001A (en) * | 2020-07-22 | 2020-12-15 | 北京杰创永恒科技有限公司 | Simulator based on STM32 chip |
| CN112084001B (en) * | 2020-07-22 | 2023-05-26 | 北京杰创永恒科技有限公司 | Emulator based on STM32 chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190129 Termination date: 20210718 |