CN207992988U - A kind of startup configuration multiplex circuit - Google Patents
A kind of startup configuration multiplex circuit Download PDFInfo
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- CN207992988U CN207992988U CN201820396517.0U CN201820396517U CN207992988U CN 207992988 U CN207992988 U CN 207992988U CN 201820396517 U CN201820396517 U CN 201820396517U CN 207992988 U CN207992988 U CN 207992988U
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Abstract
The utility model discloses a kind of startups to configure multiplex circuit, including reset level control module, startup level configuration module and output isolation module；The complexing pin of the input terminal and embeded processor that start level configuration module connects, and output end is connect with the input terminal of output isolation module, exports the output end of isolation module as the output end for starting configuration multiplex circuit；The input terminal of reset level control module receives the reset signal from watchdog reset circuit, and output end is connect with the third end for starting level configuration module.The startup configuration multiplex circuit of the utility model need not carry out signal switching and pin multiplexing function can be realized, and entire circuit has zero handoff delay, and circuit is simple, of low cost, dependable performance.
Description
Technical field
The utility model is related to chip start-up circuit technical fields, and in particular to a kind of startup configuration multiplex circuit.
Background technology
Embeded processor needs by starting configuration feature to be BOOT pin configuration level during electrifying startup,
So that embeded processor is according to the level signal on the BOOT pins read, and then determine the start-up mode of processor.By
It is limited in processor I/O resources, when processor I/O resource scarcitys, start configuration feature and I/O output functions will use it is same
A pin, at this time periphery need reusable- design circuit and start configuration feature and I/O output functions to realize.
Prior art generally use high-speed bus switches chip timesharing and realizes startup configuration feature and I/O output functions, tool
The startup configuration multiplex circuit block diagram of body is as shown in Figure 1, high-speed bus switches first end (as input terminal) and the insertion of chip
The startup configuration of formula processor and the connection of universal port (BOOTx/GPIOx) complexing pin, second end and watchdog reset circuit
Connection receives reset signal, and third end is connect with level configuration circuit is started, and the 4th end is connect with output circuit.When embedded
In processor start-up course, chip is switched by high-speed bus and is switched to startup level configuration circuit, for complexing pin configuration electricity
It puts down to complete to start, after embeded processor start completion, then it is electric normal output to be switched back by high-speed bus switching chip
Road, complexing pin is as normal general purpose I/O port.
However, there are still problems with and defect for existing startup configuration multiplex circuit：Switch chip using high-speed bus
When the shortcomings of there are of high cost, circuit is complicated, service efficiency is not high and volume is big.
Utility model content
The utility model provides a kind of startup configuration multiplex circuit, to solve in existing startup configuration multiplex circuit using height
When fast bus switch chip it is existing it is of high cost, circuit is complicated, service efficiency is low and bulky problem, technical solution is such as
Under：
A kind of startup configuration multiplex circuit, including reset level control module, startup level configuration module and output isolation
Module；
It is described start level configuration module input terminal connect with the complexing pin of the embeded processor, output end and
The output end of the input terminal connection of the output isolation module, the output isolation module configures multiplex circuit as the startup
Output end；
The input terminal of the reset level control module receives the reset signal from watchdog reset circuit, output end with
The third end connection for starting level configuration module, for exporting control level signal to the startup level configuration module,
The startup level configuration module is controlled to complete to start level configuration.
In above-mentioned technical proposal, it is preferred that the reset level control module includes first switch unit and second switch
Unit；
Wherein, the output end that the control terminal of the first switch unit passes through first resistor and the watchdog reset circuit
Connection, receives the reset signal, first end is connect by second resistance with the control terminal of the second switch unit, second end
Ground connection；
The first end of the second switch unit is connect with the third end for starting level configuration module, second end and electricity
Source connects, and is also parallel with the first pull-up resistor between the control terminal and second end of the second switch unit.
In above-mentioned technical proposal, it is preferred that the startup level configuration module includes 3rd resistor and the 4th resistance；
Wherein, the both ends of the 3rd resistor are managed with the output end of the reset level control module and the multiplexing respectively
Foot connects, and described 4th resistance one end is connect with the complexing pin, other end ground connection.
In above-mentioned technical proposal, it is preferred that the startup level configuration module includes the second pull-up resistor and the 4th resistance；
Wherein, second pull-up resistor one end is connect with the complexing pin, and the other end connects power supply, the 4th electricity
Resistance one end is connect with the complexing pin, other end ground connection.
In above-mentioned technical proposal, it is preferred that the output isolation module includes diode and pull down resistor；
Wherein, the anode of the diode is connect with the output end for starting level configuration module, described in cathode conduct
The output end of isolation module is exported, and is grounded by the pull down resistor.
In above-mentioned technical proposal, it is preferred that the control terminal of the second switch unit is grounded by filter capacitor.
The startup of the utility model configures multiplex circuit, and when embeded processor resets and starts, reset level controls mould
Output control level signal is complete to control startup level configuration module to startup level configuration module after block receives reset signal
At level configuration is started, complexing pin is as general purpose I/O pins after reset.The utility model starts configuration multiplexing as a result,
Circuit need not carry out signal switching and can be realized pin multiplexing function, and entire circuit has zero handoff delay, and circuit it is simple,
Of low cost, dependable performance.
Description of the drawings
Fig. 1 is the structure diagram in the prior art for starting configuration multiplex circuit；
Fig. 2 is the structure diagram for starting configuration multiplex circuit in the utility model embodiment one；
Fig. 3 is that embeded processor is configured to startup configuration multiplexing when low level starts in the utility model embodiment two
The circuit diagram of circuit；
Fig. 4 is that embeded processor is configured to startup configuration multiplexing when high level starts in the utility model embodiment two
The circuit diagram of circuit.
Specific implementation mode
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than the restriction to the utility model.It further needs exist for
It is bright, it illustrates only for ease of description, in attached drawing and the relevant part of the utility model rather than entire infrastructure.
Embodiment one
Fig. 2 is the structure diagram for starting configuration multiplex circuit in the utility model embodiment one, wherein starts configuration multiplexing
Circuit 1 includes reset level control module 11, starts level configuration module 12 and output isolation module 13；Start level and configures mould
The input terminal of block 12 and the BOOTx/GPIOx complexing pins of embeded processor connect, output end and output isolation module 13
Input terminal connects, and exports output end of the output end of isolation module 13 as startup configuration multiplex circuit 1, embedded for exporting
The level signal of the universal port output of processor；The input terminal of reset level control module 11 is received from watchdog reset electricity
The reset signal on road, output end connects with the third end for starting level configuration module 12, and level signal is controlled to opening for exporting
Dynamic level configuration module 12, control start level configuration module 12 and complete to start level configuration.
Start configuration multiplex circuit 1 application include：When embeded processor resets and starts, reset level control module
After 11 receive the reset signal from watchdog reset circuit, output control level signal starts level configuration module 12 to control
It completes startup level to configure, after start completion, BOOTx/GPIOx complexing pins are as universal port, by starting level configuration
Module 12 and output 13 outputs level signals of isolation module.
In the utility model embodiment, when embeded processor, which resets, to be started, reset level control module, which receives, to be resetted
Output control level signal is completed to start level to level configuration module is started to control startup level configuration module after signal
Configuration, complexing pin is as general purpose I/O pins after reset.The utility model starts configuration multiplex circuit and does not need as a result,
It carrying out signal switching and pin multiplexing function can be realized, entire circuit has zero handoff delay, and circuit is simple, of low cost,
Dependable performance.
Embodiment two
Fig. 3 shows that embeded processor is configured to the circuit diagram of startup configuration multiplex circuit when low level starts,
In, reset level control module 11 includes first switch unit Q2 and second switch unit Q1；The control of first switch unit Q2
End is connected by the output end of first resistor R3 and watchdog reset circuit, receives reset signal, and first end passes through second resistance
R2 is connect with the control terminal of second switch unit Q1, second end ground connection；The first end of second switch unit Q1 is matched with level is started
The third end connection of module 12 is set, second end is connect with power supply, and between the control terminal and second end of second switch unit Q1 also
It is parallel with the first pull-up resistor R1, the control terminal of second switch unit Q1 is grounded by filter capacitor C1.Preferably, first switch
Unit Q2 is NPN type triode, and second switch unit Q1 is PNP type triode.
It includes 3rd resistor R5 and the 4th resistance R7 to start level configuration module 12；Wherein, the both ends of 3rd resistor R5 point
Do not connect with the output end of reset level control module 11 and BOOTx/GPIOx complexing pins, the 4th one end resistance R7 with
BOOTx/GPIOx complexing pins connect, other end ground connection.
It includes diode D1 and pull down resistor R8 to export isolation module 13；Wherein, the anode of diode D1 and startup level
The output end of configuration module 12 connects, output end of the cathode as output isolation module 13, and is grounded by pull down resistor R8,
Middle pull down resistor R8 can ensure that stable output signal.
Specific workflow is as follows, and embeded processor, which resets, to be started, and watchdog circuit output low level effectively resets
Signal is to first switch unit Q2 so that Q2 ends, and the first pull-up resistor R1 provides for second switch unit Q1 control terminals at this time
High level so that Q1 ends, and reset level control module 11 exports 0V at this time.Start the 4th resistance R7 in level configuration module 12
As pull down resistor, BOOTx/GPIOx complexing pins are pulled down to low level, and processor can normally read BOOTx/ at this time
The configuration level of GPIOx complexing pins simultaneously starts；After reset, the high level signal of watchdog circuit output failure, at this time
Q1 and Q2 conductings, reset level control module 11 export high level, and BOOTx/GPIOx complexing pins are by 3rd resistor R5 pull-up
High level, and as universal port GPIO signals are exported by starting level configuration module 12 and output isolation module 13.
Fig. 4 shows that embeded processor is configured to the circuit diagram of startup configuration multiplex circuit when high level starts,
In, reset level control module 11, output isolation module 13 are identical as Fig. 3, and details are not described herein.Start level configuration module 12
Including the second pull-up resistor R6 and the 4th resistance R7, wherein second one end pull-up resistor R6 connects with BOOTx/GPIOx complexing pins
It connects, the other end connects power supply, and the 4th one end resistance R7 is connect with BOOTx/GPIOx complexing pins, other end ground connection.
Specific workflow is as follows, and when embeded processor, which resets, to be started, Q1 and Q2 ends, reset level control module
11 output 0V, BOOTx/GPIOx complexing pins are high level by the second pull-up resistor R6 pull-up, and processor can normally be read
To BOOTx/GPIOx complexing pins configuration level and start；After reset, BOOTx/GPIOx complexing pins are as general
The normal outputs level signals of diode D1 are passed through in port.
In one embodiment, resistance R5, R6 and the R7 started in level configuration module can be all configured at electricity
On the plate of road, so that user is according to actual needs by being welded to connect corresponding resistor, to build the startup side with embeded processor
The corresponding startup level configuration module of formula.
In the utility model embodiment, when embeded processor, which resets, to be started, reset level control module, which receives, to be resetted
Output control level signal is completed to start level to level configuration module is started to control startup level configuration module after signal
Configuration, complexing pin is as general purpose I/O pins after reset.The utility model starts configuration multiplex circuit and does not need as a result,
Carry out signal switching and can be realized pin multiplexing function, entire circuit has zero handoff delay, and circuit it is simple, it is of low cost,
Dependable performance can protect startup level configuration module not influenced by peripheral circuit level by exporting isolation module.
Note that above are only the preferred embodiment and institute's application technology principle of the utility model.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various bright
Aobvious variation is readjusted and is substituted without departing from the scope of protection of the utility model.Therefore, although passing through above example
The utility model is described in further detail, but the utility model is not limited only to above example, is not departing from
Can also include other more equivalent embodiments in the case that the utility model is conceived, and the scope of the utility model is by appended
Right determine.
Claims (6)
1. a kind of startup configures multiplex circuit, which is characterized in that the startup configuration multiplex circuit includes reset level control mould
Block starts level configuration module and output isolation module；
Wherein, the complexing pin of the input terminal for starting level configuration module and embeded processor connects, output end and institute
The input terminal connection of output isolation module is stated, the output end of the output isolation module configures multiplex circuit as described start
Output end；
The input terminal of the reset level control module receives the reset signal from watchdog reset circuit, output end with it is described
The third end connection for starting level configuration module, for exporting control level signal to the startup level configuration module, control
The startup level configuration module is completed to start level configuration.
2. startup according to claim 1 configures multiplex circuit, which is characterized in that the reset level control module includes
First switch unit and second switch unit；
Wherein, the control terminal of the first switch unit is connected by the output end of first resistor and the watchdog reset circuit
It connects, receives the reset signal, first end is connect by second resistance with the control terminal of the second switch unit, the second termination
Ground；
The first end of the second switch unit is connect with the third end for starting level configuration module, and second end connects with power supply
It connects, and the first pull-up resistor is also parallel between the control terminal and second end of the second switch unit.
3. startup according to claim 1 configures multiplex circuit, which is characterized in that the startup level configuration module includes
3rd resistor and the 4th resistance；
Wherein, the both ends of the 3rd resistor connect with the output end of the reset level control module and the complexing pin respectively
It connects, described 4th resistance one end is connect with the complexing pin, other end ground connection.
4. startup according to claim 1 configures multiplex circuit, which is characterized in that the startup level configuration module includes
Second pull-up resistor and the 4th resistance；
Wherein, second pull-up resistor one end is connect with the complexing pin, and the other end connects power supply, the 4th resistance one
End is connect with the complexing pin, other end ground connection.
5. startup according to claim 1 configures multiplex circuit, which is characterized in that the output isolation module includes two poles
Pipe and pull down resistor；
Wherein, the anode of the diode is connect with the output end for starting level configuration module, and cathode is as the output
The output end of isolation module, and be grounded by the pull down resistor.
6. startup according to claim 2 configures multiplex circuit, which is characterized in that the control terminal of the second switch unit
It is grounded by filter capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820396517.0U CN207992988U (en) | 2018-03-22 | 2018-03-22 | A kind of startup configuration multiplex circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820396517.0U CN207992988U (en) | 2018-03-22 | 2018-03-22 | A kind of startup configuration multiplex circuit |
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| Publication Number | Publication Date |
|---|---|
| CN207992988U true CN207992988U (en) | 2018-10-19 |
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ID=63828879
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|---|---|---|---|
| CN201820396517.0U Active CN207992988U (en) | 2018-03-22 | 2018-03-22 | A kind of startup configuration multiplex circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111198527A (en) * | 2020-01-15 | 2020-05-26 | 北京实干兴邦科技有限公司 | FPGA-based GPIO output state control device, control method and application |
| CN111752223A (en) * | 2020-06-29 | 2020-10-09 | 配天机器人技术有限公司 | Signal configuration method, input/output device and computer storage medium |
-
2018
- 2018-03-22 CN CN201820396517.0U patent/CN207992988U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111198527A (en) * | 2020-01-15 | 2020-05-26 | 北京实干兴邦科技有限公司 | FPGA-based GPIO output state control device, control method and application |
| CN111198527B (en) * | 2020-01-15 | 2021-03-30 | 北京实干兴邦科技有限公司 | FPGA-based GPIO output state control device, control method and application |
| CN111752223A (en) * | 2020-06-29 | 2020-10-09 | 配天机器人技术有限公司 | Signal configuration method, input/output device and computer storage medium |
| CN111752223B (en) * | 2020-06-29 | 2022-04-01 | 配天机器人技术有限公司 | Signal configuration method, input/output device and computer storage medium |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hirain Technologies Co.,Inc. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer of Beijing Jingwei Hengrun Technology Co. Ltd. Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |
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| CP03 | Change of name, title or address |