CN207663327U - Realize the circuit of DC charging and USB port communication function - Google Patents

Realize the circuit of DC charging and USB port communication function Download PDF

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Publication number
CN207663327U
CN207663327U CN201721917600.XU CN201721917600U CN207663327U CN 207663327 U CN207663327 U CN 207663327U CN 201721917600 U CN201721917600 U CN 201721917600U CN 207663327 U CN207663327 U CN 207663327U
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semiconductor
oxide
metal
usb
modules
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阮绍云
许仿珍
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Shenzhen Waterward Information Co Ltd
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Guizhou Fortuneship Technology Co Ltd
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Abstract

The utility model is related to a kind of circuits for realizing DC charging and USB port communication function, including DC interface modules, usb interface module, master control GPIO modules, for selecting DC to charge or the DC USB charging selecting module of USB chargings and the communication identification module of USB communications for identification, the input terminal DC_IN of the DC interface modules and the input terminal VBUS_IN of usb interface module are connected to the feeder ear VBUS of master control GPIO modules by the DC USB selecting modules that charge；The input terminal DC_IN of the DC interface modules and input terminal VBUS_IN of usb interface module is connected to the detection voltage end VCDT of master control GPIO modules by communication identification module.The circuit of the utility model embodiment can realize DC charge functions and usb communication function simultaneously, facilitate user in the USB functions of carrying out being continuing with smart machine when DC chargings, improve user experience.

Description

Realize the circuit of DC charging and USB port communication function
Technical field
The utility model is related to electronic equipment interfaces field of circuit technology, more particularly to a kind of realization DC chargings and USB port The circuit of communication function.
Background technology
With the development of intelligent electronic device, when can use longer after once charging it is desirable to intelligent electronic device Between, it is also higher and higher to the battery capacity requirement of intelligent electronic device.
Existing intelligent electronic device, such as：Mobile phone, tablet computer etc. are charged and are communicated by USB port mostly, but It is that USB port is primarily used to communication, maximum output current is 0.5A, and the standard charging of existing intelligent electronic device is electric It is even higher that stream has all reached 1A.
In order to allow intelligent electronic device to obtain the charging current of bigger, generally use additionally increases the side of DC charging ports Formula, but the charging platform of existing intelligent electronic device only supports the single channel charging port based on USB, additional DC cradles Protection circuit is filled by simple counnter attack just directly to connect with the ends VBUS of USB port, master control GPIO module charging platforms are to VBUS The detection voltage VCDT of terminal voltage is divided by VBUS and is generated, and in many systems, the variations of only VCDT from low to high could touch The process that master control starts response charge event and usb communication event is sent out, and after into normal charging process, VCDT is also led Voltage monitoring of the control for input of charging, the true charging input voltage of VCDT reflections are correct realize necessary to charge function. So when DC charging adapters are inserted into DC charging ports and are charged, it is not responding to because DC charging adapters only add voltage of VBUS Agreement on the D+/D- signal wires of USB, so it is to insert DC charging adapters that charging platform, which can be identified correctly, hence into DC charging adapter charged states, and later again when USB port is inserted into USB data line, because of master control GPIO module charging platforms Middle VBUS and VCDT signals have been always maintained at voltage, due to the variations of VCDT not from low to high, so charging platform cannot be known The insert action of other USB line, thus also would not retriggered identification USB Type process, in this way, will cause carry out DC chargings When the not available situations of USB, user experience is poor.
Utility model content
The technical problem to be solved by the present invention is to the shortcomings in for the above-mentioned prior art, provide a kind of reality The circuit of existing DC charging and USB port communication function.
The utility model solves the technological means that technical problem uses and is to provide a kind of realizations DC charging and USB port communication work( The circuit of energy, including DC interface modules, usb interface module, the DC interface modules and usb interface module pass through master control GPIO Module is connected to rechargeable battery, further includes for selecting the DC-USB charging selecting modules and use that DC charges or USB charges In the communication identification module of identification usb communication, the input terminal of the input terminal DC_IN and usb interface module of the DC interface modules VBUS_IN is connected to the input terminal of DC-USB charging selecting modules, the output end connection of the DC-USB chargings selecting module To the feeder ear VBUS of master control GPIO modules；The input terminal of the input terminal DC_IN and usb interface module of the DC interface modules VBUS_IN is connected to the input terminal of communication identification module, and the output end of the communication identification module is connected to master control GPIO moulds The detection voltage end VCDT of block, the usb interface module further include data anode D+ and data negative terminal D-, the data anode D+ The signal anode USB_D+ and signal negative terminal USB_D- of master control GPI O modules are respectively connected to data negative terminal D-.
Further, the DC-USB chargings selecting module includes that the first counnter attack fills circuit module and the second counnter attack filling circuit Module, the input terminal DC_IN of the DC interface modules fill circuit module by first counnter attack and are connected to the master control GPIO The input terminal VBUS_IN of the feeder ear VBUS of module, the usb interface module fill circuit module connection by second counnter attack To the feeder ear VBUS of the master control GPIO modules.
Further, it includes the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor that first counnter attack, which fills circuit module, The drain electrode of Q3 and the 4th metal-oxide-semiconductor Q4, the first metal-oxide-semiconductor Q1 are connected to the input terminal DC_IN of the DC interface modules, described The source electrode of first metal-oxide-semiconductor Q1 is connected to the source electrode of the second metal-oxide-semiconductor Q2, and the drain electrode of the second metal-oxide-semiconductor Q2 is connected to described The feeder ear VBUS of master control GPIO modules, the grid short circuit of the grid and the second metal-oxide-semiconductor Q2 of the first metal-oxide-semiconductor Q1, described The grid of one metal-oxide-semiconductor Q1 is connected to the anode of the first diode D1, and the source electrode of the first metal-oxide-semiconductor Q1 is connected to the first diode The cathode of D1, the first diode D1 are parallel with first resistor R1, and the grid of the first metal-oxide-semiconductor Q1 also passes through second resistance R2 is connected to the drain electrode of third metal-oxide-semiconductor Q3, the source electrode ground connection of the third metal-oxide-semiconductor Q3, and the grid of the third metal-oxide-semiconductor Q3 passes through 3rd resistor R3 is connected to the drain electrode of the 4th metal-oxide-semiconductor Q4, and the source electrode of the 4th metal-oxide-semiconductor Q4 is grounded, the 4th metal-oxide-semiconductor Q4's Grid is connected to the first control output end VBUS_EN1 of the master control GPIO modules, and the drain electrode of the 4th metal-oxide-semiconductor Q4 is also logical The input terminal DC_IN that the 4th resistance R4 is connected to DC interface modules is crossed, the drain electrode of the 4th metal-oxide-semiconductor Q4 also passes through the 5th resistance R5 is grounded, and the grid of the third metal-oxide-semiconductor Q3 also passes through the first capacitance C1 ground connection, the 3rd resistor R3 the second diodes in parallel The anode of D2, the second diode D2 are connected to the grid of third metal-oxide-semiconductor Q3, and the cathode of the second diode D2 is connected to The drain electrode of 4th metal-oxide-semiconductor Q4.
Further, it includes the 5th metal-oxide-semiconductor Q5, the 6th metal-oxide-semiconductor Q6, the 7th metal-oxide-semiconductor that second counnter attack, which fills circuit module, The drain electrode of Q7 and the 8th metal-oxide-semiconductor Q8, the 5th metal-oxide-semiconductor Q5 are connected to the input terminal VBUS_IN of the usb interface module, The drain electrode of the source shorted of the source electrode and the 6th metal-oxide-semiconductor Q6 of the 5th metal-oxide-semiconductor Q5, the 6th metal-oxide-semiconductor Q6 is connected to master control The feeder ear VBUS of GPIO modules, the grid short circuit of the grid and the 6th metal-oxide-semiconductor Q6 of the 5th metal-oxide-semiconductor Q5, the 5th MOS The anode of the grid connection third diode D3 of pipe Q5, the cathode of the third diode D3 are connected to the source of the 5th metal-oxide-semiconductor Q5 Pole, the 6th resistance R6 of the third diode D3 parallel connections, the source electrode of the 5th metal-oxide-semiconductor Q5 also pass through the 7th resistance R7 and the 8th Resistance R8 ground connection, the grid of the 5th metal-oxide-semiconductor Q5 is also connected to the drain electrode of the 7th metal-oxide-semiconductor Q7 by the 9th resistance R9, described The source electrode of 7th metal-oxide-semiconductor Q7 is grounded, and the grid of the 7th metal-oxide-semiconductor Q7 connects the drain electrode of the 8th metal-oxide-semiconductor Q8, and the described 7th The grid of metal-oxide-semiconductor Q7 is additionally coupled on the circuit between the 7th resistance R7 and the 8th resistance R8, the source electrode of the 8th metal-oxide-semiconductor Q8 Ground connection, the grid of the 8th metal-oxide-semiconductor Q8 are connected to the line between the 4th resistance R4 and the 5th resistance R5 by the tenth resistance R10 On the road, the grid of the 8th metal-oxide-semiconductor Q8 also passes through the second capacitance C2 ground connection, the tenth resistance R10 the 4th diodes in parallel The cathode of D4, the 4th diode D4 are connected to the grid of the 8th metal-oxide-semiconductor Q8, and the anode of the 4th diode D4 connects It is connected on the circuit between the 4th resistance R4 and the 5th resistance R5.
Further, the communication identification module includes that D/C voltage tracks circuit module and USB voltage tracking circuit modules, The input terminal DC_IN of the DC interface modules tracks the detection that circuit module is connected to master control GPIO modules by the D/C voltage The input terminal VBUS_IN of voltage end VCDT, the usb interface module are connected to master by the USB voltage tracking circuits module The detection voltage end VCDT of GPIO modules is controlled, the detection voltage end VCDT is grounded by eleventh resistor R11.
Further, the D/C voltage tracking circuit module includes the 9th metal-oxide-semiconductor Q9, twelfth resistor R12, the 13rd electricity R13 and the 5th diode D5 is hindered, the drain electrode of the 9th metal-oxide-semiconductor Q9 is connected to DC interface modules by twelfth resistor R12 Input terminal DC_IN, the drain electrode of the 9th metal-oxide-semiconductor Q9 are also connected to the anode of the 5th diode D5 by thirteenth resistor R13, The cathode of the 5th diode D5 is connected to the detection voltage end VCDT of master control GPIO modules, the source of the 9th metal-oxide-semiconductor Q9 Pole is grounded, and the grid of the 9th metal-oxide-semiconductor Q9 is connected on the circuit between the 7th resistance R7 and the 8th resistance R8.
Further, the USB voltage tracking circuits module includes the tenth metal-oxide-semiconductor Q10, the 11st metal-oxide-semiconductor Q11, the tenth The drain electrode of four resistance R14, the 15th resistance R15 and the 6th diode D6, the tenth metal-oxide-semiconductor Q10 pass through the 14th electricity Resistance R14 is connected to the input terminal VBUS_IN of usb interface module, and the drain electrode of the tenth metal-oxide-semiconductor Q10 also passes through the described 15th Resistance R15 is connected to the anode of the 6th diode D6, and the cathode of the 6th diode D6 is connected to master control GPIO modules Detection voltage end VCDT, the grid of the tenth metal-oxide-semiconductor Q10 is connected to the grid of the third metal-oxide-semiconductor Q3, the described tenth The drain electrode of metal-oxide-semiconductor Q10 is additionally coupled to the drain electrode of the 11st metal-oxide-semiconductor Q11, and the source electrode of the 11st metal-oxide-semiconductor Q11 is grounded, The grid of the 11st metal-oxide-semiconductor Q11 is connected to the second control output end VBUS_EN2 of the master control GPIO modules.
Further, the detection voltage end VCDT of the master control GPIO modules is also grounded by third capacitance C3.
Further, the DC interface modules include DC connectors U1, the 16th resistance R16 and the 17th resistance R17, institute It includes G1 pins, G2 pins, G3 pins, G4 pins and DC+ pins, the G1 pins, G2 pins, G3 pipes to state DC connectors U1 Foot and G4 pins are grounded, and the DC+ pins are the input terminal DC_IN of the DC interface modules, and the DC+ pins are connected to institute The drain electrode of the first metal-oxide-semiconductor Q1 is stated, the DC+ pins are also connected to the of the master control GPIO modules by the 16th resistance R16 One control signal DCIN_DET, the first control signal DCIN_DET also passes through the 17th resistance R17 ground connection.
Further, the usb interface module includes USB connector U2, the 18th resistance R18, the 19th resistance R19, The USB connector U2 includes VBUS pins, D- pins, D+ pins, ID pins, GND pins, H6 pins, H7 pins, H8 pins With H9 pins, the H6 pins, H7 pins, H8 pins, H9 pins and GND pins are grounded, and the VBUS pins are connected to institute The drain electrode of the 5th metal-oxide-semiconductor Q5 is stated, the VBUS pins are also connected to the of the master control GPIO modules by the 18th resistance R18 Two control signal VBUSIN_DET, the second control signal VBUSIN_DET are grounded by the 19th resistance R19, The D- pins are the data negative terminal D-, and the D- pins are connected to signal the negative terminal USB_D-, the D of master control GPIO modules + pin is the data anode D+, and the D+ pins are connected to the signal anode USB_D+ of master control GPIO modules, the ID pins It is connected to the equipment identification end IDDIG of master control GPIO modules.
Using above-mentioned technical proposal, the utility model at least has the advantages that：The utility model is by being equipped with DC- USB charging selecting modules and communication identification module, the input terminal DC_IN of DC interface modules and the input terminal of usb interface module VBUS_IN is connected to feeder ear VBUS, the DC interface module of master control GPIO modules by DC-USB chargings selecting module Input terminal DC_IN and the input terminal VBUS_IN of usb interface module master control GPIO is connected to by the communication identification module The detection voltage end VCDT of module, when DC interface modules connect DC charging adapters, the input terminal DC_IN of DC interface modules is logical It crosses the DC-USB chargings selecting module and exports charging voltage to the feeder ear VBUS, charge for rechargeable battery, into DC Charged state, at this point, the branch pressure voltage of the input terminal DC_IN of detection voltage end VCDT response DC interface modules, detects voltage end The change triggers master control GPIO modules of the voltage of VCDT from low to high start the response to charging and USB events, but because of DC Charging adapter will not respond the agreement on the D+/D- signal wires of USB, so the identification of master control GPIO modules inserts DC chargings and fits Orchestration is without will be considered that usb communication.；USB data line, the confession of master control GPIO modules are inserted into after being inserted into DC charging adapters The voltage that electric end VBUS still responds the input terminal DC_IN of DC interface modules continues as rechargeable battery charging, is inserted into usb data Line line makes the voltage of the input terminal VBUS_IN of usb interface module get higher, this event passes through the second control signal VBUSIN_ DET notifies master control GPIO modules, master control GPIO modules to pass through to the first control output end VBUS_EN1 and the second control output end The suitable control of VBUS_EN2 so that the voltage on detection voltage end VCDT generates a variation from low to high, to touch Hair master control GPIO modules begin to respond to USB insertion events, and after the completion of this process, usb communication can be established, and charging input is still selected For the input terminal DC_IN of DC interface modules, and detect the input terminal DC_IN that voltage end VCDT is restored to reflection DC interface modules Branch pressure voltage, thus simultaneously realize DC charge functions and usb communication function, facilitate user to continue when carrying out DC chargings Using the USB functions of smart machine, user experience is improved.
Description of the drawings
Fig. 1 is the block diagram of circuit one embodiment that the utility model realizes DC chargings and USB port communication function.
Fig. 2 is that the utility model realizes that the circuit structure of circuit one embodiment of DC chargings and USB port communication function shows It is intended to.
The embodiments will be further described with reference to the accompanying drawings for the realization, functional characteristics and advantage of the utility model aim.
Specific implementation mode
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work The every other embodiment obtained, shall fall within the protection scope of the present invention.
It please refers to Fig.1 and Fig. 2, the utility model provides a kind of technical solution：A kind of realization DC charging and USB port communicate work( The circuit of energy, including DC interface modules 1, usb interface module 2, the DC interface modules 1 and usb interface module 2 pass through master control GPIO modules 3 are connected to rechargeable battery 100, it is characterised in that：Further include for selecting the DC-USB that DC charges or USB charges The selecting module 4 that charges and for identification the communication identification module 5 of usb communication, the input terminal DC_IN of the DC interface modules 1 The input terminal of DC-USB charging selecting modules 4 is connected to the input terminal VBUS_IN of usb interface module 2, the DC-USB fills The output end of electric selecting module 4 is connected to the feeder ear VBUS of master control GPIO modules 3；The input terminal DC_ of the DC interface modules 1 The input terminal VBUS_IN of IN and usb interface module 2 is connected to the input terminal of communication identification module 5, the communication identification module 5 output end is connected to the detection voltage end VCDT of master control GPIO modules 3, and the usb interface module 2 further includes data anode D+ The signal anode USB_D of master control GPIO modules 3 is respectively connected to data negative terminal D-, the data anode D+ and data negative terminal D- + and signal negative terminal USB_D-.
The effect of the DC-USB chargings selecting module 4 is the input terminal DC_IN and USB interface mould from DC interface modules 1 The real input all the way as charging is selected in the input terminal VBUS_IN of block 2.And on the one hand the effect of communication identification module 5 is So that detection voltage end VCDT reflections is made to select the partial pressure of charging input in charging process, on the other hand there ought be USB insertions No matter how the input terminal DC_IN states of DC interface modules 1 all ensure that the voltage on detection voltage end VCDT generates when event Variation from low to high, to trigger response of the master control GPIO modules 3 to usb communication, when implementing, the master control GPIO modules 3 are equipped with the voltage change that the first control signal DCIN_DET is used to detect the input terminal DC_IN of the DC interface modules 1, institute State the input terminal that master control GPIO modules 3 are used to detect the usb interface module 2 equipped with the second control signal VBUSIN_DET The voltage change of VBUS_IN, the master control GPIO modules 3 are equipped with the first control output end VBUS_EN1 and the second control output end VBUS_EN2, the input terminal VBUS_ of input terminal DC_IN and the usb interface module 2 for controlling the DC interface modules 1 The voltage break-make of IN and the detection voltage end VCDT, the first control output end VBUS_EN1 is for controlling the DC interfaces The voltage of the input terminal DC_IN of module 1 is exported to the break-make of the detection voltage end VCDT, second control output end The voltage for the input terminal VBUS_IN that VBUS_EN2 is used to control the usb interface module 2 is exported to the detection voltage end The break-make of VCDT.
In the specific implementation, the DC interface modules 1 are used to be attached with external DC charging adapters, the USB Interface module 2 with USB data line for connecting, the DC-USB charging selecting modules 4 and DC interface modules 1 and USB interface mould The output end of block 2 is connected for selecting DC charge modes or USB charge modes, specifically, when being only inserted DC charging adapters When, DC-USB charging selecting module 4 responds DC charging adapters and exports to the of the input terminal DC_IN of DC interface modules 1 One charging voltage, into DC charge modes to master control GPI O modules；When being only inserted USB data line, the DC-USB chargings choosing It selects the response of module 4 USB data line to export to the second charging voltage of the input terminal VUBS_IN of usb interface module 2, be filled into USB Power mode, when being inserted into DC charging adapters and USB data line simultaneously, the DC-USB chargings selecting module 4 responds DC chargings The first charging voltage to the master control GPIO modules 3 of adapter output charge to rechargeable battery, into DC charge modes, from And improve charge efficiency；The input terminal DC_IN of the communication identification module 5 and DC interface modules 1 and usb interface module 2 it is defeated Enter VBUS_IN is held to connect, by the detection for controlling DC interface modules 1 and 2 output end of usb interface module and master control GPIO modules 3 The break-make of voltage end VCDT, to make master control GPIO modules 3 identify the insertion of DC charging adapters and/or USB data line, and When USB data line is inserted into, the agreement on the D+/D- signal wires of USB is responded, realizes usb communication function.
The present embodiment is by being equipped with DC-USB charging selecting modules 4 and communication identification module 5, the input of DC interface modules 1 The input terminal VBUS_IN of end DC_IN and usb interface module 2 is connected to master control by DC-USB chargings selecting module 4 The input terminal DC_IN of feeder ear VBUS, the DC interface module 1 of GPIO modules 3 and the input terminal VBUS_IN of usb interface module 2 are equal The detection voltage end VCDT of master control GPIO modules 3 is connected to by the communication identification module 5, when DC interface modules 1 connect DC When charging adapter, the input terminal DC_IN of DC interface modules 1 exports charging voltage by DC-USB charging selecting modules 4 It to the feeder ear VBUS, charges for rechargeable battery, into DC charged states, at this point, detection voltage end VCDT responses DC connects The branch pressure voltage of the input terminal DC_IN of mouth mold block 1, DC chargers are not responding to the agreement on the D+/D- signal wires of USB, master control The identification of GPIO modules 3 inserts DC charging adapters without will be considered that usb communication；It is inserted into after being inserted into DC charging adapters USB data line, the voltage of the input terminal DC_IN of the feeder ear VBUS response DC interface modules 1 of master control GPIO modules 4 continues as can Rechargeable battery charge, be inserted into USB data line make usb interface module 2 input terminal VBUS_IN's and voltage is got higher so that in master It controls the voltage on the detection voltage end VCDT of GPIO modules 3 and generates a variation from low to high, to trigger master control GPIO moulds Block 3 begins to respond to USB insertion events, and after the completion of this process, usb communication can be established, and charging input is still chosen to be DC interface moulds The input terminal DC_IN of block 1, and detect the partial pressure electricity that voltage end VCDT is restored to the input terminal DC_IN of reflection DC interface modules 1 Pressure；Specifically, being inserted into USB data line line makes the voltage of the input terminal VBUS_IN of usb interface module 2 get higher, this event passes through Second control signal VBUSIN_DET notice master control GPIO modules 3, master control GPIO modules 3 are by the first control output end The suitable control of VBUS_EN1 and the second control output end VBUS_EN2 so that the voltage on detection voltage end VCDT generates one A variation from low to high begins to respond to USB insertion events to trigger master control GPIO modules 3, after the completion of this process, USB Communication can establish, and charging input is still chosen to be the input terminal DC_IN of DC interface modules 1, and detects voltage end VCDT and be restored to The branch pressure voltage for reflecting the input terminal DC_IN of DC interface modules 1, can realize DC charge functions and usb communication function simultaneously, convenient User improves user experience in the USB functions of carrying out being continuing with smart machine when DC chargings.
In one alternate embodiment, DC-USB charging selecting module 4 includes that the first counnter attack fills circuit module and the Two counnter attacks fill circuit module, and the input terminal DC_IN of the DC interface modules 1 fills circuit module by first counnter attack and is connected to The input terminal VBUS_IN of the feeder ear VBUS of the master control GPIO modules 3, the usb interface module 2 pass through second counnter attack Fill the feeder ear VBUS that circuit module is connected to the master control GPIO modules 3.
When implementing, when only DC charging adapters are inserted into or are inserted into DC charging adapters and USB data line simultaneously, First counnter attack fills circuit module conducting and second counnter attack fills circuit module cut-off, at this time by DC charging adapters into Row charging, and it is avoided that DC charging adapters export that charging voltage to the feeder ear VBUS of the master control GPIO modules 3 is counter to be filled To usb interface module 2, and then burn out USB data line and external equipment；When only USB data line is inserted into, first counnter attack It fills circuit module to end and second counnter attack filling circuit module conducting, at this point, being charged by USB data line, and can keep away Exempt from USB data line to export to the anti-filling of the charging voltage of the feeder ear VBUS of the master control GPIO modules 3 to DC interface modules 1, carry High safety in utilization.
In one alternate embodiment, first counnter attack fill circuit module include the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, The drain electrode of third metal-oxide-semiconductor Q3 and the 4th metal-oxide-semiconductor Q4, the first metal-oxide-semiconductor Q1 are connected to the input terminal of the DC interface modules 1 DC_IN, the source electrode of the first metal-oxide-semiconductor Q1 are connected to the source electrode of the second metal-oxide-semiconductor Q2, the drain electrode of the second metal-oxide-semiconductor Q2 It is connected to the feeder ear VBUS of the master control GPIO modules 3, the grid of the grid and the second metal-oxide-semiconductor Q2 of the first metal-oxide-semiconductor Q1 The grid of short circuit, the first metal-oxide-semiconductor Q1 is connected to the anode of the first diode D1, the source electrode connection of the first metal-oxide-semiconductor Q1 To the cathode of the first diode D1, the first diode D1 is parallel with first resistor R1, and the grid of the first metal-oxide-semiconductor Q1 is also The drain electrode of third metal-oxide-semiconductor Q3, the source electrode ground connection of the third metal-oxide-semiconductor Q3, the third metal-oxide-semiconductor are connected to by second resistance R2 The grid of Q3 is connected to the drain electrode of the 4th metal-oxide-semiconductor Q4 by 3rd resistor R3, and the source electrode ground connection of the 4th metal-oxide-semiconductor Q4 is described The grid of 4th metal-oxide-semiconductor Q4 is connected to the first control output end VBUS_EN1 of the master control GPIO modules 3, the 4th MOS The drain electrode of pipe Q4 is also connected to the input terminal DC_IN of DC interface modules 1, the leakage of the 4th metal-oxide-semiconductor Q4 by the 4th resistance R4 Also by the 5th resistance R5 ground connection, the grid of the third metal-oxide-semiconductor Q3 also passes through the first capacitance C1 ground connection, the 3rd resistor for pole The anode of the second diode D2, the second diode D2 of R3 parallel connections is connected to the grid of third metal-oxide-semiconductor Q3, the two or two pole The cathode of pipe D2 is connected to the drain electrode of the 4th metal-oxide-semiconductor Q4.
It includes the 5th metal-oxide-semiconductor Q5, the 6th metal-oxide-semiconductor Q6, the 7th metal-oxide-semiconductor Q7 and the 8th that second counnter attack, which fills circuit module, The drain electrode of metal-oxide-semiconductor Q8, the 5th metal-oxide-semiconductor Q5 are connected to the input terminal VBUS_IN of the usb interface module 2, and the described 5th The drain electrode of the source electrode of metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 and source shorted, the 6th metal-oxide-semiconductor Q6 is connected to master control GPIO modules 3 Feeder ear VBUS, the grid short circuit of the grid and the 6th metal-oxide-semiconductor Q6 of the 5th metal-oxide-semiconductor Q5, the grid of the 5th metal-oxide-semiconductor Q5 Pole connects the anode of third diode D3, and the cathode of the third diode D3 is connected to the source electrode of the 5th metal-oxide-semiconductor Q5, and described the Three diode D3 the 6th resistance R6 of parallel connection, the source electrode of the 5th metal-oxide-semiconductor Q5 are also connect by the 7th resistance R7 and the 8th resistance R8 The grid on ground, the 5th metal-oxide-semiconductor Q5 is also connected to the drain electrode of the 7th metal-oxide-semiconductor Q7, the 7th metal-oxide-semiconductor by the 9th resistance R9 The source electrode of Q7 is grounded, and the grid of the 7th metal-oxide-semiconductor Q7 connects drain electrode and the grid of the 7th metal-oxide-semiconductor Q7 of the 8th metal-oxide-semiconductor Q8 Pole is additionally coupled on the circuit between the 7th resistance R7 and the 8th resistance R8, the source electrode of the 8th metal-oxide-semiconductor Q8 ground connection, and described the The grid of eight metal-oxide-semiconductor Q8 is connected to by the tenth resistance R10 on the circuit between the 4th resistance R4 and the 5th resistance R5, and described The grid of eight metal-oxide-semiconductor Q8 is also by the second capacitance C2 ground connection, the tenth resistance R10 parallel connections the 4th diode D4, and the described 4th The cathode of diode D4 is connected to the grid of the 8th metal-oxide-semiconductor Q8, and the anode of the 4th diode D4 is connected to the 4th electricity It hinders on the circuit between R4 and the 5th resistance R5.
When implementing, the first control output end VBUS_EN1 acquiescence output low levels of the master control GPIO modules 3, when only When being inserted into USB data line, at this point, the input terminal DC_IN due to DC interface modules 1 does not have input voltage, lead to third metal-oxide-semiconductor Q3 End with the 8th metal-oxide-semiconductor Q8, due to the cut-off of third metal-oxide-semiconductor Q3 so that the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 are turned off, and are kept away The voltage for exempting from the feeder ear VBUS of master control GPIO modules 3 moves back to DC interface modules 1；The input terminal of the usb interface module 2 The voltage of VBUS_IN is got higher by low, described due to the effect of the parasitic diode (not shown) of the inside of the 5th diode Q5 The voltage of the input terminal VBUS_IN of usb interface module 2 is added on the 7th resistance R7, due to the 8th metal-oxide-semiconductor Q8 cut-offs so that the Seven resistance R7 and the 8th resistance R8 partial pressures are so that the 7th metal-oxide-semiconductor Q7 conductings, the 6th resistance R6 and the 9th resistance R9 partial pressures make The 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 conductings are obtained, to realize USB charge functions.
When being only inserted D/C adapter or being inserted into D/C adapter and USB data line simultaneously, the DC interface modules 1 it is defeated Enter to hold the voltage of DC_IN to be got higher by low, makes the 4th since the first control output end VBUS_EN1 gives tacit consent to output low level Metal-oxide-semiconductor Q4 cut-off, the 4th resistance R4 and the 5th resistance R5 are divided so that third metal-oxide-semiconductor Q3 and the 8th metal-oxide-semiconductor Q8 conductings, due to the Eight metal-oxide-semiconductor Q8 are connected so that the 7th metal-oxide-semiconductor Q7 cut-offs are so that the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 cut-offs, prevent master control The voltage of the feeder ear VBUS of GPIO modules 3 moves back to usb interface module 2；And since third metal-oxide-semiconductor Q3 is connected so that first Resistance R1 and second resistance R2 partial pressure conducting the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2, realizes DC charge functions.
In one alternate embodiment, the communication identification module 5 include D/C voltage tracking circuit module and USB voltages with Track circuit module, the input terminal DC_IN of the DC interface modules 1 track circuit module by the D/C voltage and are connected to master control The input terminal VBUS_IN of the detection voltage end VCDT of GPIO modules 3, the usb interface module 2 pass through the USB voltage-tracings Detection the voltage end VCDT, the detection voltage end VCDT that circuit module is connected to master control GPIO modules 3 pass through eleventh resistor R11 is grounded.
When implementing, the D/C voltage tracking circuit module is used to track the voltage of DC charging adapters, the USB voltages Tracking circuit module is used to track the voltage of USB data line, when only DC charging adapters are inserted into, master control GPIO modules 3 Detect the voltage of the input terminal DC_IN of voltage end VCDT response DC interface modules 1；It is main when only USB data line is inserted into Control the voltage of the output end VBUS_IN of the detection voltage end VCDT response usb interface modules 2 of GPIO modules 3；It is inserted when simultaneously When entering USB data line and D/C adapter, the detection voltage end VCDT of master control GPIO modules 3 finally responds the defeated of DC interface modules 1 Entering to hold the voltage of DC_IN, when having USB data line insertion, no matter what state the input terminal DC_IN of DC interface modules 1 is in, No matter the input terminal DC_IN of the DC interface modules 1 exports high level or exports low level, and USB identification modules can be in master It is being examined under first control output end VBUS_EN1 of 3 output of control GPIO modules and the second control output end VBUS_EN2 signals cooperation The voltage surveyed on voltage end VCDT generates variation from low to high, to trigger the phase that master control GPIO modules 3 recognize USB insertions Agreement on D+/D- signal wires of the pass process to respond USB, can normally start USB processes, while realizing DC charge functions With usb communication function.
In one alternate embodiment, the D/C voltage tracking module includes the 9th metal-oxide-semiconductor Q9, twelfth resistor R12, the The drain electrode of 13 resistance R13 and the 5th diode D5, the 9th metal-oxide-semiconductor Q9 are connected to DC interfaces by twelfth resistor R12 The input terminal DC_IN of module 1, the drain electrode of the 9th metal-oxide-semiconductor Q9 are also connected to the 5th diode D5 by thirteenth resistor R13 Anode, the cathode of the 5th diode D5 is connected to detection the voltage end VCDT, the 9th MOS of master control GPIO modules 3 The source electrode of pipe Q9 is grounded, and the grid of the 9th metal-oxide-semiconductor Q9 is connected to the line between the 7th resistance R7 and the 8th resistance R8 On the road.
The USB voltage tracking modules include the tenth metal-oxide-semiconductor Q10, the 11st metal-oxide-semiconductor Q11, the 14th resistance R14, the tenth The drain electrode of five resistance R15 and the 6th diode D6, the tenth metal-oxide-semiconductor Q10 are connected to USB by the 14th resistance R14 The input terminal VBUS_IN of interface module 2, the drain electrode of the tenth metal-oxide-semiconductor Q10 are also connected to by the 15th resistance R15 The cathode of the anode of the 6th diode D6, the 6th diode D6 is connected to the detection voltage end of master control GPIO modules 3 VCDT, the grid of the tenth metal-oxide-semiconductor Q10 are connected to the grid of the third metal-oxide-semiconductor Q3, the drain electrode of the tenth metal-oxide-semiconductor Q10 It is additionally coupled to the drain electrode of the 11st metal-oxide-semiconductor Q11, the source electrode ground connection of the 11st metal-oxide-semiconductor Q11, the 11st metal-oxide-semiconductor The grid of Q11 is connected to the second control output end VBUS_EN2 of the master control GPIO modules 3.
When implementing, the second control output end VBUS_EN2 acquiescence output low levels of the master control GPIO modules 3, when only When being inserted into USB data line, since the input terminal DC_IN of DC interface modules 1 is in low level always, lead to third metal-oxide-semiconductor Q3, the Eight metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 cut-offs, and then lead to the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 cut-offs, and due to the 8th Metal-oxide-semiconductor Q8 cut-offs so that the 7th metal-oxide-semiconductor Q7 conductings are so that the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 are connected, due to second Control output end VBUS_EN2 acquiescence outputs low level makes the 11st metal-oxide-semiconductor Q11 cut-offs, and since the tenth metal-oxide-semiconductor Q10 is cut Only so that the voltage of the input terminal VBUS_I N of usb interface module 2 passes through the 14th resistance R14, the 15th resistance R15, the 6th The partial pressure of diode D6 and eleventh resistor R11 is added to detection voltage end VCDT, master control the GPIO module 3 of master control GPIO modules 3 The agreement on D+/D- signal wires of the correlated process of USB insertions to respond USB is recognized, realizes USB charge functions and USB Communication function.
When being inserted into DC charging adapters after being inserted into USB data line, the electricity of the input terminal DC_IN of DC interface modules 1 Pressure is got higher by low, and at this time since the first control output end VBUS_EN1 gives tacit consent to output low level, the 4th metal-oxide-semiconductor Q4 ends, So that third metal-oxide-semiconductor Q3, the 8th metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 conductings, so that the first metal-oxide-semiconductor Q1 and second Metal-oxide-semiconductor Q2 conductings, the 8th metal-oxide-semiconductor Q8 is connected so that the 7th metal-oxide-semiconductor Q7 and the 9th metal-oxide-semiconductor Q9 cut-offs are so that the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 cut-offs, and the 9th metal-oxide-semiconductor Q9 ends so that the voltage of the input terminal DC_IN of DC interface modules 1 passes through the 12 resistance R12, thirteenth resistor R13, the 5th diode D5 and eleventh resistor R11 partial pressure be added to master control GPIO modules 3 Detection voltage end VCDT, since the tenth metal-oxide-semiconductor Q10 turn-on times are slightly more late than the 9th metal-oxide-semiconductor Q9 deadlines, in the 9th MOS Pipe Q9 had been switched off and in this period that the tenth metal-oxide-semiconductor Q10 is not yet connected, due to the 5th diode D5 and the 6th diode The detection voltage end VCDT of D6, master control GPIO module 3 is input terminal DC_IN and usb interface module 2 from DC interface modules 1 Select voltage high in input terminal VBUS_IN, after the tenth metal-oxide-semiconductor Q10 conductings, the detection voltage end of master control GPIO modules 3 VCDT only reflects the partial pressure of the input terminal DC_IN of DC interface modules 1, the detection voltage end of master control GPIO modules 3 in whole process Without apparent voltage fluctuation on VCDT, master control GPIO modules 3 not will be considered that be changed in USB port, and usb communication is continued, And it is to be in DC charged states at this time.
In another embodiment, when only DC charging adapters are inserted into, the input terminal DC_IN's of DC interface modules 1 Voltage is got higher by low, since the first control output end VBUS_EN1 gives tacit consent to output low level, so the 4th metal-oxide-semiconductor Q4 is cut Only, so that third metal-oxide-semiconductor Q3, the 8th metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 conductings, so that the first metal-oxide-semiconductor Q1 and the Two metal-oxide-semiconductor Q2 conductings, the voltage of the input terminal DC_IN of DC interface modules 1 are added to by the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 The feeder ear VBUS of master control GPIO modules 3, since the 8th metal-oxide-semiconductor Q8 is connected so that the 7th metal-oxide-semiconductor Q7 ends, so that the 5th Metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 cut-offs, prevent the voltage of the feeder ear VBUS of master control GPIO modules 3 from moving back to usb interface module On 2；And since the 8th metal-oxide-semiconductor Q8 is connected so that the 9th metal-oxide-semiconductor Q9 ends, so that the input terminal DC_IN of DC interface modules 1 Voltage by being added to master after twelfth resistor R12, thirteenth resistor R13, the 5th diode D5 and eleventh resistor R11 partial pressure The detection voltage end VCDT of GPIO modules 3 is controlled, and since the input terminal so that usb interface module 2 is connected in the tenth metal-oxide-semiconductor Q10 The influence of VBUS_IN to the detection voltage end VCDT of master control GPIO modules 3 are cut off, and detection voltage end VCDT only reflects DC interfaces The partial pressure of the input terminal DC_IN of module 1, detection voltage end VCDT triggering master control GPIO modules 3 start USB correlated processes, because of DC Charging adapter only adds feeder ear voltage of VBUS and is not responding to the agreement on the D+/D- signal wires of USB, so master control GPIO modules 3 identifications are to insert DC charging adapters to enter DC charged states.
USB data line, the electricity of the input terminal VBUS_IN of usb interface module 2 are inserted into after being inserted into DC charging adapters Pressure is got higher by low, after master control GPIO modules 3 detect this variation by the first control signal VBUSIN_DET, described in control First control output end VBUS_EN1 output high level makes the 4th metal-oxide-semiconductor Q4 conductings, so that third metal-oxide-semiconductor Q3, the 8th Metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 cut-offs, since third metal-oxide-semiconductor Q3 ends so that the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 is cut Only, since the 8th metal-oxide-semiconductor Q8 ends the 7th metal-oxide-semiconductor Q7 and the 9th metal-oxide-semiconductor Q9 is both turned on, and since the 7th metal-oxide-semiconductor Q7 is led It is logical that 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 is both turned on, so that the feeder ear VBUS of master control GPIO modules 3 is connect by USB The input terminal VBUS_IN drivings of mouth mold block 2.
And due to the 9th metal-oxide-semiconductor Q9 conductings so that the voltage of the input terminal DC_IN of DC interface modules 1 cannot be transferred to master The detection voltage end VCDT of GPIO modules 3 is controlled, at this point, master control GPIO modules 3 control the second control output end VBUS_EN2 outputs High level makes the 11st metal-oxide-semiconductor Q11 conductings, to but also the voltage of the input terminal VBUS_IN of usb interface module 2 cannot Be transferred to master control GPIO modules 3 detection voltage end VCDT, master control GPIO module 3 think USB port be in be not inserted into state；Then 3 inside of master control GPIO modules will automatically reset with the relevant states of USB, and later, secondary control second controls master control GPIO modules 3 again Output end VBUS_EN2 exports low level so that the 11st metal-oxide-semiconductor Q11 cut-offs, at this point, due to the 9th metal-oxide-semiconductor Q9 conductings and the 11 metal-oxide-semiconductor Q11 cut-offs so that the partial pressure of the only voltage of the input terminal VBUS_IN of usb interface module 2 is added to master control GPIO The variation of the voltage of the detection voltage end VCDT of module 3, this detection voltage end VCDT from low to high will trigger master control GPIO moulds The correlated process that block 3 is inserted into automatically into USB.After the completion of the correlated process that USB is inserted into, master control GPIO modules 3 are by described first Control output end VBUS_EN1 output voltages are set low again so that the 4th metal-oxide-semiconductor Q4 cut-off, so that third metal-oxide-semiconductor Q3, the Eight metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 conductings, so that the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 are connected and the 5th metal-oxide-semiconductor Q5 With the 6th metal-oxide-semiconductor Q6 cut-offs, the feeder ear VBUS of the master control GPIO modules 3 made changes to be driven by the input terminal DC_IN of DC interface modules 1 It is dynamic to enter DC charged states.
In the specific implementation, it can make the 5th metal-oxide-semiconductor Q5 by adjusting the resistance value of the 5th resistance R5 and the tenth resistance R10 And the 6th metal-oxide-semiconductor Q6 it is suitable by the end of the time interval between the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 conductings, to ensure DC Interface module 1 and 2 two-way power supply of usb interface module make the feeder ear VBUS of master control GPIO modules 3 while not being shorted with each other The fluctuation of upper generation is in tolerance interval, to not cause the erroneous judgement of master control GPIO modules 3.
And since the conducting of the 8th metal-oxide-semiconductor Q8 makes the 9th metal-oxide-semiconductor Q9 cut-offs, so that the input of DC interface modules 1 The voltage of end DC_IN can be added on the detection voltage end VCDT of master control GPIO modules 3, wherein the conducting of the tenth metal-oxide-semiconductor Q10 Cut-off than the 9th metal-oxide-semiconductor Q9 is slightly late, the 9th metal-oxide-semiconductor Q9 has been switched off and this section that the tenth metal-oxide-semiconductor Q10 is not yet connected is very short Time in, due to the effect of the 5th diode D5 and the 6th diode D6, the detection voltage end VCDT of master control GPIO modules 3 from The high person of voltage is selected in both the input terminal DC_IN of DC interface modules 1 and the input terminal VBUS_IN of usb interface module 2, and is worked as After tenth metal-oxide-semiconductor Q10 conductings, the voltage of the input terminal VBUS_IN of usb interface module 2 cannot be added to master control GPIO modules 3 The detection voltage end VCDT of detection voltage end VCDT, master control GPIO module 3 only reflect the input terminal DC_IN of DC interface modules 1 Voltage, the voltage detected described in such whole process on voltage end VCDT obviously do not fluctuate, master control GPIO modules 3 It not will be considered that and changed on usb interface module 2, usb communication is continued, and enters DC charged states at this time.
In one alternate embodiment, the detection voltage end VCDT of the master control GPIO modules 3 also passes through third capacitance C3 Ground connection.
The present embodiment is grounded by the detection voltage end VCDT in master control GPIO modules 3 by third capacitance C3, and described the Three capacitance C3 are electric capacity of voltage regulation, can effectively stablize the voltage of the detection voltage end VCDT, avoid the mistake of master control GPIO modules 3 Sentence, improves circuit stability.A certain range of fluctuation is not interfering with 3 charge function of master control GPIO modules just in the VCDT short time Often work.
In one alternate embodiment, the DC interface modules 1 include DC connectors U1, the 16th resistance R16 and the tenth Seven resistance R17, the DC connectors U1 include G1 pins, G2 pins, G3 pins, G4 pins and DC+ pins, the G1 pipes Foot, G2 pins, G3 pins and G4 pins are grounded, and the DC+ pins are the input terminal DC_IN of the DC interface modules 1, described DC+ pins are connected to the drain electrode of the first metal-oxide-semiconductor Q1, and the DC+ pins are also connected to the master by the 16th resistance R16 The first control signal DCIN_DET, the first control signal DCIN_DET of GPIO modules 3 is controlled also by the 17th electricity Hinder R17 ground connection.
The usb interface module 2 includes USB connector U2, the 18th resistance R18, the 19th resistance R19, and the USB connects It includes VBUS pins, D- pins, D+ pins, ID pins, GND pins, H6 pins, H7 pins, H8 pins and H9 pins to meet device U2, The H6 pins, H7 pins, H8 pins, H9 pins and GND pins are grounded, and the VBUS pins are the usb interface modules 2 Input terminal VBUS_IN, the VBUS pins are connected to the drain electrode of the 5th metal-oxide-semiconductor Q5, and the VBUS pins also pass through 18 resistance R18 are connected to the second control signal VBUSIN_DET of the master control GPIO modules 3, the second control input End VBUSIN_DET is grounded by the 19th resistance R19, and the D- pins are the data negative terminal of the usb interface module 2 D-, the D- pins are connected to the signal negative terminal USB_D- of master control GPIO modules 3, and the D+ pins are the usb interface module 2 Data anode D+, the D+ pins are connected to the signal anode USB_D+ of master control GPIO modules 3, and the ID pins are connected to master The equipment for controlling GPIO modules 3 identifies end IDDIG.
When implementing, when being inserted into DC charging adapters, the input terminal DC_IN of DC interface modules 1 passes through the 16th resistance R16 outputs are divided to the first control signal DCIN_DET of master control GPIO modules 3, and the input terminal of the usb interface module 2 VBUS_IN passes through the 18th resistance R18 outputs partial pressure to the second control signal VBUSIN_DET of master control GPIO modules 3, master Controlling GPIO modules 3 can be according to the voltage of the first control signal DCIN_DET and the second control signal VBUSIN_DET The insertion of variation identification USB data line and DC charging adapters, and then it is specifically chosen charging path and usb communication mode.
The utility model realizes that the operation principle of the circuit of DC chargings and USB port communication function is as follows：
S1 is first inserted into USB data line when original state is USB data line and DC charging adapters are not inserted into, this When, since the input terminal DC_IN of DC interface modules 1 does not have voltage, so no matter the first control output end VBUS_EN1 is defeated Go out low level or high level, third metal-oxide-semiconductor Q3, the 8th metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 are cut-off, third metal-oxide-semiconductor Q3 Cut-off the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 are turned off, avoid the voltage of the feeder ear VBUS of master control GPIO modules 3 Move back to DC interface modules 1；And the voltage of the input terminal VBUS_IN of usb interface module 2 is due to the parasitism two of the 5th metal-oxide-semiconductor Q5 The effect of pole pipe is added on the 7th resistance R7, since the partial pressure of the 7th resistance R7 and the 8th resistance R8 acts on so that the 7th metal-oxide-semiconductor Q7 is connected, so that the 6th resistance R6 and the 9th resistance R9 partial pressure conductings the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6, such USB The voltage of the input terminal VBUS_IN of interface module 2 drives master control GPIO modules 3 by the 5th metal-oxide-semiconductor Q6 and the 6th metal-oxide-semiconductor Q6 Feeder ear VBUS；The partial pressure of 7th resistance R7 and the 8th resistance R8 is also simultaneously so that the 9th metal-oxide-semiconductor Q9 conductings, make the 5th diode The voltage signal of D5 reverses biased, the input terminal DC_IN of DC interface modules 1 will not generate shadow to the detection voltage end VCDT It rings.
Since the second control output end VBUS_EN2 gives tacit consent to output low level so that the 11st metal-oxide-semiconductor Q11 cut-offs, The tenth metal-oxide-semiconductor Q10 and the 11st metal-oxide-semiconductor Q11 is turned off so that the voltage of the input terminal VBUS_IN of usb interface module 2 14th resistance R14, the 15th resistance R15, the 6th diode D6 and eleventh resistor R11 carry out partial pressure and are added to the detection electricity Pressure side VCDT, in this case, the master control GPIO modules 3 normally start USB processes and complete usb communication and USB charging processes.
S2 is inserted into DC charging adapters in the case where USB data line is already inserted into, since first control is defeated Outlet VBUS_EN1 acquiescence output low levels, so the partial pressure of the 4th metal-oxide-semiconductor Q4 cut-offs, the 4th resistance R4 and the 5th resistance R5 are defeated Go out so that third metal-oxide-semiconductor Q3, the 8th metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 conductings, wherein due to the effect of the 4th diode D4, So that the turn-on time of the 8th metal-oxide-semiconductor Q8 is slightly early, the conducting of the 8th metal-oxide-semiconductor Q8 makes the 7th metal-oxide-semiconductor Q7 cut-offs, so that the The company of the input terminal VBUS_IN and the feeder ear VBUS of five metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 cut-off cut-out usb interface modules 2 It connects, the voltage of the feeder ear VBUS is prevented to move back to usb interface module 2, and the conducting of third metal-oxide-semiconductor Q3 makes the first MOS Pipe Q1 and the second metal-oxide-semiconductor Q2 conductings so that the feeder ear VBUS changes the input terminal DC_IN drivings by DC interface modules 1.
Resistance value by adjusting 3rd resistor R3 and the tenth resistance R10 can make the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 It is suitable by the end of the time interval between the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 conductings, with ensure to be inserted into DC charging adapters and This two-way power supply of USB data line makes the fluctuation generated on the feeder ear VBUS in receivable range while not being shorted with each other It is interior, to not cause the erroneous judgement of master control GPIO modules 3.For the detection voltage end VCDT of master control GPIO modules 3, due to Eight metal-oxide-semiconductor Q8 are connected quickly so that the 9th metal-oxide-semiconductor Q9 ends quickly, so that the electricity of the input terminal DC_IN of DC interface modules 1 Pressure partial pressure can be added on the detection voltage end VCDT, and the turn-on time of the tenth metal-oxide-semiconductor Q10 is than the 9th metal-oxide-semiconductor Q9 deadlines It is slightly late, the 9th metal-oxide-semiconductor Q9 has been switched off and in time that this section that the tenth metal-oxide-semiconductor Q10 is not yet connected is very short, due to the five or two The presence of pole pipe D5 and the 6th diode D6, the detection voltage end VCDT be from the input terminal DC_IN of DC interface modules 1 and The high person of voltage is selected in input terminal VBUS_IN the two of usb interface module 2, and after the tenth metal-oxide-semiconductor Q10 conductings, the detection Voltage end VCDT only reflects the voltage of the input terminal DC_IN of DC interface modules 1.Do not have on the detection voltage end VCDT described in this way There is apparent voltage fluctuation, master control GPIO modules 3 not will be considered that be changed on usb interface module 2, and usb communication is continued, and Practical charging path has been switched to DC charged states, and detect voltage end VCDT reflections is effective charging paths DC interface moulds The voltage of the input terminal DC_IN of block 1.
S3, when the state that USB data line and DC charging adapters are all inserted into, during usb communication carries out, charging path connects for DC The input terminal DC_IN of mouth mold block 1 extracts DC charging adapters at this time, and the voltage of the input terminal DC_IN of DC interface modules 1 is by height It is lower so that third metal-oxide-semiconductor Q3, the 8th metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 are turned off, wherein when the cut-off of third metal-oxide-semiconductor Q3 Between it is slightly more early than the deadline of the tenth metal-oxide-semiconductor Q10, since the cut-off of third metal-oxide-semiconductor Q3 makes the first metal-oxide-semiconductor Q1 and the 2nd MOS Pipe Q2 cut-offs, and since the 8th metal-oxide-semiconductor Q8 ends so that the 7th metal-oxide-semiconductor Q7 and the 9th metal-oxide-semiconductor Q9 are connected, so that the 5th Metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 conductings, by adjusting 3rd resistor R3 and the tenth resistance R10 can make the first metal-oxide-semiconductor Q1 and Second metal-oxide-semiconductor Q2 is suitable by the end of the time interval between the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 conductings, to ensure two-way electricity Source makes the voltage fluctuation on the feeder ear VBUS in tolerance interval while not short cut with each other, to not cause master control The erroneous judgement of GPIO modules 3.
For the detection voltage end VCDT, since the tenth metal-oxide-semiconductor Q10 ends quickly, and second control Output end VBUS_EN2 acquiescence output low levels so that the 11st metal-oxide-semiconductor Q11 cut-offs, so that usb interface module 2 is defeated Enter to hold the voltage of VBUS_IN can be added on detection voltage end VCDT, the 9th metal-oxide-semiconductor Q9 turn-on times are than the tenth metal-oxide-semiconductor Q10 Deadline is slightly late, within the time that the tenth metal-oxide-semiconductor Q10 has been switched off and this section that the 9th metal-oxide-semiconductor Q9 is not yet connected is very short, by In the presence of the 5th diode D5 and the 6th diode D6, the detection voltage end VCDT is the input terminal from DC interface modules 1 The high person of voltage is selected between DC_IN and the input terminal VBUS_IN of usb interface module 2, after the 9th metal-oxide-semiconductor Q9 conductings, the inspection The voltage that voltage end VCDT only reflects the input terminal VBUS_IN of usb interface module 2 is surveyed, in this way, due to third capacitance C3's Pressure stabilization function so that detected on voltage end VCDT without apparent voltage fluctuation described in whole process, master control GPIO modules 3 are not It will be considered that and changed in USB port, usb communication is continued, and practical charging path is also switched to the input of usb interface module 2 Hold VBUS_IN, and the detection voltage end VCDT reflections be effective charging paths usb interface module 2 input terminal VBUS_IN Voltage.
S4, when the state that USB data line and DC charging adapters are inserted into, during usb communication carries out, charging path connects for DC The input terminal DC_IN of mouth mold block 1, at this point, if extracting USB data line, usb communication terminates, in this case, USB interface mould The voltage of the input terminal VBUS_IN of block 2 and its output to the second control signal VBUSIN_DET of master control GPIO modules 3 point Pressure is lower by height, and circuit state does not have other variations, still maintains DC charged states, and the detection voltage end VCDT reflects DC The voltage of the input terminal DC_IN of interface module 1.Master control GPIO modules 3 pass through the second control signal VBUSIN_DET inspections Voltage this signal that is lower for measuring the input terminal VBUS_IN of usb interface module 2 recognizes that USB data line has been pulled out.
S5, when the state that USB data line and DC charging adapters are all not inserted into, when first DC charging adapters being inserted into, The voltage of the input terminal DC_IN of DC interface modules 1 is got higher by low, is exported since the first control output end VBUS_EN1 gives tacit consent to Low level, so the 4th metal-oxide-semiconductor Q4 cut-offs, the 4th resistance R4 and the 5th resistance R5 are divided so that third metal-oxide-semiconductor Q3, the 8th MOS The conducting of pipe Q8 and the tenth metal-oxide-semiconductor Q10 conductings, third metal-oxide-semiconductor Q3 makes the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 conductings, DC connect The voltage of the input terminal DC_IN of mouth mold block 1 is added to the power supply of master control GPIO modules 3 by the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 VBUS is held, since the 8th metal-oxide-semiconductor Q8 is connected so that the 7th metal-oxide-semiconductor Q7 ends, so that the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 ends, and prevents the voltage of the feeder ear VBUS of master control GPIO modules 3 from moving back on usb interface module 2；And due to the 8th MOS Pipe Q8 is connected so that the 9th metal-oxide-semiconductor Q9 ends, so that the voltage of the input terminal DC_IN of DC interface modules 1 passes through the 12nd The inspection of master control GPIO modules 3 is added to after resistance R12, thirteenth resistor R13, the 5th diode D5 and eleventh resistor R11 partial pressures Survey voltage end VCDT, and since the tenth metal-oxide-semiconductor Q10 is connected so that the input terminal VBUS_IN of usb interface module 2 is to master control The influence of the detection voltage end VCDT of GPIO modules 3 is cut off, and detection voltage end VCDT only reflects the input terminal of DC interface modules 1 The voltage of DC_IN, detection voltage end VCDT triggering master control GPIO modules 3 start USB correlated processes, because of DC charging adapters Only plus feeder ear voltage of VBUS and be not responding to the agreement on the D+/D- signal wires of USB, so master control GPIO modules 3 identification be slotting Enter DC charging adapters and enters DC charged states.
S6, when DC charging adapters are already inserted into, and circuit has been in DC charged states, at this point, DC interface modules 1 is defeated Enter to hold the voltage of DC_IN to be exported to the first control signal DCIN_DET's of master control GPIO modules 3 by the 16th resistance R16 Partial pressure is height, and the partial pressure that usb interface module 2 is output to the second control signal VBUSIN_DET of master control GPIO modules 3 is It is low.It is inserted into USB data line, the voltage of the input terminal VBUS_IN of usb interface module 2 is got higher by low, and usb interface module 2 is defeated at this time Go out the partial pressure to the second control signal VBUSIN_DET of master control GPIO modules 3 to be high, master control GPIO modules 3 receive second Charging current thresholding is turned down after the high level of control signal VBUSIN_DET, avoids the input terminal from usb interface module 2 High current is sucked on VBUS_IN, master control GPIO modules 3 control the first control output end VBUS_EN1 output high level conductings later 4th metal-oxide-semiconductor Q4, so that third metal-oxide-semiconductor Q3, the 8th metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 cut-offs, third metal-oxide-semiconductor Q3's cuts Only so that the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 cut-offs, the cut-off of the 8th metal-oxide-semiconductor Q8 make the 7th metal-oxide-semiconductor Q7 and the 9th MOS Pipe Q9 conductings, the 7th metal-oxide-semiconductor Q7 is connected so that the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 are connected, so that master control GPIO modules For 3 feeder ear VBUS by the input terminal VBUS_IN drivings of usb interface module 2, the 9th metal-oxide-semiconductor Q9, which is connected, makes DC interface modules 1 The voltage of input terminal DC_IN cannot be transferred to detection voltage end VCDT.
At the same time, master control GPIO modules 3 control the second control output end VBUS_EN2 output high level conducting the 11st Metal-oxide-semiconductor Q11, so that the voltage of the input terminal VBUS_IN of usb interface module 2 cannot be transmitted to the detection voltage Holding VCDT, detection voltage end VCDT to be in low level state makes master control GPIO modules 3 think that USB port is in and be not inserted into state, Then the inside of master control GPIO modules 3 and the relevant states of USB will automatically reset, and master control GPIO modules 3 are again described in secondary control Two control output end VBUS_EN2 outputs low level makes the 11st metal-oxide-semiconductor Q11 cut-offs, due to the tenth metal-oxide-semiconductor Q10 and the 11st Metal-oxide-semiconductor Q11 is cut-off state, and the voltage of the input terminal VBUS_IN of usb interface module 2 is added to detection voltage end VCDT, Triggering master control GPIO modules 3 are inserted into correlated process by this automatically into USB, in this process the feeder ear of master control GPIO modules 3 For VBUS by the input terminal VBUS_IN drivings of usb interface module 2, the VCDT reflections of detection voltage end are the defeated of usb interface module 2 The case where entering to hold the voltage of VBUS_IN, USB is inserted separately into this and S1 is completely the same.
USB is inserted into after the completion of correlated process, and master control GPIO modules 3 control the first control output end VBUS_EN1 again Export low level so that the 4th metal-oxide-semiconductor Q4 cut-offs, so that third metal-oxide-semiconductor Q3, the 8th metal-oxide-semiconductor Q8 and the tenth metal-oxide-semiconductor Q10 Conducting, so that the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 are connected and the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 cut-offs so that The feeder ear VBUS of master control GPIO modules 3 changes is driven into DC charged states by the input terminal DC_IN of DC interface modules 1.
In the specific implementation, it can make the 5th metal-oxide-semiconductor Q5 by adjusting the resistance value of 3rd resistor R3 and the tenth resistance R10 And the 6th metal-oxide-semiconductor Q6 it is suitable by the end of the time interval between the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 conductings, to ensure DC Interface module 1 and usb interface module 2 this two-way power supply make the feeder ear of master control GPIO modules 3 while not being shorted with each other The fluctuation generated on VBUS is in tolerance interval, to not cause the erroneous judgement of master control GPIO modules 3.
And since the conducting of the 8th metal-oxide-semiconductor Q8 makes the 9th metal-oxide-semiconductor Q9 cut-offs, so that the input of DC interface modules 1 The voltage of end DC_IN can be added on the detection voltage end VCDT of master control GPIO modules 3, wherein the conducting of the tenth metal-oxide-semiconductor Q10 Cut-off than the 9th metal-oxide-semiconductor Q9 is slightly late, the 9th metal-oxide-semiconductor Q9 has been switched off and this section that the tenth metal-oxide-semiconductor Q10 is not yet connected is very short Time in, due to the effect of the 5th diode D5 and the 6th diode D6, the detection voltage end VCDT of master control GPIO modules 3 from The high person of voltage is selected in both the input terminal DC_IN of DC interface modules 1 and the input terminal VBUS_IN of usb interface module 2, and is worked as After tenth metal-oxide-semiconductor Q10 conductings, the voltage of the input terminal VBUS_IN of usb interface module 2 cannot be added to master control GPIO modules 3 The detection voltage end VCDT of detection voltage end VCDT, master control GPIO module 3 only reflect the input terminal DC_IN of DC interface modules 1 Voltage, the voltage detected described in such whole process on voltage end VCDT obviously do not fluctuate, master control GPIO modules 3 It not will be considered that and changed on usb interface module 2, usb communication is continued, and practical charging circuit has been switched to DC interface moulds The input terminal DC_IN of block 1, and the detection voltage end VCDT reflections be effective charging paths DC interface modules 1 input terminal The voltage of DC_IN enters DC charged states at this time.
The above is only the preferred embodiment of the present invention, and it does not limit the scope of the patent of the present invention, Equivalent structure or equivalent flow shift made by using the description of the utility model and the drawings, is directly or indirectly transported Used in other related technical areas, it is equally included in the patent within the scope of the utility model.

Claims (10)

1. a kind of circuit for realizing DC charging and USB port communication function, including DC interface modules, usb interface module, the DC connect Mouth mold block and usb interface module are connected to rechargeable battery by master control GPIO modules, it is characterised in that：Further include for selecting Select the DC-USB charging selecting modules and the communication identification module of usb communication for identification of DC chargings or USB chargings, the DC The input terminal DC_IN of the interface module and input terminal VBUS_IN of usb interface module is connected to DC-USB charging selecting modules The output end of input terminal, the DC-USB chargings selecting module is connected to the feeder ear VBUS of master control GPIO modules；The DC connects The input terminal DC_IN of the mouth mold block and input terminal VBUS_IN of usb interface module is connected to the input terminal of communication identification module, The output end of the communication identification module is connected to the detection voltage end VCDT of master control GPIO modules, and the usb interface module is also It is respectively connected to master control GPIO modules including data anode D+ and data negative terminal D-, the data anode D+ and data negative terminal D- Signal anode USB_D+ and signal negative terminal USB_D-.
2. the circuit according to claim 1 for realizing DC charging and USB port communication function, it is characterised in that：The DC- The USB selecting modules that charge include that the first counnter attack fills circuit module and the second counnter attack and fills circuit module, the DC interface modules it is defeated Enter to hold DC_IN to fill feeder ear VBUS, the USB that circuit module is connected to the master control GPIO modules by first counnter attack The input terminal VBUS_IN of interface module fills the power supply that circuit module is connected to the master control GPIO modules by second counnter attack Hold VBUS.
3. the circuit according to claim 2 for realizing DC charging and USB port communication function, it is characterised in that：Described first Counnter attack fill circuit module include the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3 and the 4th metal-oxide-semiconductor Q4, described first The drain electrode of metal-oxide-semiconductor Q1 is connected to the input terminal DC_IN of the DC interface modules, and the source electrode of the first metal-oxide-semiconductor Q1 is connected to institute The source electrode of the second metal-oxide-semiconductor Q2 is stated, the drain electrode of the second metal-oxide-semiconductor Q2 is connected to the feeder ear VBUS of the master control GPIO modules, The grid of the grid short circuit of the grid and the second metal-oxide-semiconductor Q2 of the first metal-oxide-semiconductor Q1, the first metal-oxide-semiconductor Q1 is connected to first The source electrode of the anode of diode D1, the first metal-oxide-semiconductor Q1 is connected to the cathode of the first diode D1, the first diode D1 The grid for being parallel with first resistor R1, the first metal-oxide-semiconductor Q1 is also connected to the leakage of third metal-oxide-semiconductor Q3 by second resistance R2 Pole, the source electrode ground connection of the third metal-oxide-semiconductor Q3, the grid of the third metal-oxide-semiconductor Q3 are connected to the 4th MOS by 3rd resistor R3 The drain electrode of pipe Q4, the source electrode ground connection of the 4th metal-oxide-semiconductor Q4, the grid of the 4th metal-oxide-semiconductor Q4 are connected to the master control GPIO First control output end VBUS_EN1 of module, the drain electrode of the 4th metal-oxide-semiconductor Q4 are also connected to DC by the 4th resistance R4 and connect The drain electrode of the input terminal DC_IN, the 4th metal-oxide-semiconductor Q4 of mouth mold block also pass through the 5th resistance R5 ground connection, the third metal-oxide-semiconductor Q3 Grid also by the first capacitance C1 ground connection, the second diode D2 of the 3rd resistor R3 parallel connections, the second diode D2's Anode is connected to the grid of third metal-oxide-semiconductor Q3, and the cathode of the second diode D2 is connected to the drain electrode of the 4th metal-oxide-semiconductor Q4.
4. the circuit according to claim 3 for realizing DC charging and USB port communication function, it is characterised in that：Described second Counnter attack fill circuit module include the 5th metal-oxide-semiconductor Q5, the 6th metal-oxide-semiconductor Q6, the 7th metal-oxide-semiconductor Q7 and the 8th metal-oxide-semiconductor Q8, the described 5th The drain electrode of metal-oxide-semiconductor Q5 is connected to the input terminal VBUS_IN of the usb interface module, the source electrode and the 6th of the 5th metal-oxide-semiconductor Q5 The source shorted of metal-oxide-semiconductor Q6, the drain electrode of the 6th metal-oxide-semiconductor Q6 are connected to the feeder ear VBUS of master control GPIO modules, and described The grid short circuit of the grid and the 6th metal-oxide-semiconductor Q6 of five metal-oxide-semiconductor Q5, the grid connection third diode D3 of the 5th metal-oxide-semiconductor Q5 Anode, the cathode of the third diode D3 is connected to the source electrode of the 5th metal-oxide-semiconductor Q5, the third diode D3 parallel connections the 6th The source electrode of resistance R6, the 5th metal-oxide-semiconductor Q5 also pass through the 7th resistance R7 and the 8th resistance R8 ground connection, the 5th metal-oxide-semiconductor Q5 Grid the drain electrode of the 7th metal-oxide-semiconductor Q7 is also connected to by the 9th resistance R9, the source electrode ground connection of the 7th metal-oxide-semiconductor Q7 is described The grid of 7th metal-oxide-semiconductor Q7 connects the drain electrode of the 8th metal-oxide-semiconductor Q8, and the grid of the 7th metal-oxide-semiconductor Q7 is additionally coupled to the 7th electricity It hinders on the circuit between R7 and the 8th resistance R8, the source electrode of the 8th metal-oxide-semiconductor Q8 is grounded, the grid of the 8th metal-oxide-semiconductor Q8 It is connected on the circuit between the 4th resistance R4 and the 5th resistance R5 by the tenth resistance R10, the grid of the 8th metal-oxide-semiconductor Q8 Also by the second capacitance C2 ground connection, the cathode of the tenth resistance R10 parallel connections the 4th diode D4, the 4th diode D4 connect It is connected to the grid of the 8th metal-oxide-semiconductor Q8, the anode of the 4th diode D4 is connected to the 4th resistance R4 and the 5th resistance R5 Between circuit on.
5. the circuit according to claim 4 for realizing DC charging and USB port communication function, it is characterised in that：The communication Identification module includes D/C voltage tracking circuit module and USB voltage tracking circuit modules, the input terminal DC_ of the DC interface modules IN tracks the detection voltage end VCDT that circuit module is connected to master control GPIO modules, the USB interface mould by the D/C voltage The input terminal VBUS_IN of block is connected to the detection voltage end of master control GPIO modules by the USB voltage tracking circuits module VCDT, the detection voltage end VCDT are grounded by eleventh resistor R11.
6. the circuit according to claim 5 for realizing DC charging and USB port communication function, it is characterised in that：The DC electricity Pressure tracking circuit module includes the 9th metal-oxide-semiconductor Q9, twelfth resistor R12, thirteenth resistor R13 and the 5th diode D5, described The drain electrode of 9th metal-oxide-semiconductor Q9 is connected to the input terminal DC_IN of DC interface modules, the 9th metal-oxide-semiconductor by twelfth resistor R12 The drain electrode of Q9 is also connected to the anode of the 5th diode D5 by thirteenth resistor R13, and the cathode of the 5th diode D5 connects It is connected to the source electrode ground connection of detection the voltage end VCDT, the 9th metal-oxide-semiconductor Q9 of master control GPIO modules, the 9th metal-oxide-semiconductor Q9's Grid is connected on the circuit between the 7th resistance R7 and the 8th resistance R8.
7. the circuit according to claim 6 for realizing DC charging and USB port communication function, it is characterised in that：The USB electricity Pressure tracking circuit module includes the tenth metal-oxide-semiconductor Q10, the 11st metal-oxide-semiconductor Q11, the 14th resistance R14, the 15th resistance R15 and the The drain electrode of six diode D6, the tenth metal-oxide-semiconductor Q10 is connected to the input of usb interface module by the 14th resistance R14 VBUS_IN, the drain electrode of the tenth metal-oxide-semiconductor Q10 is held also to be connected to the 6th diode D6 by the 15th resistance R15 Anode, the cathode of the 6th diode D6 is connected to the detection voltage end VCDT of master control GPIO modules, the tenth metal-oxide-semiconductor The grid of Q10 is connected to the grid of the third metal-oxide-semiconductor Q3, and the drain electrode of the tenth metal-oxide-semiconductor Q10 is additionally coupled to the described 11st The drain electrode of metal-oxide-semiconductor Q11, the source electrode ground connection of the 11st metal-oxide-semiconductor Q11, the grid of the 11st metal-oxide-semiconductor Q11 are connected to institute State the second control output end VBUS_EN2 of master control GPIO modules.
8. the circuit according to claim 7 for realizing DC charging and USB port communication function, it is characterised in that：The master control The detection voltage end VCDT of GPIO modules is also grounded by third capacitance C3.
9. the circuit according to claim 8 for realizing DC charging and USB port communication function, it is characterised in that：The DC connects Mouth mold block includes DC connectors U1, the 16th resistance R16 and the 17th resistance R17, and the DC connectors U1 includes G1 pins, G2 Pin, G3 pins, G4 pins and DC+ pins, the G1 pins, G2 pins, G3 pins and G4 pins are grounded, the DC+ Pin is the input terminal DC_IN of the DC interface modules, and the DC+ pins are connected to the drain electrode of the first metal-oxide-semiconductor Q1, described DC+ pins are also connected to the first control signal DCIN_DET of the master control GPIO modules by the 16th resistance R16, described First control signal DCIN_DET also passes through the 17th resistance R17 ground connection.
10. the circuit according to claim 9 for realizing DC charging and USB port communication function, it is characterised in that：The USB Interface module includes USB connector U2, the 18th resistance R18, the 19th resistance R19, and the USB connector U2 includes VBUS pipes Foot, D- pins, D+ pins, ID pins, GND pins, H6 pins, H7 pins, H8 pins and H9 pins, the H6 pins, H7 pipes Foot, H8 pins, H9 pins and GND pins are grounded, and the VBUS pins are connected to the drain electrode of the 5th metal-oxide-semiconductor Q5, described VBUS pins are also connected to the second control signal VBUSIN_DET of the master control GPIO modules by the 18th resistance R18, The second control signal VBUSIN_DET is grounded by the 19th resistance R19, and the D- pins are the data minus D-, the D- pins is held to be connected to the signal negative terminal USB_D- of master control GPIO modules, the D+ pins are the data anode D+, The D+ pins are connected to the signal anode USB_D+ of master control GPIO modules, and the ID pins are connected to setting for master control GPIO modules Standby identification end IDDIG.
CN201721917600.XU 2017-12-29 2017-12-29 Realize the circuit of DC charging and USB port communication function Active CN207663327U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110943520A (en) * 2018-09-21 2020-03-31 南京翊宁智能科技有限公司 Charging path management circuit of equipment and equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110943520A (en) * 2018-09-21 2020-03-31 南京翊宁智能科技有限公司 Charging path management circuit of equipment and equipment

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