CN109726059B

CN109726059B - Server test system

Info

Publication number: CN109726059B
Application number: CN201910002188.6A
Authority: CN
Inventors: 张志安
Original assignee: Inspur Power Commercial Systems Co Ltd
Current assignee: Inspur Power Commercial Systems Co Ltd
Priority date: 2019-01-02
Filing date: 2019-01-02
Publication date: 2022-07-29
Anticipated expiration: 2039-01-02
Also published as: CN109726059A

Abstract

The invention discloses a server test system which comprises a test board detection circuit, a signal gating module arranged on a mainboard of a server, a USB test interface, a control module, a first power interface, a second power interface and a power conversion module which are arranged on the test board. The control module in the server test system can interact with the CPLD on the server mainboard to acquire the actual running state (started or shut down) of the server from the CPLD on the mainboard, so that whether the server can be normally started or shut down is judged, and the test result is accurate. Moreover, the server test system is simple in structure, low in cost, small and portable. In addition, the server test system of this application need not outside special cable, only need when the test occupy the server a USB interface can, it is comparatively convenient to operate.

Description

Server test system

Technical Field

The invention relates to the technical field of server testing, in particular to a server testing system.

Background

Currently, the server is a core device of the computing device, and the quality of the server is concerned by users. In order to ensure the quality of the server, a plurality of tests, such as a DC cycle test, an AC cycle test, a pressure test, a function test, a performance test, and the like, are performed on the server. The DC cycle test and the AC cycle test are used for testing whether the startup and shutdown of the server are normal or not.

For the AC cycle test, the test is usually performed using a programmable AC Source, or a self-made fatigue machine. The testing principle of the programmable AC Source is as follows: the method comprises the steps of presetting the startup time and the shutdown time of a server on a programmable AC Source by pre-judging the startup time and the shutdown time of the server, and controlling the communication state of a power supply circuit of the server according to the preset startup time and the preset shutdown time so as to carry out AC cycle test. However, the programmable AC Source does not interact with the server, so that the actual operating state of the server cannot be known, if the actual operating state of the server does not coincide with the predetermined time, the test item cannot be completed well, and the problem occurring in the actual operating process of the server cannot be tested.

The testing principle of the self-made fatigue machine is as follows: and the power supply of the server mainboard is externally connected and converted into a fixed interface for detecting the fatigue machine. The fatigue machine correspondingly determines that the server is started or shut down by detecting the power-on state (the power-on of the mainboard power supply is only one link of the server and is combined with certain starting pre-judging time) or the power-off state of the mainboard power supply, so that the AC Cycle test of the server is completed once. However, if the boot prediction time of the server is inaccurate, the test items cannot be completed well. In addition, the cost of the programmable AC Source and the self-made fatigue machine is higher, the occupied space is larger, the equipment is heavier, and the transportation is not facilitated.

Therefore, how to provide a solution to the above technical problems is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a server test system which has the advantages of more accurate test result, simple structure, lower cost, small size and portability; in addition, an external special cable is not needed, and only one USB interface of the server is occupied during testing, so that the operation is convenient.

In order to solve the technical problems, the invention provides a server testing system which comprises a testing board detection circuit, a signal gating module arranged on a mainboard of a server, a USB testing interface arranged on the testing board, a control module, a first power interface used for accessing commercial power during testing, a second power interface used for connecting with the power interface on the mainboard during testing and a power conversion module used for converting the commercial power into a power supply required by the control module; wherein:

the first signal transmission end of the signal gating module is connected with a south bridge platform control unit PCH on the mainboard, the second signal transmission end is connected with a complex programmable logic device CPLD on the mainboard, the third signal transmission end is connected with a signal transmission end of a USB interface on the mainboard, and the control end is connected with the mainboard CPLD; the signal transmission end of the USB test interface is connected with the control module, the USB test interface is correspondingly connected with the USB interface during testing, the first power supply interface is respectively connected with the second power supply interface and the input end of the power supply conversion module, and the output end of the power supply conversion module is connected with the power supply end of the control module;

The test board detection circuit is used for generating a test board connection signal when detecting that the USB test interface is connected with the USB interface; the main board CPLD is used for controlling the signal gating module to communicate with signal transmission between the main board CPLD and the control module after receiving the test board connection signal, so that the control module sends a power-on instruction or a power-off instruction to the main board CPLD and correspondingly obtains power-on information or power-off information of the server from the main board CPLD.

Preferably, the test board detection circuit comprises a first resistor, a second resistor, a first controllable switch, a second controllable switch and a third resistor; wherein:

the first end of the first resistor is connected with the first end of the second resistor, the common end of the first resistor is connected with the output end of a first direct current power supply, the second end of the first resistor is respectively connected with the mainboard CPLD and the control end of the first controllable switch, the first end of the first controllable switch is connected with the second end of the second resistor, the second end of the first controllable switch is respectively connected with the first end of the second controllable switch, the grounding end of the USB interface and the mainboard CPLD, the control end of the second controllable switch is connected with the mainboard CPLD, the second end of the second controllable switch is grounded, the first end of the third resistor is connected with the grounding end of the USB test interface, and the second end of the third resistor is grounded; the first controllable switch is switched on when a high level is input to the control end, and is switched off when a low level is input to the control end;

The main board CPLD is specifically configured to determine that the USB test interface is connected to the USB interface, and control the first controllable switch to be turned off and the second controllable switch to be turned on, and control the signal gating module to communicate signal transmission between the main board CPLD and the control module when it is detected that the voltage value of the ground terminal of the USB interface is within a preset voltage range.

Preferably, the server test system further includes a third controllable switch, a fourth resistor, a fifth resistor, and a power switch, which are disposed on the test board; wherein:

the first end of the third controllable switch is connected with the live wire end of the first power interface, the second end of the third controllable switch is connected with the live wire end of the second power interface, the control end of the third controllable switch is respectively connected with the first end of the fourth resistor and the control module, the first end of the fourth controllable switch is connected with the zero wire end of the first power interface, the second end of the fourth controllable switch is connected with the zero wire end of the second power interface, the control end of the fourth controllable switch is respectively connected with the first end of the fifth resistor and the control module, the second end of the fourth resistor is connected with the second end of the fifth resistor, the common end of the fourth controllable switch is grounded, and the control module is also connected with the power switch; the third controllable switch and the fourth controllable switch are both switched on when a high level is input to the control end and switched off when a low level is input to the control end;

The control module is further configured to control the third controllable switch and the fourth controllable switch to be turned on when the power switch is pressed.

Preferably, the control module comprises:

the starting module is used for sending a starting instruction to the mainboard CPLD after the signal transmission between the mainboard CPLD and the control module is communicated, so that the mainboard CPLD can be started and enter an operating system after receiving the starting instruction, and the started information is transmitted to the starting module when entering the operating system;

the shutdown module is used for starting timing when the startup information is received from the startup module, and sending a shutdown instruction to the mainboard CPLD when the timing time reaches a preset first time, so that the mainboard CPLD is shut down after receiving the shutdown instruction, and the shutdown information is transmitted to the shutdown module;

the AC cut-off module is used for starting timing when the shutdown information is received from the shutdown module during AC Cycle testing, and controlling the third controllable switch and the fourth controllable switch to be switched off after the timing time reaches a preset second time;

and the AC power-on module is used for starting timing from the moment when the third controllable switch and the fourth controllable switch are both switched off when an AC Cycle test is carried out, and controlling the third controllable switch and the fourth controllable switch to be both switched on after the timing time reaches a preset third time.

Preferably, the server test system further includes a mode presetting module for presetting a test mode, and a time presetting module for presetting the preset first time, the preset second time, and the preset third time; the test modes comprise a DC Cycle mode and an AC Cycle mode; wherein:

the mode preset module and the time preset module are both connected with the control module;

the control module is also used for executing the starting module and the shutdown module according to the set time Cycle of the time presetting module during testing if the testing mode is a DC Cycle mode until the Cycle times reach the preset testing times; and if the test mode is an AC Cycle mode, circularly executing the starting module, the shutdown module, the AC cut-off module and the AC power-on module according to the set time of the time presetting module during testing until the Cycle times reach the preset test times.

Preferably, the mode presetting module and the time presetting module are both multi-way dial switches.

Preferably, the server test system further includes a sixth resistor and a seventh resistor disposed on the test board; wherein:

A first end of the sixth resistor is connected with a power supply end of the USB test interface, a second end of the sixth resistor is respectively connected with the control module and a first end of the seventh resistor, a second end of the seventh resistor is grounded, and the power supply end of the USB interface is connected with an output end of a second direct-current power supply;

the control module is further configured to determine that the USB test interface is connected to the USB interface when the voltage value of the first end of the seventh resistor is detected to be within a preset voltage value range.

Preferably, the control module is a CPLD disposed on the test board.

Preferably, when the main board CPLD and the test board CPLD are connected through I ² When the bus C performs signal transmission, the server test system further comprises a first pull-up resistor and a second pull-up resistor which are arranged on the mainboard, and a third pull-up resistor and a fourth pull-up resistor which are arranged on the test board; two mainboard signal wires are connected between the second signal transmission end of the signal gating module and the mainboard CPLD, and two test board signal wires are connected between the signal transmission end of the USB test interface and the test board CPLD; wherein:

the first end of the first pull-up resistor is connected to one of the mainboard signal lines, the first end of the second pull-up resistor is connected to the other mainboard signal line, the second end of the first pull-up resistor is connected with the second end of the second pull-up resistor, and the common end of the first pull-up resistor is connected with a third direct current power supply;

The first end of the third pull-up resistor is connected to one of the test board signal lines, the first end of the fourth pull-up resistor is connected to the other test board signal line, the second end of the third pull-up resistor is connected with the second end of the fourth pull-up resistor, and the common end of the third pull-up resistor is connected with the power supply end of the test board CPLD.

Preferably, the server test system further includes a first capacitor and a second capacitor disposed on the test board; wherein:

the first end of the first capacitor is connected with the first end of the second capacitor, and the common end of the first capacitor is connected with the power supply end of the test board CPLD; and the second end of the first capacitor is connected with the second end of the second capacitor, and the common end of the first capacitor is grounded.

The invention provides a server test system, which comprises a test board detection circuit, a signal gating module arranged on a mainboard of a server, a USB test interface, a control module, a first power interface, a second power interface and a power conversion module, wherein the USB test interface, the control module, the first power interface, the second power interface and the power conversion module are arranged on the test board; wherein: the test board detection circuit is used for generating a test board connection signal when detecting that the USB test interface is connected with the USB interface; the main board CPLD is used for controlling the signal gating module to communicate signal transmission between the main board CPLD and the control module after receiving the connecting signal of the test board, so that the control module can send a starting instruction or a shutdown instruction to the main board CPLD and correspondingly acquire the started information or the shutdown information of the server from the main board CPLD.

Therefore, the control module in the server test system can interact with the CPLD on the server mainboard to acquire the actual running state (started or shut down) of the server from the CPLD on the mainboard, so that whether the server can be normally started or shut down is judged, and the test result is accurate. Moreover, the server test system is simple in structure, low in cost, small and portable. In addition, the server test system of this application need not outside special cable, only need when the test occupy the server a USB interface can, it is comparatively convenient to operate.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a server test system according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a server motherboard according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a test board according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating a connection between the server motherboard shown in fig. 2 and the test board shown in fig. 3 according to an embodiment of the present invention.

Detailed Description

The core of the invention is to provide a server test system, which has more accurate test result, simple structure, lower cost, small size and portability; in addition, an external special cable is not needed, and only one USB interface of the server is occupied during testing, so that the operation is convenient.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a server test system according to an embodiment of the present invention.

The server test system includes: the system comprises a test board detection circuit 1, a signal gating module 2 arranged on a mainboard of a server, a USB test interface 3, a control module 4, a first power interface PS1 used for accessing commercial power during testing, a second power interface PS2 used for connecting with a power interface on the mainboard during testing, and a power conversion module 7 used for converting the commercial power into a power supply required by the control module 4, wherein the USB test interface 3 and the control module 4 are arranged on the test board; wherein:

The first signal transmission end of the signal gating module 2 is connected with a south bridge PCH on the mainboard, the second signal transmission end is connected with a CPLD on the mainboard, the third signal transmission end is connected with a signal transmission end of a USB interface on the mainboard, and the control end is connected with the CPLD on the mainboard; the signal transmission end of the USB test interface 3 is connected with the control module 4, the USB test interface 3 is correspondingly connected with the USB interface during testing, the first power interface PS1 is respectively connected with the second power interface PS2 and the input end of the power conversion module 7, and the output end of the power conversion module 7 is connected with the power supply end of the control module 4;

the test board detection circuit 1 is used for generating a test board connection signal when detecting that the USB test interface 3 is connected with the USB interface; the main board CPLD is used for controlling the signal gating module 2 to communicate with signal transmission between the main board CPLD and the control module 4 after receiving the test board connection signal, so that the control module 4 sends a power-on instruction or a power-off instruction to the main board CPLD and correspondingly obtains power-on information or power-off information of the server from the main board CPLD.

Specifically, the server test system of the present application includes a test board detection circuit 1, a signal gating module 2, a USB test interface 3, a control module 4, a first power interface PS1, a second power interface PS2, and a power conversion module 7, and its working principle is:

In the prior art, a CPLD (Complex Programmable Logic Device), a south bridge PCH (Platform control unit), a power interface, and a USB (Universal Serial Bus) interface are disposed on a motherboard of a server. When the motherboard USB interface is connected to a general USB device (such as a USB disk), the motherboard south bridge PCH can interact with the general USB device through the motherboard USB interface.

The mainboard CPLD can control the startup and shutdown of the server, so that the test board for testing whether the startup and shutdown of the server are normal or not is arranged outside the server, and the test board is enabled to interact with the mainboard CPLD through the mainboard USB interface, so that whether the server can be normally started up or shut down is accurately judged.

In detail, considering that the USB interface of the motherboard may be connected to the general USB device, and may also be connected to the test board, the test board detection circuit 1 is provided in the present application to detect whether the USB interface of the motherboard is specifically connected to the general USB device or the test board. The test board detection circuit 1 generates a test board connection signal when detecting that the test board is connected with the USB interface of the mainboard; and generating a common equipment connection signal when detecting that the common USB equipment is connected with the USB interface of the mainboard.

In order to realize that when the mainboard USB interface is connected with the test board, the test board realizes interaction with the mainboard CPLD through the mainboard USB interface; when the mainboard USB interface is connected with ordinary USB equipment, the test board realizes interaction with the mainboard south bridge PCH through the mainboard USB interface, and the signal gating module 2 (selecting one signal from two signals for transmission) is additionally arranged on the mainboard of the server.

The first signal transmission end of the signal gating module 2 is connected with the motherboard south bridge PCH, the second signal transmission end is connected with the motherboard CPLD, and the third signal transmission end is connected with the motherboard USB interface. The signal gating module 2 is controlled by the mainboard CPLD, and when the mainboard CPLD controls the line communication between the first signal transmission end and the third signal transmission end of the signal gating module 2, the mainboard south bridge PCH can interact with equipment inserted by the mainboard USB interface through the mainboard USB interface; when the main board CPLD controls the line communication between the second signal transmission end and the third signal transmission end of the signal gating module 2, the main board CPLD can interact with the device into which the main board USB interface is inserted through the main board USB interface.

Therefore, after receiving the connection signal of the test board, the main board CPLD controls the signal gating module 2 to communicate with the line between the second signal transmission end and the third signal transmission end thereof, so as to realize the interaction between the test board and the main board CPLD; after receiving the connection signal of the ordinary device, the control signal gating module 2 connects the line between the first signal transmission end and the third signal transmission end thereof, so as to realize the interaction between the motherboard south bridge PCH and the ordinary USB device.

Further, for the test board, the test board is provided with a USB test interface 3, a control module 4, a first power interface PS1, a second power interface PS2, and a power conversion module 7. Specifically, in terms of power supply, the first power interface PS1 of the test board supplies the commercial power input during the test to the power conversion module 7, and the power conversion module 7 supplies power to the control module 4; on the other hand, the power is supplied to the second power interface PS2, and the power is supplied to the motherboard by the second power interface PS2, so that the motherboard of the server is powered on. In the interaction aspect, the USB test interface 3 is connected to the control module 4, and the USB test interface 3 is connected to the motherboard USB interface through a USB cable during testing, so as to realize interaction between the control module 4 and the motherboard CPLD.

It can be seen that, when the test server is ready to be turned on and off, the USB test interface 3 of the test board is connected to the USB interface of the motherboard, and the first power interface PS1 of the test board is connected to the power interface of the motherboard. After the interface connection is completed, the commercial power is input into the first power interface PS1 of the test board, so that both the test board and the server motherboard are powered on.

It should be noted that, if the present application sets in advance that the motherboard CPLD immediately starts the boot program after being powered on, the control module 4 can detect the boot state of the server through the motherboard CPLD after the server motherboard is powered on, and send a shutdown instruction to the motherboard CPLD after detecting that the server is powered on, so that the motherboard CPLD controls the server to shutdown. The main board CPLD immediately returns the shutdown information of the server to the control module 4 after the server is shutdown. The control module 4 sends a power-on instruction to the motherboard CPLD after receiving the power-off information of the server, so that the motherboard CPLD controls the server to be powered on. The main board CPLD immediately returns the boot information of the server to the control module 4 after the server is booted and enters the operating system, thereby testing whether the server is normally booted or not.

If the present application sets in advance that the boot program is started only after the motherboard CPLD is powered on and receives the boot instruction (the following embodiment is based on this situation), the control module 4 sends the boot instruction to the motherboard CPLD after the server motherboard is powered on, so that the motherboard CPLD controls the server to boot. The main board CPLD immediately returns the boot information of the server to the control module 4 after the server is booted and enters the operating system. The control module 4 sends a shutdown instruction after receiving the startup information of the server, so that the mainboard CPLD controls the server to shutdown. After the server is powered off, the CPLD of the mainboard can immediately return the power-off information of the server to the control module 4, so that whether the power-on and the power-off of the server are normal or not is tested.

Referring to fig. 2, fig. 3, and fig. 4, fig. 2 is a schematic structural diagram of a server motherboard according to an embodiment of the present invention, fig. 3 is a schematic structural diagram of a test board according to an embodiment of the present invention, and fig. 4 is a schematic connection diagram between the server motherboard shown in fig. 2 and the test board shown in fig. 3 according to an embodiment of the present invention. The server testing system is based on the embodiment as follows:

as a preferred embodiment, the testing board detecting circuit 1 includes a first resistor R1, a second resistor R2, a first controllable switch Q1, a second controllable switch Q2 and a third resistor R3; wherein:

A first end of a first resistor R1 is connected with a first end of a second resistor R2, a common end of the first resistor R3878 is connected with an output end of a first direct-current power supply, a second end of the first resistor R1 is connected with a control end of a mainboard CPLD and a first controllable switch Q1 respectively, a first end of a first controllable switch Q1 is connected with a second end of a second resistor R2, a second end of the first controllable switch Q1 is connected with a first end of a second controllable switch Q2, a ground end of a USB interface and the mainboard CPLD respectively, a control end of the second controllable switch Q2 is connected with the mainboard CPLD, a second end of the second controllable switch Q2 is grounded, a first end of a third resistor R3 is connected with a ground end of the USB test interface 3, and a second end of a third resistor R3 is grounded; the first controllable switch Q1 is turned on when the control terminal inputs a high level, and turned off when the control terminal inputs a low level;

the main board CPLD is specifically configured to determine that the USB test interface 3 is connected to the USB interface, and control the first controllable switch Q1 to be turned off, the second controllable switch Q2 to be turned on, and the signal gating module 2 to communicate signal transmission between the main board CPLD and the control module 4 when the voltage value of the ground terminal of the USB interface is detected to be within the preset voltage range.

It should be noted that the preset of the present application is set in advance, and only needs to be set once, and the reset is not needed unless the modification is needed according to the actual situation.

Specifically, the test board detection circuit 1 of the present application includes a first resistor R1, a second resistor R2, a first controllable switch Q1, a second controllable switch Q2, and a third resistor R3, which is disposed on the server motherboard, and its operating principle is:

under the condition that the first controllable switch Q1 is not controlled by the main board CPLD, a voltage signal (high level) divided by the first resistor R1 from the first dc power supply (voltage value may be 3.3V) is input to the control end of the first controllable switch Q1. Since the first controllable switch Q1 is turned on when the control terminal is inputted with a high level and turned off when the control terminal is inputted with a low level, the first controllable switch Q1 is turned on without the control of the main board CPLD.

It is known that a USB interface of a general USB device has four transmission channels, the transmission channels distributed on both sides are respectively connected to a power supply and a ground, and the transmission channel distributed in the middle is used for signal transmission. When the USB interface of the general USB device is connected to the USB interface of the motherboard (the first controllable switch Q1 is in a conducting state), the ground terminal of the USB interface of the motherboard is grounded, i.e. the voltage is close to 0.

In order to distinguish the ordinary USB device from the test board, the ground terminal of the USB test interface 3 on the test board of the present application is connected to the third resistor R3, so when the USB test interface 3 is correspondingly connected to the USB interface of the motherboard (the first controllable switch Q1 is in a conducting state), the voltage at the ground terminal of the USB interface of the motherboard is the voltage value V at the two ends of the third resistor R3 _R3 。

Based on this, the voltage value V of the third resistor R3 is used in advance _R3 For reference, a voltage range is set, e.g. V _R3 －V _r ～V _R3 +V _r Wherein V is _r Is the allowed error voltage value. The main board CPLD can detect the main board after being electrifiedAnd if the voltage value of the grounding end of the board USB interface is detected to be within the set voltage range, which indicates that the USB interface of the mainboard is connected with the USB test interface 3 of the test board at the moment, the control signal gating module 2 is communicated with the signal transmission between the CPLD of the mainboard and the USB interface of the mainboard.

Or, if the main board CPLD detects that the voltage value of the ground terminal of the main board USB interface is not within the set voltage range (close to 0), which indicates that the main board USB interface is connected to the USB interface of the ordinary USB device at this time, the control signal gating module 2 may communicate the signal transmission between the main board south bridge PCH and the main board USB interface.

Since the ground terminal of the motherboard USB interface needs to be grounded during signal transmission, the first controllable switch Q1 can be controlled to be turned off and the second controllable switch Q2 can be controlled to be turned on after the connection of the motherboard USB interface is determined, so that the ground terminal of the motherboard USB interface is grounded.

As a preferred embodiment, the server test system further includes a third controllable switch K1, a fourth controllable switch K2, a fourth resistor R4, a fifth resistor R5, and a power switch SW disposed on the test board; wherein:

A first end of a third controllable switch K1 is connected with a live wire end of the first power interface PS1, a second end of the third controllable switch K1 is connected with a live wire end of the second power interface PS2, a control end of the third controllable switch K1 is connected with a first end of a fourth resistor R4 and the control module 4, a first end of the fourth controllable switch K2 is connected with a neutral wire end of the first power interface PS1, a second end of the fourth controllable switch K2 is connected with a neutral wire end of the second power interface PS2, a control end of the fourth controllable switch K2 is connected with a first end of a fifth resistor R5 and the control module 4, a second end of the fourth resistor R4 is connected with a second end of the fifth resistor R5, a common end of the fourth controllable switch is grounded, and the control module 4 is further connected with the power switch SW; the third controllable switch K1 and the fourth controllable switch K2 are both switched on when the control end inputs a high level and switched off when the control end inputs a low level;

the control module 4 is further adapted to control the third controllable switch K1 and the fourth controllable switch K2 to be conductive when the power switch SW is pressed.

Further, the server test system of the present application further includes a third controllable switch K1, a fourth controllable switch K2, a fourth resistor R4, a fifth resistor R5 and a power switch SW on the test board, and the operating principle is as follows:

For safety, when the first power interface PS1 of the test board is connected to the commercial power, the test board does not immediately connect to the second power interface PS2, but first converts the commercial power connected to the first power interface PS1 to the power conversion module 7 and then supplies power to the control module 4. After the control module 4 is powered on, the power switch SW is pressed, and when the control module 4 detects that the power switch SW is pressed (for example, when the power switch SW is pressed, the level of a port where the power switch SW is connected with the control module 4 changes), the control module 4 controls the third controllable switch K1 and the fourth controllable switch K2 to be turned on, so that the first power interface PS1 is connected with the second power interface PS 2.

The third controllable switch K1 and the fourth controllable switch K2 are both turned on when the control terminal inputs a high level and turned off when the control terminal inputs a low level. Therefore, in the case where the third controllable switch K1 and the fourth controllable switch K2 are not controlled by the control module 4, the control terminals thereof are grounded and are in the off state.

As a preferred embodiment, the control module 4 comprises:

the starting module is used for sending a starting instruction to the mainboard CPLD after the signal transmission between the mainboard CPLD and the control module 4 is communicated, so that the mainboard CPLD can be started and enter the operating system after receiving the starting instruction, and the started information is transmitted to the starting module when entering the operating system;

the AC cut-off module is used for starting timing when the shutdown information is received from the shutdown module during AC Cycle testing, and controlling the third controllable switch K1 and the fourth controllable switch K2 to be switched off after the timing time reaches a preset second time;

and the AC power-on module is used for starting timing when the third controllable switch K1 and the fourth controllable switch K2 are both switched off during AC Cycle testing, and controlling the third controllable switch K1 and the fourth controllable switch K2 to be switched on after the timing time reaches a preset third time.

Specifically, the procedure of the AC Cycle test of the present application: 1) the control module 4 sends the starting instruction to the main board CPLD. And the main board CPLD is started up and enters an operating system after receiving the starting-up instruction. The main board CPLD immediately notifies the control module 4 of the boot information after entering the operating system. 2) After receiving the power-on information, the control module 4 waits for a preset first time T1 to return a power-off instruction to the motherboard CPLD. The main board CPLD normally shuts down the system after receiving the shutdown instruction, and transmits shutdown information to the control module 4. 3) After receiving the shutdown information, the control module 4 waits for a preset second time T2 to control the third controllable switch K1 and the fourth controllable switch K2 to be turned off, and then cuts off the ac power supply. 4) After the third controllable switch K1 and the fourth controllable switch K2 are both turned off, the control module 4 waits for a preset third time T3 and then controls the third controllable switch K1 and the fourth controllable switch K2 to be turned on, and the server motherboard is powered on again. Generally, the AC Cycle test tests the startup and shutdown of the server for multiple times, so the method circularly executes the step 1) → the step 4) until the Cycle reaches the preset test frequency.

Compared with the AC Cycle test, the DC Cycle test does not cut off the AC power supply, and only executes the step 1) and the step 2) circularly until the Cycle times reach the preset test times. Therefore, the AC Cycle test program is written into the control module 4, so that the control module 4 has the capability of realizing the AC Cycle test and the capability of realizing the DC Cycle test.

As a preferred embodiment, the server testing system further includes a mode presetting module for presetting a testing mode, and a time presetting module for presetting a preset first time, a preset second time, and a preset third time; the test mode comprises a DC Cycle mode and an AC Cycle mode; wherein:

the mode presetting module and the time presetting module are both connected with the control module 4;

the control module 4 is further configured to execute the startup module and the shutdown module according to a set time Cycle of the time presetting module during testing if the test mode is the DC Cycle mode until the Cycle number reaches the preset test number; if the test mode is the AC Cycle mode, the starting module, the shutdown module, the AC cutting-off module and the AC electrifying module are executed according to the set time Cycle of the time presetting module during testing until the Cycle times reach the preset test times.

Further, in order to enable the server test system to achieve both DC Cycle testing and AC Cycle testing, the test board is additionally provided with the mode presetting module. The mode presetting module sets a test mode (DC Cycle mode or AC Cycle mode) of the server test system in advance and informs the control module 4. The control module 4 executes the corresponding test program according to the test mode set by the mode presetting module.

In addition, for the first time T1, the second time T2 and the third time T3 in the test program, the application adds a time presetting module on the test board. Before the test, the time presetting module sets specific values of the first time T1, the second time T2 and the third time T3 in advance and informs the control module 4. The control module 4 executes the test program according to the preset time of the time presetting module during the test.

As a preferred embodiment, the mode presetting module and the time presetting module are both embodied as a multi-way dial switch.

Specifically, the mode presetting module and the time presetting module of the present application may both be multi-way dial switches, for example, as shown in fig. 2, the mode presetting module is a three-way dial switch SW1, and the time presetting module is an eight-way dial switch SW 2. For the three-way toggle switch SW1, the following Table 1 may be set:

TABLE 1

A first switch SW1_1 of the three-way dial switch SW1 is turned to an ON position, which indicates that the test mode of the server test system is set to be an AC Cycle mode; the first switch SW1_1 is turned OFF, which indicates that the test mode of the server test system is set to DC Cycle mode. The second switch SW1_2 is turned to the OFF position, and the third switch SW1_3 is turned to the ON position, which indicates that the eight-way dial switch SW2 performs time setting ON the first time T1 at the moment; the second switch SW1_2 is turned to the ON position, and the third switch SW1_3 is turned to the OFF position, which indicates that the eight-way dial switch SW2 performs time setting ON the second time T2 at the moment; the second switch SW1_2 is turned to the ON position, and the third switch SW1_3 is turned to the ON position, which indicates that the eight-way dial switch SW2 performs time setting ON the third time T3 at the moment; the second switch SW1_2 is turned OFF and the third switch SW1_3 is turned OFF, which indicates that the time set by the eight-way dial switch SW2 is not used, and the specific values of the first time T1, the second time T2 and the third time T3 stored in advance in the control module 4 are used.

For the eight-way toggle switch SW2, it may be set to: the first switch SW2_1 is turned to the ON position and the remaining switches are turned to the OFF position, representing 1 sec; the second switch SW2_2 is turned to the ON position and the remaining switches are turned to the OFF position for 2 sec; the third switch SW2_3 is turned to the ON position and the remaining switches are turned to the OFF position, representing 4 sec; the fourth switch SW2_4 is turned to the ON position and the remaining switches are turned to the OFF position for 8 sec; the fifth switch SW2_5 is opened to the ON position and the remaining switches are opened to the OFF position for 16 sec; the sixth switch SW2_6 is turned to the ON position and the remaining switches are turned to the OFF position for 32 sec; the seventh switch SW2_7 is turned to the ON position and the remaining switches are turned to the OFF position, representing 64 sec; the eighth switch SW2_8 is opened to the ON position and the remaining switches are opened to the OFF position for 128 sec.

In a preferred embodiment, the server test system further includes a sixth resistor R6 and a seventh resistor R7 disposed on the test board; wherein:

a first end of the sixth resistor R6 is connected with a power supply end of the USB test interface 3, a second end of the sixth resistor R6 is respectively connected with the control module 4 and a first end of the seventh resistor R7, a second end of the seventh resistor R7 is grounded, and the power supply end of the USB interface is connected with an output end of the second direct-current power supply;

the control module 4 is further configured to determine that the USB test interface 3 is connected to the USB interface when the voltage value of the first end of the seventh resistor R7 is detected to be within the preset voltage value range.

Further, this application still adds sixth resistance R6 and seventh resistance R7 on the testing board, and its theory of operation is:

since the power terminal of the USB interface of the motherboard is connected to the second dc power source (e.g. 5V), the present application connects two resistors (the sixth resistor R6 and the seventh resistor R7) in series at the power terminal of the USB test interface 3 of the test board. If the motherboard USB interface is not connected to the USB test interface 3, the voltage between the sixth resistor R6 and the seventh resistor R7 is about 0; if the main board USB interface is connected to the USB test interface 3, the sixth resistor R6 and the seventh resistor R7 divide the voltage output by the second dc power supply, and the voltage between the sixth resistor R6 and the seventh resistor R7 is the voltage V at the two ends of the seventh resistor R7 _R7 。

Based on this, the present application can use the voltage value V at the two ends of the seventh resistor R7 in advance _R7 For reference, a range of voltage values, e.g. V, is set _R7 －V _r ～V _R7 +V _r Wherein V is _r Is the allowed error voltage value. The control module 4 will detect the voltage value between the sixth resistor R6 and the seventh resistor R7 after being powered on, and if the voltage value between the sixth resistor R6 and the seventh resistor R7 is detected to be within the set voltage value range, it indicates that the USB test interface 3 of the test board is connected to the USB interface of the motherboard at this time; if the voltage value between the two is detected not to be within the set voltage value range (close to 0), it indicates that the USB test interface 3 of the test board is not connected to the USB interface of the motherboard.

As a preferred embodiment, the control module 4 is embodied as a CPLD provided on a test board.

Specifically, the control module 4 of the present application can be selected from, but not limited to, a CPLD, and the present application is not particularly limited thereto.

As a preferred embodiment, when the main board CPLD and the test board CPLD are connected through I ² When the C bus transmits signals, the server test system further includes a first pull-up resistor R11 and a second pull-up resistor R12 disposed on the motherboard, and a third pull-up resistor R13 and a fourth pull-up resistor R12 disposed on the test boardR14; two mainboard signal wires are connected between the second signal transmission end of the signal gating module 2 and the mainboard CPLD, and two test board signal wires are connected between the signal transmission end of the USB test interface 3 and the test board CPLD; wherein:

A first end of the first pull-up resistor R11 is connected to one of the mainboard signal lines, a first end of the second pull-up resistor R12 is connected to the other mainboard signal line, a second end of the first pull-up resistor R11 is connected with a second end of the second pull-up resistor R12, and a common end of the first pull-up resistor R11 is connected with a third direct-current power supply;

the first end of the third pull-up resistor R13 is connected to one of the test board signal lines, the first end of the fourth pull-up resistor R14 is connected to the other test board signal line, the second end of the third pull-up resistor R13 is connected to the second end of the fourth pull-up resistor R14, and the common end of the third pull-up resistor R13 is connected to the power supply end of the test board CPLD.

Specifically, when the main board CPLD and the test board CPLD are connected through I ² When the C bus carries out signal transmission, I ² A pull-up resistor is additionally arranged on the C bus to pull up the I ² And C, the voltage signal on the bus enables normal signal transmission between the main board CPLD and the test board CPLD.

In a preferred embodiment, the server test system further includes a first capacitor C1 and a second capacitor C2 disposed on the test board; wherein:

the first end of the first capacitor C1 is connected with the first end of the second capacitor C2, and the common end of the first capacitor C1 is connected with the power supply end of the test board CPLD; the second terminal of the first capacitor C1 is connected to the second terminal of the second capacitor C2, and the common terminal thereof is grounded.

Furthermore, considering that there is an interference signal in the power signal input by the power source end of the test board CPLD, the first capacitor C1 and the second capacitor C2 are added to the power source end of the test board CPLD in the present application to filter the interference signal existing in the power signal input by the test board CPLD, thereby stabilizing the power input of the test board CPLD.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A server test system is characterized by comprising a test board detection circuit, a signal gating module arranged on a mainboard of a server, a USB test interface, a control module, a first power interface, a second power interface and a power conversion module, wherein the USB test interface, the control module, the first power interface, the second power interface and the power conversion module are arranged on the test board; wherein:

The test board detection circuit is used for generating a test board connection signal when detecting that the USB test interface is connected with the USB interface; the main board CPLD is used for controlling the signal gating module to communicate with signal transmission between the main board CPLD and the control module after receiving the test board connection signal, so that the control module sends a power-on instruction or a power-off instruction to the main board CPLD and correspondingly obtains power-on information or power-off information of the server from the main board CPLD;

the test board detection circuit comprises a first resistor, a second resistor, a first controllable switch, a second controllable switch and a third resistor; wherein:

2. The server test system of claim 1, further comprising a third controllable switch, a fourth resistor, a fifth resistor, and a power switch disposed on the test board; wherein:

3. The server test system of claim 2, wherein the control module comprises:

4. The server test system according to claim 3, wherein the server test system further comprises a mode presetting module for presetting a test mode and a time presetting module for presetting the preset first time, the preset second time, and the preset third time; the test modes comprise a DC Cycle mode and an AC Cycle mode; wherein:

5. The server test system of claim 4, wherein the mode preset module and the time preset module are both embodied as multi-tap switches.

6. The server test system of claim 1, wherein the server test system further comprises a sixth resistor and a seventh resistor disposed on the test board; wherein:

7. The server test system according to any one of claims 1 to 6, wherein the control module is in particular a CPLD provided on the test board.

8. The server test system according to claim 7, wherein when the motherboard CPLD and the test board CPLD pass through I therebetween ² When the bus C performs signal transmission, the server test system further comprises a first pull-up resistor and a second pull-up resistor which are arranged on the mainboard, and a third pull-up resistor and a fourth pull-up resistor which are arranged on the test board; two mainboard signal wires are connected between the second signal transmission end of the signal gating module and the mainboard CPLD, and two test board signal wires are connected between the signal transmission end of the USB test interface and the test board CPLD; wherein:

9. The server test system of claim 7, further comprising a first capacitor and a second capacitor disposed on the test board; wherein: