CN207489897U - N-shaped crystalline silicon double-side cell - Google Patents
N-shaped crystalline silicon double-side cell Download PDFInfo
- Publication number
- CN207489897U CN207489897U CN201720599465.2U CN201720599465U CN207489897U CN 207489897 U CN207489897 U CN 207489897U CN 201720599465 U CN201720599465 U CN 201720599465U CN 207489897 U CN207489897 U CN 207489897U
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon
- type
- crystal silicon
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Abstract
The utility model provides a kind of N-shaped crystalline silicon double-side cell, including substrate, p+ type crystal silicon layers, p++ type silicon films, front passivated reflection reducing penetrates layer, front metal electrode layer, n++ type silicon films, passivating back antireflection layer and back metal gate line electrode, substrate uses N-shaped crystal silicon chip, the front of N-shaped crystal silicon chip is equipped with the p+ type crystal silicon layers that doping is formed, local setting p++ type silicon films on p+ type crystal silicon layers, p+ types crystal silicon layer and the common front surface deposition front passivated reflection reducing of p++ type silicon films penetrate layer, front metal electrode layer penetrates front passivated reflection reducing and penetrates layer and contacted with p++ type silicon films, the back side setting n++ type silicon films of N-shaped crystal silicon chip, n++ type silicon fimls layer surface deposits passivating back antireflection layer；It is compound that the utility model avoids contact zone caused by metal electrode is in direct contact p+ type doped layers；And reduce the contact resistance between metal grid lines electrode and p+ type doped layers.
Description
Technical field
The utility model is related to a kind of N-shaped crystalline silicon double-side cells.
Background technology
With the development of photovoltaic market, demand of the people to high-efficiency crystal silicon cell is more and more urgent.With respect to p-type crystalline silicon
For battery, since N-shaped crystalline silicon is insensitive to metal impurities, has restrain oneself performance well in other words, therefore its minority carrier
Son has larger diffusion length；In addition, N-shaped crystalline silicon uses phosphorus doping, there is no the shapes because leading to B-O complexing bodies during illumination
Into because the light-induced degradation phenomenon in p-type crystal silicon cell may be not present.Therefore, N-shaped crystal silicon cell is increasingly becoming numerous researchs
The object of mechanism and photovoltaic enterprises pay attention.
In all N-shaped crystal silicon cells, n-PERT double-side cells（Passivated Emitter Rear Totally-
Diffused, i.e. emitter junction are passivated full back surface field diffusion battery）, it is device architecture and preparation process and existing p as shown in Figure 1
Type crystal silicon battery is immediate, is easiest to the Technology Ways used by most enterprises.In general, n-PERT double-side cells are with N-shaped
Monocrystalline silicon piece is substrate, such as N-shaped crystal silicon layer 01 in Fig. 1, boron, phosphorus atoms is adulterated respectively in its front and back, as formed P in Fig. 1
+ type crystal silicon layer 02, n+ types crystal silicon layer 05, formed p+n emitters and nn+ the back of the body electric field, then using deielectric-coating passivation just, the back of the body
Face is respectively formed passivated reflection reducing and penetrates film layer 03, dielectric passivation film layer 06, finally penetrates deielectric-coating and forms front and back contact electrode,
That is metal grid lines electrode 04, metal back electrode 07 in Fig. 1.
At present, the screen-printed metallization of p-type side is a technical barrier being not yet fully solved.In general, in order to reduce
Ag starches the contact resistance with p-type layer, need to mix a certain amount of Al, and the presence of Al can cause p type emitter contact zone compound electric
Stream increases.There are three types of the methods for solving the problems, such as this at present：One is using deeper junction depth, while keep relatively small surface
Concentration, to prevent passivation region recombination current from increasing；The second is using selective emitter, it is compound to shield contact zone；The third is
Electroplating technology is used to reduce contact zone area and compound.Although above method can alleviate front face area to a certain extent
It is compound, but since metal electrode and p+ types emitter surface are still in direct contact, metal ion is easy to penetrate into boron diffusion
Area（P+ type crystal silicon layers）, destroy the p+n knots below electrode, so as to cause the compound increase in p+n interfaces, battery open circuit voltage and
Transfer efficiency reduces；The body resistivity of slurry can be made to increase, and cell series resistance is caused to increase in addition, introducing Al in Ag slurries
Greatly, fill factor reduces.
M.K. Stodolny et al. is in document【N-Type Polysilicon Passivating Contacts for
Industrial Bifacial N-PERT Cells, EUPVSEC-2016】It proposes using ultra-thin silica and n++ type polysilicons
Thin film passivation n-PERT cell backsides, although contact zone caused by when reducing back metal is compound, its front still uses
Screen printing electrode is in direct contact p+ type emitter region, there are larger contact zone is compound, the open-circuit voltage and transfer efficiency of battery
It is difficult to be obviously improved.
Utility model content
The purpose of this utility model is to provide a kind of N-shaped crystalline silicon double-side cell, overcomes metal electrode in n-PERT batteries
The problem of compound increase in contact zone caused by being in direct contact p+ type emitter surfaces and open-circuit voltage reduce.
The technical solution of the utility model is：
A kind of N-shaped crystalline silicon double-side cell, including substrate, p+ types crystal silicon layer, p++ types silicon film, front passivated reflection reducing
Layer, front metal electrode layer, n++ types silicon film, passivating back antireflection layer and back metal gate line electrode are penetrated, substrate uses n
Type crystal silicon chip, the front of N-shaped crystal silicon chip are equipped with the p+ type crystal silicon layers that doping is formed, local setting on p+ type crystal silicon layers
P++ type silicon films, i.e. p++ types silicon film are only set below front metal electrode layer, p+ types crystal silicon layer and p++ type silicon films
Common front surface deposition front passivated reflection reducing penetrates layer, front metal electrode layer penetrate front passivated reflection reducing penetrate layer and with p++ type silicon
Film layer contacts, the back side setting n++ type silicon films of N-shaped crystal silicon chip, the deposition passivating back antireflective of n++ type silicon fimls layer surface
Layer, back metal electrode layer penetrate passivating back antireflection layer and are contacted with n++ type silicon films.
Further, N-shaped crystal silicon chip uses N-shaped monocrystalline silicon piece or N-shaped polysilicon chip, the resistivity of N-shaped crystal silicon chip
In 0.3 ~ 10 Ω cm, thickness in 50 ~ 500um.
Further, the thickness of p+ types crystal silicon layer is in 0.2 ~ 2um, and square resistance is in 20 ~ 200 Ω/.
Further, n++ types silicon film using the non-crystalline silicon of phosphorus doping, amorphous silica, microcrystal silicon, crystallite silica or
Polysilicon, n++ type silicon fiml layer thickness is in 10nm ~ 10um.
Further, subsidiary one layer of ultra-thin silicon oxide layer, ultra-thin silica between n++ types silicon film and N-shaped crystal silicon layer
The thickness of layer is in 1 ~ 3nm.
Further, p++ types silicon film is boron doped non-crystalline silicon, amorphous silica, microcrystal silicon, crystallite silica or more
Crystal silicon, p++ type silicon fiml layer thickness is in 10nm ~ 10um.
Further, subsidiary one layer of ultra-thin silicon oxide layer between p++ types silicon film and p+ type crystal silicon layers, thickness 1 ~
3nm。
Further, front passivated reflection reducing penetrates layer including at least a-SiNx, a-SiOx, a-SiCx, a-SiCxNy, a-
The combination of any one or more in SiNxOy, a-AlOx, front passivated reflection reducing penetrate layer thickness in 60 ~ 150nm.
Further, passivating back antireflection layer includes at least a-SiNx, a-SiOx, a-SiCx, a-SiCxNy, a-
The combination of any one or more in SiNxOy, a-AlOx, passivating back antireflection layer thickness is in 60 ~ 150nm.
Further, front metal electrode layer is appointing in Ag, Ni/Ag, Ni/Cu, Ni/Cu/Sn or Ni/Cu/Ag electrode
Meaning is a kind of, and back metal gate line electrode is any one in Ag, Ni/Ag, Ni/Cu, Ni/Cu/Sn or Ni/Cu/Ag electrode.
The beneficial effects of the utility model are：This kind of N-shaped crystalline silicon double-side cell, compared with prior art, has following
Advantage：First, p++ types silicon film is introduced between front metal electrode and p+ type doped layers and forms passivation contact layer, is effectively avoided
Contact zone caused by metal electrode is in direct contact p+ type doped layers is compound；Secondly, it reduces metal grid lines electrode and is mixed with p+ types
Contact resistance between diamicton；It, can be in addition, front electrode slurry can directly use existing p-type cell front side silver slurry
Reduce the line resistance of metal grid lines electrode.
Description of the drawings
Fig. 1 is the structure diagram of existing n-PERT crystal-silicon solar cells；
In Fig. 1,01-n type crystal silicon layers；02- p+ type crystal silicon layers；03- passivated reflection reducings penetrate film layer；04- metal grid lines electricity
Pole；05- n+ type crystal silicon layers；06- dielectric passivation film layers；07- metal back electrodes.
Fig. 2 is the structure diagram of the utility model embodiment N-shaped crystalline silicon double-side cell；
In Fig. 2,1-n type crystal silicon chips；2-p+ type crystal silicon layers；3-n++ type silicon films；4-p++ type silicon films；5- fronts
Passivated reflection reducing penetrates layer；6- passivating back antireflection layers；7- front metal electrode layers；8- back metal electrode layers.
Specific embodiment
The preferred embodiment of the utility model is described in detail below in conjunction with the accompanying drawings.
Embodiment
A kind of N-shaped crystalline silicon double-side cell, such as Fig. 2, including substrate, p+ types crystal silicon layer 2, p++ types silicon film 4, front
Passivated reflection reducing penetrates layer 5, front metal electrode layer 7, n++ types silicon film 3, passivating back antireflection layer 6 and back metal grid line electricity
Pole 8, substrate use N-shaped crystal silicon chip 1, and the front of N-shaped crystal silicon chip 1 is equipped with the p+ types crystal silicon layer 2 that doping is formed, and p+ types are brilliant
Local setting p++ types silicon film 4 on body silicon layer 2, i.e. p++ types silicon film 4 are only set on 7 lower section of front metal electrode layer, and p+ types are brilliant
Body silicon layer 2 and the common front surface deposition front passivated reflection reducing of p++ types silicon film 4 penetrate layer 5, and front metal electrode layer 7 penetrates just
Face passivated reflection reducing is penetrated layer 5 and is contacted with p++ types silicon film 4, the back side setting n++ types silicon film 3 of N-shaped crystal silicon chip 1, n++ types
3 surface of silicon film deposition passivating back antireflection layer 6, back metal electrode layer 8 penetrates passivating back antireflection layer 6 and n++ types
Silicon film 3 contacts.
By above structure, first, p++ types silicon film 4 is introduced between front metal electrode layer 7 and p+ types crystal silicon layer 2
Passivation contact layer is formed, it is compound to avoid contact zone caused by front metal electrode layer 7 is in direct contact p+ types crystal silicon layer 2；p++
Type silicon film is used in 7 lower section of front metal electrode layer, i.e., local setting p++ types silicon film 4, can reduce on p+ types crystal silicon layer 2
It is compound below front metal electrode layer 7；If with all setting, since p++ types silicon film 4 can post the generation of front incident light
It is raw to absorb, reduce the short circuit current of battery.Secondly, the contact between front metal electrode layer 7 and p+ types crystal silicon layer 2 is reduced
Resistance.In addition, front metal electrode 7 can directly use existing p-type cell front side silver slurry, front metal electricity can be reduced
The line resistance of pole layer 7.
N-shaped crystal silicon chip 1 uses N-shaped monocrystalline silicon piece, and resistivity is in 2 Ω cm, and thickness is in 180um；The N-shaped crystal silicon layer
1 is mainly used for absorbing photon, generates photo-generated carrier.
2 thickness of p+ types crystal silicon layer is in 1um, and square resistance is in 60 Ω/；The p+ types crystal silicon layer 2 and N-shaped crystal silicon layer
1 forms homogeneity p+n emitters, for detaching photo-generated carrier.
N++ types silicon film 3 is the polysilicon of phosphorus doping, and thickness is in 150nm；N++ types silicon film 3 is attached to one layer and surpasses below
Thin silicon oxide layer, thickness is in 1.5nm.The n++ types silicon film 3 forms nn++ types back of the body electric field with N-shaped crystal silicon chip 1, can be blunt
Electrochemical cell back surface, reduction back surface is compound, while can form good ohm with N-shaped crystal silicon chip 1 and metallic back electrode layer 8
Contact.
P++ types silicon film 4 is boron doped polysilicon, and thickness is in 150nm；P++ types silicon film 4 and p+ type crystal silicon layers
Subsidiary one layer of ultra-thin silicon oxide layer between 2, thickness is in 1.5nm.The p++ types silicon film 4 forms p++p with p+ types crystal silicon layer 2
+ type front-surface field, can passivation cell p+ emitters contact zone, reduce contact zone surface recombination, while can be with p+ type crystal
Silicon layer 2 and front metal electrode 7 form good Ohmic contact.
Front passivated reflection reducing penetrates the composite film that layer 5 is formed for a-AlOx and a-SiNx, thickness respectively in 10nm and
60nm.The passivated reflection reducing, which penetrates layer 5, will be used for reducing reflection of the incident light in silicon chip surface, while form p+ types crystal silicon layer 2
Good surface passivation.
Passivating back antireflection layer 6 is a-SiNx, and thickness is in 80nm.The passivating back antireflection layer 6 will be used for reducing
Back surface incident light silicon chip surface reflection, while to nn++ types the back of the body electric field form good interface passivation.
Front metal electrode layer 7 is the Ag gate line electrodes that silk-screen printing is formed, and front metal electrode layer 7 is used for collecting photoproduction
Hole in carrier.Metallic back electrode layer 8 is the Ag gate line electrodes that silk-screen printing is formed, which is used for receiving
Collect the electronics in photo-generated carrier.
Claims (10)
1. a kind of N-shaped crystalline silicon double-side cell, it is characterised in that：Including substrate, p+ types crystal silicon layer, p++ types silicon film, front
Passivated reflection reducing penetrates layer, front metal electrode layer, n++ types silicon film, passivating back antireflection layer and back metal gate line electrode, lining
Bottom uses N-shaped crystal silicon chip, and the front of N-shaped crystal silicon chip is equipped with the p+ type crystal silicon layers that doping is formed, on p+ type crystal silicon layers
Local setting p++ type silicon films, i.e. p++ types silicon film are only set below front metal electrode layer, p+ types crystal silicon layer and p++ types
The common front surface deposition front passivated reflection reducing of silicon film penetrates layer, front metal electrode layer penetrate front passivated reflection reducing penetrate layer and with
P++ types silicon film contacts, the back side setting n++ type silicon films of N-shaped crystal silicon chip, n++ type silicon fimls layer surface deposition passivating back
Antireflection layer, back metal electrode layer penetrate passivating back antireflection layer and are contacted with n++ type silicon films.
2. N-shaped crystalline silicon double-side cell as described in claim 1, it is characterised in that：N-shaped crystal silicon chip uses N-shaped monocrystalline silicon
Piece or N-shaped polysilicon chip, the resistivity of N-shaped crystal silicon chip is in 0.3 ~ 10 Ω cm, thickness in 50 ~ 500um.
3. N-shaped crystalline silicon double-side cell as described in claim 1, it is characterised in that：The thickness of p+ type crystal silicon layers 0.2 ~
2um, square resistance is in 20 ~ 200 Ω/.
4. N-shaped crystalline silicon double-side cell as claimed in claim 3, it is characterised in that：N++ types silicon film is non-using phosphorus doping
Crystal silicon, amorphous silica, microcrystal silicon, crystallite silica or polysilicon, n++ type silicon fiml layer thickness is in 10nm ~ 10um.
5. N-shaped crystalline silicon double-side cell as claimed in claim 4, it is characterised in that：N++ types silicon film and N-shaped crystal silicon layer
Between subsidiary one layer of ultra-thin silicon oxide layer, the thickness of ultra-thin silicon oxide layer is in 1 ~ 3nm.
6. N-shaped crystalline silicon double-side cell as claimed in claim 5, it is characterised in that：P++ types silicon film is boron doped amorphous
Silicon, amorphous silica, microcrystal silicon, crystallite silica or polysilicon, p++ type silicon fiml layer thickness is in 10nm ~ 10um.
7. N-shaped crystalline silicon double-side cell as claimed in claim 6, it is characterised in that：P++ types silicon film and p+ type crystal silicon layers
Between subsidiary one layer of ultra-thin silicon oxide layer, thickness is in 1 ~ 3nm.
8. N-shaped crystalline silicon double-side cell as claimed in claim 7, it is characterised in that：Front passivated reflection reducing is penetrated layer and is included at least
The combination of any one or more in a-SiNx, a-SiOx, a-SiCx, a-SiCxNy, a-SiNxOy, a-AlOx, front are blunt
Change antireflection layer thickness in 60 ~ 150nm.
9. such as claim 1-8 any one of them N-shaped crystalline silicon double-side cells, it is characterised in that：Passivating back antireflection layer
Including at least the group of any one or more in a-SiNx, a-SiOx, a-SiCx, a-SiCxNy, a-SiNxOy, a-AlOx
It closes, passivating back antireflection layer thickness is in 60 ~ 150nm.
10. such as claim 1-8 any one of them N-shaped crystalline silicon double-side cells, it is characterised in that：Front metal electrode layer is
Any one in Ag, Ni/Ag, Ni/Cu, Ni/Cu/Sn or Ni/Cu/Ag electrode, back metal gate line electrode is Ag, Ni/Ag,
Any one in Ni/Cu, Ni/Cu/Sn or Ni/Cu/Ag electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720599465.2U CN207489897U (en) | 2017-05-26 | 2017-05-26 | N-shaped crystalline silicon double-side cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720599465.2U CN207489897U (en) | 2017-05-26 | 2017-05-26 | N-shaped crystalline silicon double-side cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207489897U true CN207489897U (en) | 2018-06-12 |
Family
ID=62484101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720599465.2U Active CN207489897U (en) | 2017-05-26 | 2017-05-26 | N-shaped crystalline silicon double-side cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207489897U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628049A (en) * | 2020-06-11 | 2020-09-04 | 常州时创能源股份有限公司 | Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof |
-
2017
- 2017-05-26 CN CN201720599465.2U patent/CN207489897U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628049A (en) * | 2020-06-11 | 2020-09-04 | 常州时创能源股份有限公司 | Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206907779U (en) | N-type crystal silicon double-side solar cell | |
| ES2926597T3 (en) | Photovoltaic module, solar cell and method for producing the solar cell | |
| US10084107B2 (en) | Transparent conducting oxide for photovoltaic devices | |
| CN109728103B (en) | Solar cell | |
| Glunz et al. | n-type silicon-enabling efficiencies> 20% in industrial production | |
| US20090255574A1 (en) | Solar cell fabricated by silicon liquid-phase deposition | |
| CN107369726B (en) | n-type crystalline silicon double-sided solar cell | |
| CN103413838B (en) | A kind of crystal-silicon solar cell and preparation method thereof | |
| US20100243042A1 (en) | High-efficiency photovoltaic cells | |
| CN103199143B (en) | The heterojunction solar battery device of N-type hydrogen-doped crystallized silicon passivated | |
| CN110828584A (en) | P-type local back surface field passivation double-sided solar cell and preparation process thereof | |
| CN107275432B (en) | Crystalline silicon solar cell and preparation method thereof | |
| CN112563348A (en) | Metallization method for passivation contact of tunneling oxide layer on back electrode of solar cell | |
| CN106449845B (en) | One kind is based on Si/TiOxThe two-sided crystal-silicon solar cell of hetero-junctions | |
| CN209199953U (en) | A kind of passivation solar battery of type metal electrode | |
| CN108615775B (en) | Interdigital back contact heterojunction monocrystalline silicon battery | |
| CN207489897U (en) | N-shaped crystalline silicon double-side cell | |
| CN207381411U (en) | The two-sided crystal silicon battery of p-type with polysilicon passivation tunnel composite junction | |
| CN209199966U (en) | A kind of low cost p-type all back-contact electrodes crystal silicon solar battery | |
| CN203760493U (en) | N-type crystalline silicon battery | |
| CN103730532A (en) | Hydrogen-doped crystallized silicon passivated heterojunction solar cell | |
| CN208507687U (en) | A kind of interdigital back contacts hetero-junctions monocrystalline silicon battery | |
| CN209981254U (en) | Crystalline silicon double-sided solar cell structure | |
| CN103227228A (en) | P-type silicon substrate heterojunction cell | |
| CN206271724U (en) | A kind of two-sided crystal-silicon solar cell based on Si/TiOx hetero-junctions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |