CN207124636U - Branch road convergent type board - Google Patents

Abstract

The utility model discloses a kind of branch road convergent type board, and it includes FPGA module, CPU module and power module.The FPGA module includes FPGA and the crystal oscillator, SDH phaselocked loops, the optical modules of STM 1 and the encryption chip that are connected respectively with FPGA；The CPU module communicates to connect with the FPGA module, the CPU module includes CPU, storage chip, Ethernet switching chip and ethernet channel selector, the storage chip and Ethernet switching chip are connected with the CPU respectively, and the ethernet channel selector is connected with the Ethernet switching chip；The power module is connected with the FPGA module and CPU module, is each assembly power supply in FPGA module and CPU module.The utility model is with the branch road convergent type boards of FPGA conceptual designs STM 1, the recoverable resources of product module is provided for developer and continue the flexibility of exploitation using FPGA and CPU programmable features, meanwhile relative to ASIC schemes, FPGA and CPU cost are greatly lowered.

Description

Branch road convergent type board

Technical field

It the utility model is related to MSAP optical transports field, and in particular to a kind of branch road convergent type board.

Background technology

MSAP is used for the access, convergence and transmission that Ethernet service and TDM business are realized on a unified platform, its Can provide Ethernet, PDH, E1, V.35, V.24 private line service and the Telecom-level network management such as.Intermediate layer is used as using MSAP equipment To connect SDH transmission networks and access network, while network upgrade is realized, the net for being effectively protected operator early stage again builds throwing Money.MSAP concentration, uniform characteristics also make it have that access capacity is big, distribution is concentrated, occupied little space, manages and facilitates, builds If many advantages, such as, access low with O＆M cost, simple dilatation, MSAP has turned into the main flow equipment of each operator in recent years One of, paid attention to by manufacturer in industry.

STM-1 branch road convergent type boards are applied MSAP is large-scale and the service card of medium size installations, undertake the basic network elements of TM Function, the convergence of subordinate MSAP equipment superior MSAP/MSTP equipment is realized, is one of most important branch an outpost of the tax office of MSAP equipment, STM-1 branch road convergent types board mainly builds circuit realiration by using special ASIC schemes at present, and ASIC schemes are mostly state Wai great factories provide, and cost is of a relatively high, and flexibility is poor, and scheme advantage is smaller.

Utility model content

The purpose of this utility model be to provide a kind of cost it is relatively low, can flexible expansion branch road convergent type board.

To achieve the above object, the utility model uses following technical scheme：

A kind of branch road convergent type board, including：

FPGA module, the FPGA module include FPGA and the crystal oscillator, SDH phaselocked loops, the STM-1 light that are connected respectively with FPGA Module and encryption chip；

CPU module, the CPU module communicate to connect with the FPGA module, and the CPU module includes CPU, storage core Piece, Ethernet switching chip and ethernet channel selector, the storage chip and Ethernet switching chip respectively with it is described CPU connections, the ethernet channel selector are connected with the Ethernet switching chip；

Power module, the power module are connected with the FPGA module and CPU module, are FPGA module and CPU module In each assembly power supply.

Further, the FPGA is Cyclone IV Series FPGAs.

Further, the response frequency of the crystal oscillator is 77.76Mhz.

Further, the SDH phaselocked loops are ZL30122 molded line card synchronizers.

Further, the encryption chip is DS28E01-100 chips.

Further, the CPU is MPC8309 processors.

Further, the storage chip includes Flash memory chip and SDRAM storage chips, and the Flash stores core Piece is M29W128GH70N6E chips, and the SDRAM storage chips are MT47H64M16HR-3IT chips.

Further, the Ethernet switching chip is IP175G chips.

Further, the ethernet channel selector is TS3L100 logic switches.

After adopting the above technical scheme, the utility model compared with background technology, has the following advantages that：

The utility model is with FPGA conceptual design STM-1 branch road convergent type boards, and FPGA and CPU programmable features is open Originator provides the recoverable resources of product module and continues the flexibility of exploitation, meanwhile, relative to ASIC schemes, FPGA with CPU cost is greatly lowered.

Brief description of the drawings

Fig. 1 is the utility model structure composition schematic block diagram；

Fig. 2 is application schematic diagram of the present utility model.

Embodiment

In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only explaining The utility model, it is not used to limit the utility model.

Embodiment

As shown in figure 1, the utility model discloses a kind of branch road convergent type board, including FPGA module, CPU module and electricity Source module.Wherein, the FPGA module includes FPGA and the crystal oscillator, SDH phaselocked loops, the STM-1 optical modules that are connected respectively with FPGA And encryption chip；The CPU module communicates to connect with the FPGA module, and the CPU module includes CPU, storage chip, ether Net exchange chip and ethernet channel selector, the storage chip and Ethernet switching chip are connected with the CPU respectively, The ethernet channel selector is connected with the Ethernet switching chip；The power module and the FPGA module and CPU Module is connected, and is each assembly power supply in FPGA module and CPU module.

It is one of main purpose of the present utility model due to reducing cost, it is contemplated that CPU is mainly used in coordinating fpga chip Agreement auxiliary operation and webmaster correlation function are completed, itself need not carry out the calculation process work of SDH agreements, therefore should not Too high performance is sought, from dominant frequency in more than 50Mhz, with enough pin numbers, the necessary hardware interface of support. The sophisticated functions for considering subsequently extend simultaneously is, it is necessary to make headspace to performance, and the utility model is using at MPC8309 The MPC8309VMADDCA in device is managed, it has 266Mhz core work frequencies, 16kB cachings, supports DDR2, SDRAM storage Device, peripheral interface are configured with 4 UART, 2 12C, 3 MII, 1 USB, 2 TDM, 1 SPI and 4 CAN, EBI Ethernet and TDM communication protocols are supported for Local Bus, CPU, it can meet the needs of multi-protocols control application, drop simultaneously The cost of low board.

To coordinate MPC8309 processors, the storage chip includes 16MByte Flash memory chip and 8MByte DDR2SDRAM storage chips, with operational objective program.Selected respectively in the present embodiment M29W128GH70N6E and As Flash memory chip and SDRAM storage chips, it is connected MT47H64M16HR-3IT by M II interfaces with CPU.

The Ethernet switching chip mainly provides the network management path based on Ethernet, for examining for Cost And Performance demand Amount, it needs 3 switching ports, it is only necessary to supports 2 layers of function of exchange, but requires that one of switching port provides MAC To facilitate connection CPU, exchange chip must support 10/100Base-T standards, be selected in the present embodiment interface (MII/RMII) IP175G chips.

As shown in Fig. 2 the application schematic diagram of branch road convergent type board, because it accesses the ether of MSAP apparatus back boards Network management passage needs to access mutually redundant two main control cards, and must be switched by the other control signal of even lower level, it is therefore desirable to The ethernet channel selector is set, realizes the controlled switching of Ethernet network management path.In the present embodiment, TS3L100 is selected Logic switch is as ethernet channel selector.TS3L100 is the Ethernet single-pole double-throw switch (SPDT) of 4 channel widebands, and it has height The features such as bandwidth (being not less than 350Mhz), low differential cross-talk (being less than -68dB), low-power consumption, zero time delay, Low ESR, special adaptation 10/100Base-T signals.

It is in the utility model that CPU module is individually designed into One function platelet in order to design convenient and module reuse.

The FPGA module is mainly used to realize communication protocol functions.FPGA is a kind of programmable application specific integrated circuit, Its appearance both compensate for the shortcomings that ASIC flexibility deficiencies, solve the problems, such as CPLD gate circuit negligible amounts again.This implementation According to the factor such as logic unit proximity and use habit, integrated cost in example, from Altera Cyclone IV series FPGA。

The FPGA needs outside offer clock.According to the requirement of SDH agreements, logic circuit needs 19.44Mhz clock Source, and keep certain precision, therefore in one 77.76Mhz of FPGA exterior arrangements crystal oscillator, pass through frequency dividing inside FPGA and produce 19.44Mhz clock source；Other frequency clocks needed for system can be handled to obtain by the digital phase-locked loop inside FPGA.

The SDH phaselocked loops are used to work to meet requirements of the SDH to clock accuracy into row clock frequency stabilization etc..The present embodiment In, the special phase-locked loop chips of SDH select SONET/SDH low jitters line card synchronizer ZL30122.The chip has following special Property：Meet Telcordia GR-253-CORE and the ITU-T G.813 requirement to telecommunication system clock；Its internal simulation locks phase Ring can provide the shake less than 3ps for 622.08Mhz output clock, comply fully with GR-253-CORE OC-12 and G.813STM-16 rank and the clock demand of the interface less than their speed；Can provide it is programmable from 8kHz to 77.76Mhz synchronizing clock signals；Built-in quality phaselocked loop disclosure satisfy that all clock characteristics needed for SONET/SDH, and Automatic clock module selection (tri- kinds of states of locked, free-run, holdover) can be carried out；Support that 3 timing reference inputs are defeated Enter the frame synchronizing signal output with 3 pulse matchings；The optionally a variety of frame pulse signals of output pulse width, polarity and frequency；Can be with Configure the phase difference between the time delay for being input to output and output；Flexible input refers to testing mechanism, according to frequency and phase The irregular situation of position, automatic conversion timing reference input；Support the JTAG of IEEE 1149.1.

Considered in terms of port density, flexibility and productibility, STM-1 optical modules described in the present embodiment selects SFP The optical module of encapsulation.

To realize privacy requirements, it is necessary to which operation is encrypted in embedded program and FPGA programs to being placed in FLASH. To avoid cryptographic operation from reducing the operational efficiency of system, the utility model is carried out efficient, reliable and easy by encryption chip Encryption.Encryption chip in the utility model uses DS28E01-100 chips, it by single contact 1-Wire bus communications, Integrated 1024 EEPROM, EEPROM points are page 4, can provide write-protect pattern, and wherein can will be set to EPROM emulation by one page Pattern；The integrated 512 challenge response safety certification engine for meeting ISO/IEC 10118-3 SHAs (SHA-1)； The buffer of 64 is provided in addition and carries out write operation；Every DS28E01-100 also has unique 64 ROM registration codes.

The FPGA is except the device of realizing as SDH agreements, or the hinge of whole hardware, as shown in Fig. 2 its with Between CPU by Local Bus buses connect, with the differential signal of STM-1 optical modules and MSAP apparatus back boards by its from The LVDS interface connection that body carries.

It is described above, the only preferable embodiment of the utility model, but the scope of protection of the utility model is not This is confined to, any one skilled in the art can readily occur in the technical scope that the utility model discloses Change or replacement, should all cover within the scope of protection of the utility model.Therefore, the scope of protection of the utility model should It is defined by scope of the claims.

Claims (9)

1. A kind of 1. branch road convergent type board, it is characterised in that including：

   FPGA module, the FPGA module include FPGA and the crystal oscillator, SDH phaselocked loops, the STM-1 optical modules that are connected respectively with FPGA And encryption chip；

   CPU module, the CPU module and the FPGA module communicate to connect, the CPU module include CPU, storage chip, with Too net exchange chip and ethernet channel selector, the storage chip and Ethernet switching chip connect with the CPU respectively Connect, the ethernet channel selector is connected with the Ethernet switching chip；

   Power module, the power module are connected with the FPGA module and CPU module, are in FPGA module and CPU module Each assembly power supply.
2. A kind of 2. branch road convergent type board as claimed in claim 1, it is characterised in that：The FPGA is Cyclone IV series FPGA。
3. A kind of 3. branch road convergent type board as claimed in claim 1, it is characterised in that：The response frequency of the crystal oscillator is 77.76Mhz。
4. A kind of 4. branch road convergent type board as claimed in claim 1, it is characterised in that：The SDH phaselocked loops are ZL30122 types Line card synchronizer.
5. A kind of 5. branch road convergent type board as claimed in claim 1, it is characterised in that：The encryption chip is DS28E01- 100 chips.
6. A kind of 6. branch road convergent type board as claimed in claim 1, it is characterised in that：The CPU is MPC8309 processors.
7. A kind of 7. branch road convergent type board as claimed in claim 1, it is characterised in that：The storage chip is deposited including Flash Store up chip and SDRAM storage chips, the Flash memory chip is M29W128GH70N6E chips, the SDRAM storage chips For MT47H64M16HR-3IT chips.
8. A kind of 8. branch road convergent type board as claimed in claim 1, it is characterised in that：The Ethernet switching chip is IP175G chips.
9. A kind of 9. branch road convergent type board as claimed in claim 1, it is characterised in that：The ethernet channel selector is TS3L100 logic switches.