CN207010649U - A kind of device based on lock phase and phase shift calibration combining unit tester clocking error - Google Patents
A kind of device based on lock phase and phase shift calibration combining unit tester clocking error Download PDFInfo
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- CN207010649U CN207010649U CN201720928151.2U CN201720928151U CN207010649U CN 207010649 U CN207010649 U CN 207010649U CN 201720928151 U CN201720928151 U CN 201720928151U CN 207010649 U CN207010649 U CN 207010649U
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Abstract
The utility model provides a kind of device based on lock phase and phase shift calibration combining unit tester clocking error, and described device includes：Standard time clock；First clock converting unit, it is used to the standard clock signal of input being converted into pulse per second (PPS) PPS signal；Second clock converting unit, it is used to the clock signal of combining unit tester clock output module to be measured output being converted into light-metering PPS signal to be checked or electric PPS signal；Phase-locked clock, it tracks the PPS signal of input using high frequency clock and locked mutually in the rising edge of PPS signal；Clock skew unit, it is used to set additional clock skew, and exports timing offset value；3rd clock converting unit, it is used to the timing offset value that clock skew unit exports being converted to IRIG_B codes or PPS signal, and the signal after conversion is transmitted to the clock input module of combining unit tester to be measured；Display unit, it is used to show phase-locked clock lock phase and the pps pulse per second signal that clock skew unit enters after line displacement.
Description
Technical field
The present invention relates to intelligent substation detection technique field, and more particularly, to one kind based on lock phase and phase shift
The apparatus and method for calibrating combining unit tester clocking error.
Background technology
With going deep into for intelligent substation construction, the indices of intelligent secondary device are substantially improved.It is high-precision to obtain
The process layer sampled data of degree, new requirement, State Grid Corporation of China's company standard are proposed to the clock accuracy of process layer devices
《Q/GDW 11015-2013 analog input formula combining unit inspection criterions》Point out combining unit (MU：Merging Unit) when
In clock error pair when error be not more than ± 1 μ s in 10min planted agent, the time keeping error of combining unit disappears in outer synchronous signal
Afterwards, 4 μ s can be at least not more than in 10min.This requires that the clocking error of secondary smart machine must when external clock is normal
1 μ s must be less than, and in outside loss of clock, 4 μ s precision can be kept within 10min time.These indexs are to intelligence two
Secondary device proposes very high requirement, according to the requirement traced to the source, the equipment as combining unit is verified, combining unit tester
Pair when timekeeping performance at least should 2 grades higher than combining unit, to merging needed for the standard device traced to the source of unit testing instrument
Precision it is higher, therefore for combining unit tester pair when, the test of time keeping error, it is necessary to develop the clock of high accuracy
Device, to meet the calibration of the correlation time performance to merging unit testing instrument.
The content of the invention
In order to solve to lack existing for background technology high-precision test combining unit tester pair when, time keeping error
The technical problem of device, the present invention provide a kind of dress that phase and phase shift calibration combining unit tester clocking error are locked based on FPGA
Put, its be used to calibrating combining unit tester pair when error and time keeping error, described device include：
Standard time clock, it is used for the standard clock signal for inputting calibration combining unit tester clocking error；
First clock converting unit, it is used to the standard clock signal of input being converted into PPS signal；
Second clock converting unit, it is used for the clock signal for exporting combining unit tester clock output module to be measured
It is converted into light-metering PPS signal to be checked or electric PPS signal；
Phase-locked clock, it uses FPGA modes, tracks the first clock converting unit using high frequency clock and second clock turns
Change the PPS signal of unit input and lock mutually in the rising edge of PPS signal；
Clock skew unit, it is used to set additional clock skew, and exports timing offset value；
3rd clock converting unit, its be used for by the timing offset value that clock skew unit exports be converted to IRIG_B codes,
Light PPS signal or electric PPS signal, and the clock that the signal after conversion is transmitted to combining unit tester to be measured inputs mould
Block；
Display unit, it is used to show that phase-locked clock enters the PPS signal of input horizontal lock and clock skew unit pair
The PPS signal that clock signal is entered after line displacement.
IRIG is English InterRange Instrumentation Group abbreviation.IRIG is U.S. target range instrument group
Abbreviation.IRIG time standards have two major classes：One kind is parallel time code form, and this kind of code is due to being parallel form, transmission distance
From relatively near, and it is binary system, therefore it is extensive to can not show a candle to serial form；Another kind of is serial time code, shares six kinds of forms, i.e. A,
B、D、E、G、H.They main difference is that the frame rate of timing code is different, IRIG-B is Type B code therein.The time frame of Type B code
Speed is 1 frame/s, can transmit the information of 100.As widely used timing code, the following main feature of Type B code tool：Carry
Contain much information, can obtain 1 after decoding, 10,100, the temporal information and control work(of 1000c/s pulse signal and BCD codings
Can information；High-resolution, the B code bandwidth after modulation, suitable for long-distance transmissions；It is divided to direct current, two kinds of exchange, there is interface standard
Change, it is international the features such as, what IRIG_B codes that we often say referred to is exactly direct current IRIG_B codes.
Preferably, the frequency for the clock that the phase-locked clock uses is 400MHz.
Preferably, the scope of the additional clock skew of the clock skew unit setting is 0~100 μ s.
Preferably, described device also includes a clock signal output terminal mouth, and it is used to give birth to second clock converting unit
Into electric PPS signal transmit to other standards equipment so that other standards equipment receives the generation of second clock converting unit
While electric PPS signal, the electric PPS signal of the 3rd clock converting unit generation is received, to trace to the source two-way clock signal
Or detection.
Calibrated and closed using the device of the present invention based on lock phase and phase shift calibration combining unit tester clocking error
It is and as follows the step of error during unit testing instrument pair：
Combining unit tester clock output module to be measured will export clock signal transmission to calibration combining unit tester
The second clock converting unit of the device of clocking error；
The synchronizing clock signals received are converted into light-metering PPS signal to be checked or electric PPS by second clock converting unit
Signal, and sent out by corresponding optical port or power port to phase-locked clock；
Phase-locked clock uses FPGA modes, tracks the first clock converting unit using high frequency clock and second clock changes list
The PPS signal of member input is simultaneously locked mutually in the rising edge of PPS signal；
When PPS signal after lock phase passes through clock skew unit, clock skew unit setting extra time shift simultaneously exports
Timing offset value；
The timing offset value of output is converted to IRIG_B codes, light PPS signal or electric PPS through the 3rd clock converting unit to be believed
Transmitted after number to the clock input module of combining unit tester to be measured；
The clock test module of combining unit tester to be measured carries out error to clock input signal and clock output signal
Calculate can draw combining unit tester pair when error.
Calibrated and closed using the device of the present invention based on lock phase and phase shift calibration combining unit tester clocking error
And the step of unit testing instrument time keeping error, is as follows：
Combining unit tester clock output module to be measured will export clock signal transmission to calibration combining unit tester
The second clock converting unit of the device of clocking error；
The synchronizing clock signals received are converted into light-metering PPS signal to be checked or electric PPS by second clock converting unit
Signal, and sent out by corresponding optical port or power port to phase-locked clock；
Phase-locked clock uses FPGA modes, tracks the first clock converting unit using high frequency clock and second clock changes list
The PPS signal of member input is simultaneously locked mutually in the rising edge of PPS signal；
After combining unit tester output clock signal to be measured reaches the set time, combining unit tester to be measured is disconnected
Clock output signal；
When the clock output signal of combining unit tester to be measured disconnects, phase-locked clock enters punctual pattern, when locking phase
The standard clock signal that clock exports according to standard time clock continues to output lock phase PPS signal；
When PPS signal after lock phase passes through clock skew unit, clock skew unit setting extra time shift simultaneously exports
Timing offset value；
The timing offset value of output is after the 3rd converting unit is converted to IRIG_B codes, light PPS signal or electric PPS signal
Transmit to the clock input module of combining unit tester to be measured；
The clock test module of combining unit tester to be measured is defeated to the clock input signal received and the clock of itself
The time keeping error of combining unit tester can be drawn by going out signal progress error calculation.
Compared with prior art, technical scheme proposes one kind and is based on technical scheme provided by the present invention
FPGA locks are mutually and the device of combining unit tester clocking error is calibrated in phase shift, solve combining unit tester well and trace to the source
When needing high-precision pair the problem of time keeping device.
Brief description of the drawings
By reference to the following drawings, the illustrative embodiments of the present invention can be more fully understood by：
Fig. 1 is the dress based on lock phase and phase shift calibration combining unit tester time keeping error of the specific embodiment of the invention
The structure chart put；
Embodiment
The illustrative embodiments of the present invention are introduced with reference now to accompanying drawing, however, the present invention can use many different shapes
Formula is implemented, and is not limited to embodiment described herein, there is provided these embodiments are to disclose at large and fully
The present invention, and fully pass on the scope of the present invention to person of ordinary skill in the field.Show for what is be illustrated in the accompanying drawings
Term in example property embodiment is not limitation of the invention.In the accompanying drawings, identical cells/elements are attached using identical
Icon is remembered.
Unless otherwise indicated, term (including scientific and technical terminology) used herein has to person of ordinary skill in the field
It is common to understand implication.Further it will be understood that the term limited with usually used dictionary, be appreciated that and its
The linguistic context of association area has consistent implication, and is not construed as Utopian or overly formal meaning.
Fig. 1 is the dress based on lock phase and phase shift calibration combining unit tester time keeping error of the specific embodiment of the invention
The structure chart put.As shown in figure 1, the device that phase and phase shift calibration combining unit tester clocking error are locked based on FPGA
100 be used to calibrating combining unit tester pair when error and time keeping error, when described device includes standard time clock 101, first
Clock converting unit 102, second clock converting unit 103, phase-locked clock 104, clock skew unit 105, the conversion of the 3rd clock are single
Member 106, clock signal output terminal mouth 107 and display unit 108.
Standard time clock 101, it is used for the standard clock signal for inputting calibration combining unit tester clocking error.In this reality
Apply in example, standard time clock uses rubidium clock.Rubidium clock is otherwise known as rubidium atomic clock, and rubidium atomic clock is shaken by rubidium quantum part and voltage-controlled crystal (oscillator)
Swing device composition.The frequency of VCXO passes through frequency multiplication and frequency synthesis, is sent to quantized system and rubidium atomic transition frequency
It is compared.Error signal sends back to VCXO, and its frequency is adjusted, and it is locked in rubidium atom distinctive
In frequency corresponding to energy level transition.Rb atom frequency marking short-term stability can reach 10-12Magnitude, the degree of accuracy be ± 5 ×
10-11, often it is divided into classification：Plain edition, military version, space flight type etc..Because its small volume, precision are high, so most widely used.
First clock converting unit 102, it is used to the standard clock signal of input being converted into PPS signal.
Second clock converting unit 103, it is used for the clock for exporting combining unit tester clock output module to be measured
Signal is converted into light-metering PPS signal to be checked or electric PPS signal.
Phase-locked clock 104, it uses FPGA modes, and the first clock converting unit and second clock are tracked using high frequency clock
The PPS signal of converting unit input is simultaneously locked mutually in the rising edge of PPS signal.
Clock skew unit 105, it is used to set additional clock skew, and exports timing offset value.
3rd clock converting unit 106, it is used to the timing offset value that clock skew unit exports being converted to IRIG_B
Code, light PPS signal or electric PPS signal, and the signal after conversion is transmitted to the clock input of combining unit tester to be measured
Module.
Display unit, it is used to show that phase-locked clock enters the PPS signal of input horizontal lock and clock skew unit pair
The PPS signal that clock signal is entered after line displacement.
Preferably, the frequency for the clock that the phase-locked clock 104 uses is 400MHz.When phase-locked clock uses 400MHz's
During high steady master clock, the resolution ratio of one second is 2.5ns, and when the periodicity of tested input clock is longer, FPGA clock is differentiated
Rate is higher.
Preferably, the scope for the additional clock skew that the clock skew unit 105 is set is 0~100 μ s.
Preferably, described device also includes a clock signal output terminal mouth 107, and it is used for second clock converting unit
The electric PPS signal of 106 generations is transmitted to other standards equipment, so that other standards equipment receives second clock converting unit
While the electric PPS signal of 103 generations, the electric PPS signal of the 3rd clock converting unit 106 generation is received, with to two-way clock
Signal is traced to the source or detected.
Normally, all terms used in the claims are all solved according to them in the usual implication of technical field
Release, unless clearly being defined in addition wherein.All references " one/described/be somebody's turn to do【Device, component etc.】" all it is opened ground
At least one example being construed in described device, component etc., unless otherwise expressly specified.Any method disclosed herein
Step need not all be run with disclosed accurately order, unless explicitly stated otherwise.
Claims (4)
1. a kind of device based on lock phase and phase shift calibration combining unit tester clocking error, it is used to calibrate combining unit survey
Examination instrument pair when error and time keeping error, described device include：
Standard time clock, it is used for the standard clock signal for inputting calibration combining unit tester clocking error；
First clock converting unit, it is used to the standard clock signal of input being converted into pulse per second (PPS) PPS signal；
Second clock converting unit, it is used to change the clock signal of combining unit tester clock output module to be measured output
Into light-metering PPS signal to be checked or electric PPS signal；
Phase-locked clock, it uses FPGA modes, tracks the first clock converting unit using high frequency clock and second clock changes list
The PPS signal of member input is simultaneously locked mutually in the rising edge of PPS signal；
Clock skew unit, it is used to set additional clock skew, and exports timing offset value；
3rd clock converting unit, it is used to the timing offset value that clock skew unit exports being converted to IRIG_B codes, light PPS
Signal or electric PPS signal, and the signal after conversion is transmitted to the clock input module of combining unit tester to be measured；
Display unit, it is used to show that phase-locked clock enters the PPS signal of input horizontal lock and clock skew unit to clock
The PPS signal that signal enters after line displacement.
2. device according to claim 1, it is characterised in that the frequency for the clock that the phase-locked clock uses is
400MHz。
3. device according to claim 1, it is characterised in that the additional clock skew of the clock skew unit setting
Scope is 0~100 μ s.
4. device according to claim 1, it is characterised in that described device also includes a clock signal output terminal mouth,
Its electric PPS signal for being used to generate second clock converting unit is transmitted to other standards equipment, so that other standards equipment
While receiving the electric PPS signal of second clock converting unit generation, the electric PPS letters of the 3rd clock converting unit generation are received
Number, so that two-way clock signal is traced to the source or detected.
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| CN201720928151.2U CN207010649U (en) | 2017-07-27 | 2017-07-27 | A kind of device based on lock phase and phase shift calibration combining unit tester clocking error |
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| CN201720928151.2U CN207010649U (en) | 2017-07-27 | 2017-07-27 | A kind of device based on lock phase and phase shift calibration combining unit tester clocking error |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107359873A (en) * | 2017-07-27 | 2017-11-17 | 中国电力科学研究院 | A kind of apparatus and method based on lock phase and phase shift calibration combining unit tester clocking error |
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- 2017-07-27 CN CN201720928151.2U patent/CN207010649U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107359873A (en) * | 2017-07-27 | 2017-11-17 | 中国电力科学研究院 | A kind of apparatus and method based on lock phase and phase shift calibration combining unit tester clocking error |
| CN107359873B (en) * | 2017-07-27 | 2024-02-23 | 中国电力科学研究院 | Device and method for calibrating clock error of merging unit tester based on phase locking and phase shifting |
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