CN103812731A - Digitization sampling time delay frequency conversion measuring method and measuring system - Google Patents

Abstract

The invention discloses a digitization sampling time delay frequency conversion measuring method, and the method measures the non integer period time delay to the different frequency steady state analog quantity signals from an electronic transformer or analog inputting and merging unit to obtain the inertial time delay to all frequency signals from the digitization sampling process, including the non integer period time delay and integer period time delay, compensates the sending time difference for SV message based on the transmit frequency of the phaselock technique tracking SV message, reduces the influence caused by the sending time difference for SV message, and raises the digitization sampling time delay measuring precision. The invention also discloses a test system based on the method for ensuring the reliable application of the electronic transformer and the analog inputting and merging unit in the intelligent substation, eliminating the potential safety hazard of the electronic transformer and the analog inputting and merging unit on engineering application, raising the second-order system running veracity for the intelligent substation and having significance to the safe and reliable operation for the intelligent substation.

Description

A kind of digitized sampling time delay frequency conversion method of measurement and measuring system

Technical field

The present invention relates to a kind of digitized sampling time delay frequency conversion method of measurement and measuring system, belong to power automation technical field.

Background technology

Electronic mutual inductor comprises electronic current mutual inductor (being called for short ECT, i.e. Electronic Current Transformer) and electronic type voltage transformer (being called for short EVT, i.e. Electronic Voltage Transformer).Analog input merge cells refers to the merge cells of direct reception routine transformer secondary analog output, such as the merge cells for connection bus TV.Electronic mutual inductor and analog input merge cells are all that the input of analog quantity is carried out to digitized sampling, finally export digital quantity.Digitized sampling has replaced conventional cable transmission with fiber optic network transmission, thereby can avoid cable multiple spot contact, Current Transformer Secondary open circuit, voltage transformer secondary short circuit, grow the problems such as Distance Transmission loss is large, and the digitalized network transmission means of sampled value is conducive to sharing of data, adapts to intelligent substation developing direction.Therefore, the digitized sampling mode of electronic mutual inductor and analog input merge cells has obtained extensive application in intelligent substation.

The digitized sampling of electronic mutual inductor and analog input merge cells all needs, through links such as data acquisition, data processing, wait and transmission, to need the regular hour.Wherein, data acquisition, data processing and wait link generally complete based on Interruption, and Interruption is generally the integral multiple in sampling period, and required time of these links is longer, is the major part of whole sampling time delay, reaches ms level.And data send and the time delay of transmission link has certainty scarcely, but this part time delay is little, less to total delay of whole sampling element.

The time delay of digitized sampling can be divided into time delay complete cycle and non-integer-period time delay.In intelligent substation, between the sampling of relaying protection, merge cells in the application of the point-to-point Direct Sampling such as cascade, must carrying out interpolation based on the time delay of sampling element, to realize data synchronous, and the time delays of sampling in these application must accurately be measured as an important parameter.In the corresponding standard of intelligent substation, require digitized sampling time delay can not be greater than 2ms, when digitized sampling exists N time delay complete cycle, in order to meet technical requirement in form, electronic mutual inductor or merge cells manufacturer may be by SV(Sampled Value, being sampled value) sequence number of message is to N cycle of reach, now also has impact for the certainty of measurement of the application such as the metering based on external signal synchronized sampling, observing and controlling, failure wave-recording.Therefore, the time delay of digitized sampling, as key parameter, must guarantee its correctness in engineering application.

At present, digitized sampling Time delay measurement method is generally power current or the voltage that applies stable state to electronic mutual inductor or analog input merge cells, the time delay that then utilizes the phase angle relationship of power frequency component between standard analog amount and tested SV data indirectly to measure digitized sampling.This method of measurement is for can correct measurement phase relation, must apply the analog quantity of stable state, for periodic signal, there is certain phase difference in the waveform after non-integer-period time delay and original signal waveform, therefore can obtain by the poor method that is then converted to the time of this measurement stable phase the non-integer-period time delay of digitized sampling.And for signal steady-state period, after time delay complete cycle, overlap completely with original signal, there is not phase difference, therefore cannot utilize the poor method of this measurement stable phase to measure time delay complete cycle.At present, also have a kind of digitized sampling delay test method to be: under synchronous mode, to obtain digitized sampling time delay by the time difference of measuring between transmitting time and the synchronizing signal of 0 sequence number SV message.But this method for SV test serial number have artificial reach or after the phenomenon of moving cannot detect, time delay complete cycle that therefore also cannot correct measurement digitized sampling.

The links such as data acquisition in the digitized sampling process of electric mutual inductor and analog input merge cells, data processing, wait and transmission are consistent for the required time of various input signals, this time delay that embodies digitized sampling is a group delay, is identical for the time delay of the signal of various frequencies.For steady-state period signal, this time delay can be divided into time delay complete cycle and non-integer-period time delay, wherein non-integer-period time delay can be measured by the method for measuring phase difference between digitized sampling input and output, but time delay complete cycle is difficult to identification and measures.Time delay complete cycle may cause incorrect operation for relaying protection application, also can cause accuracy error for metering, observing and controlling, therefore also must accurately reach identification.

Therefore, be necessary to adopt a kind of new digitized sampling Time delay measurement method and measuring system, can accurately measure time delay complete cycle and non-integer-period time delay in digitized sampling link, eliminate the potential safety hazard in electronic mutual inductor and the application of analog input merge cells engineering, improve intelligent substation electrical secondary system operation accuracy, safety, reliability service to intelligent substation are significant.

Summary of the invention

The object of the present invention is to provide a kind of digitized sampling time delay frequency conversion method of measurement, solve the problem that existing method of measurement can not accurately measure time delay complete cycle in digitized sampling link, also provide the measuring system based on this method of measurement, overcome the potential safety hazard in electronic mutual inductor and the application of analog input merge cells engineering simultaneously.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is:

A kind of digitized sampling time delay frequency conversion method of measurement, comprises the following steps,

Step 1, giving electronic mutual inductor or analog input merge cells incoming frequency is f ₁steady-state simulation amount signal;

Step 2, measuring frequency is f ₁steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, sending shake time difference compensation in conjunction with phase calculation point time difference compensation and SV message, to calculate frequency be f ₁the time delay aperiodic T of steady-state simulation amount signal _{d1_NP}, by time delay aperiodic T _{d1_NP}acquisition frequency is f ₁the full time delay T of steady-state simulation amount signal after digitized sampling _d1=T _{d1_NP}+ m ₁t ₁, T ₁=1/f ₁, m ₁for nonnegative integer;

Step 3, giving electronic mutual inductor or analog input merge cells incoming frequency is f ₂steady-state simulation amount signal, wherein f ₁≠ f ₂;

Step 4, measuring frequency is f ₂steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, sending shake time difference compensation in conjunction with phase calculation point time difference compensation and SV message, to calculate frequency be f ₂the time delay aperiodic T of steady-state simulation amount signal _{d2_NP}, by time delay aperiodic T _{d2_NP}acquisition frequency is f ₂the full time delay T of steady-state simulation amount signal after digitized sampling _d2=T _{d2_NP}+ m ₂t ₂, T ₂=1/f ₂, m ₂for nonnegative integer;

Step 5, based on sampling group delay principle T _d1=T _d2, calculate m ₁and m ₂, obtain the value of the full time delay of digitized sampling.The process that obtains full time delay in step 2 is,

Step (A1), the frequency of calculating input electronic mutual inductor or analog input merge cells is f ₁steady-state simulation amount signal t ₁the phase place in moment

;

Step (B1), calculates the digital quantity SV signal t of electronic mutual inductor or the output of analog input merge cells ₁the phase place in ' moment

, wherein t ₁'≤t ₁, t ₁a point of corresponding SV message of ' moment, this point is t ₁message point or this point of moment electronic mutual inductor or the output of analog input merge cells are t ₁last message point of electronic mutual inductor or the output of analog input merge cells before moment;

Step (C1), by what obtain in step (A1) and step (B1)

with

calculating frequency is f ₁steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, and this phase difference is converted to the time

1;

Step (D1), calculates the phase calculation point time difference, t ₁moment and t ₁time difference Δ t between the ' moment ₁=t ₁-t ₁';

Step (E1), calculates SV message and sends shake time difference Δ T ₁;

Step (F1), according to what obtain in step (C1), step (D1) and step (E1)

, Δ t ₁with Δ T ₁, calculating frequency is f ₁time delay aperiodic of steady-state simulation amount signal

Step (G1), the full time delay of the steady-state simulation amount signal that acquisition frequency is f1 after digitized sampling is

Step (E1) is calculated SV message and is sent shake time difference Δ T ₁process,

Step (a1), adopts Phase Lock Technique to follow the tracks of the transmission frequency of digital quantity SV signal, the equispaced T of locking SV message _sV1;

Step (b1), by SV message K ₁, K ₁-1 time of reception

, calculate K ₁the actual interval of some message and former frame message

;

Step (c1), calculates actual interval

with equispaced T _sV1deviation ${{\mathrm{\&Delta;<figure-callout\; id="1"\; label="T\; k"\; filenames="HDA0000471899550000031.png"\; state="\{\{state\}\}">T</figure-callout>}}_k}_1={T_{\mathrm{SV}1-K}}_1-{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA0000471899550000031.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}};$

Step (d1), by SV message K ₁-1, K ₁-2 times of reception

, calculate K ₁the actual interval of-1 message and former frame message

;

Step (e1), calculates actual interval

with equispaced T _sV1deviation ${\mathrm{\&Delta;T}}_{k_1-1}=T_{\mathrm{SV}1-K_1-1}-{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA0000471899550000031.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}};$

Step (f1), by K ₁with K ₁the message spacing bias of-1, calculates SV message K ₁the shake time difference that point sends

.

The process that obtains full time delay in step 4 is,

Step (A2), the frequency of calculating input electronic mutual inductor or analog input merge cells is f ₂steady-state simulation amount signal t ₂the phase place in moment

;

Step (B2), calculates the digital quantity SV signal t of electronic mutual inductor or the output of analog input merge cells ₂the phase place in ' moment

, wherein t ₂'≤t ₂, t ₂a point of corresponding SV message of ' moment, this point is t ₂message point or this point of moment electronic mutual inductor or the output of analog input merge cells are t ₂last message point of electronic mutual inductor or the output of analog input merge cells before moment;

Step (C2), by what obtain in step (A2) and step (B2)

with

calculating frequency is f ₂steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, and this phase difference is converted to the time ;

Step (D2), calculates the phase calculation point time difference, t ₂moment and t ₂time difference Δ t between the ' moment ₂=t ₂-t ₂';

Step (E2), calculates SV message and sends shake time difference Δ T ₂;

Step (F2), according to what obtain in step (C2), step (D2) and step (E2)

, Δ t ₂with Δ T ₂, calculating frequency is f ₂time delay aperiodic of steady-state simulation amount signal

Step (G2), acquisition frequency is f ₂the full time delay of steady-state simulation amount signal after digitized sampling be

Step (E2) is calculated SV message and is sent shake time difference Δ T ₂process as follows,

Step (a2), adopts Phase Lock Technique to follow the tracks of the transmission frequency of digital quantity SV signal, the equispaced T of locking SV message _sV2;

Step (b2), by SV message K ₂, K ₂-1 time of reception , calculate K ₂the actual interval of some message and former frame message

Step (c2), calculates actual interval with equispaced T _sV2deviation ${\mathrm{\&Delta;T}}_{k2}={T_{\mathrm{SV}2\_K}}_2-T_{\mathrm{SV}2};$

Step (d2), by SV message K ₂-1, K ₂-2 times of reception

, calculate K ₂the actual interval of-1 message and former frame message

Step (e2), calculates actual interval

with equispaced T _sV2deviation ${\mathrm{\&Delta;T}}_{k_2-1}=T_{\mathrm{SV}2-K_2-1}-T_{\mathrm{SV}2};$

Step (f2), by K ₂with K ₂the message spacing bias of-1, calculates SV message K ₂the shake time difference that point sends

.

A measuring system for digitized sampling time delay frequency conversion method of measurement, comprises analog output part and gathers measure portion, described analog output part, for tested electronic mutual inductor or analog input merge cells provide steady-state simulation amount signal, provides the secondary singal of the tested electronic mutual inductor of reflection or the input of analog input merge cells simultaneously for gathering measure portion, in the time of analog output part external connected electronic formula instrument transformer, described analog output part comprises the standard mutual inductor, up-flow/stepup transformer and the frequency-variable controller that connect successively, described standard mutual inductor is as the linkage unit of analog output part and electronic mutual inductor, simultaneously also as analog output part and the linkage unit that gathers measure portion, in the time of the external analog input merge cells of analog output part, described analog output part comprises the power amplifier and the frequency-variable controller that connect successively, described power amplifier is as the linkage unit of analog output part and analog input merge cells, simultaneously also as analog output part and the linkage unit that gathers measure portion, the secondary singal that described collection measure portion sends in order to gather analog output part, gather the digital quantity SV signal of electronic mutual inductor or the output of analog input merge cells simultaneously, in order to measure and to calculate digitized sampling time delay, the time delay result calculating in order to display measurement, described collection measure portion comprises AD modular converter, internal clocking module, SV gathers and time mark module, measuring and calculating module and result display module, described AD modular converter, SV gathers and is all connected with measuring and calculating module with result display module with time mark module, described internal clocking module is for generation of the sampling pulse of AD modular converter, and for SV gather and time mark module temporal information is provided, described AD modular converter is as the linkage unit of analog output part and collection measure portion, the digital quantity SV signal that described SV gathers and time mark module is exported in order to gather electronic mutual inductor or analog input merge cells.

The invention has the beneficial effects as follows: 1, the present invention is based on Frequency Conversion Theory, by measuring electronic mutual inductor or the non-integer-period time delay of analog input merge cells to different frequency steady-state simulation amount signal, calculate the inherent delay of digitized sampling link to all frequency signals, comprise non-integer-period time delay and time delay complete cycle, follow the tracks of the transmission frequency of SV message based on Phase Lock Technique simultaneously, compensation SV message sends the shake time difference, reduce the impact that SV message sends the time difference, improve digitized sampling Time delay measurement accuracy; 2, the present invention can measure time delay complete cycle of digitized sampling link under steady-state simulation amount signal, efficiently solve in the application of electronic mutual inductor and analog input merge cells engineering cannot Measurement accuracy time delay complete cycle problem, guarantee electronic mutual inductor and the reliability application of analog input merge cells in intelligent substation, eliminate the potential safety hazard in electronic mutual inductor and the application of analog input merge cells engineering, improve intelligent substation electrical secondary system operation accuracy, safety, reliability service to intelligent substation are significant.

Accompanying drawing explanation

Fig. 1 is a kind of flow chart of digitized sampling time delay frequency conversion method of measurement.

Fig. 2 is f for obtaining frequency ₁the flow chart of the full time delay of steady-state simulation amount signal after digitized sampling.

Fig. 3 sends shake time difference Δ T for calculating SV message ₁flow chart.

Fig. 4 is a kind of structured flowchart of digitized sampling time delay frequency conversion measuring system.

Fig. 5 is the structural representation of measuring system external connected electronic formula instrument transformer.

Fig. 6 is the structural representation of the external analog input merge cells of measuring system.

Embodiment

Below in conjunction with Figure of description, the invention will be further described.Following examples are only for technical scheme of the present invention is more clearly described, and can not limit the scope of the invention with this.

As shown in Figure 1, a kind of digitized sampling time delay frequency conversion method of measurement, comprises the following steps,

Step 1, giving electronic mutual inductor or analog input merge cells incoming frequency is f ₁steady-state simulation amount signal.

Step 2, measuring frequency is f ₁steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, sending shake time difference compensation in conjunction with phase calculation point time difference compensation and SV message, to calculate frequency be f ₁the time delay aperiodic T of steady-state simulation amount signal _{d1_NP}, by time delay aperiodic T _{d1_NP}acquisition frequency is f ₁the full time delay T of steady-state simulation amount signal after digitized sampling _d1=T _{d1_NP}+ m ₁t ₁, T ₁=1/f ₁, m ₁for nonnegative integer.

Acquisition frequency is f ₁the full time delay of steady-state simulation amount signal after digitized sampling process as shown in Figure 3:

Step (A1), the frequency of calculating input electronic mutual inductor or analog input merge cells is f ₁steady-state simulation amount signal t ₁the phase place in moment

;

Step (B1), calculates the digital quantity SV signal t of electronic mutual inductor or the output of analog input merge cells ₁the phase place in ' moment

, wherein t ₁'≤t ₁, t ₁a point of corresponding SV message of ' moment, this point is t ₁message point or this point of moment electronic mutual inductor or the output of analog input merge cells are t ₁last message point of electronic mutual inductor or the output of analog input merge cells before moment.

Step (C1), by what obtain in step (A1) and step (B1)

with

calculating frequency is f ₁steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, and this phase difference is converted to the time

.

Step (D1), calculates the phase calculation point time difference, t ₁moment and t ₁time difference Δ t between the ' moment ₁=t ₁-t ₁'.

Step (E1), calculates output SV message and sends shake time difference Δ T ₁, concrete steps are as follows:

Step (a1), adopts Phase Lock Technique to follow the tracks of the transmission frequency of digital quantity SV signal, the equispaced T of locking SV message _sV1;

Step (b1), by SV message K ₁, K ₁-1 time of reception

, calculate K ₁the actual interval of some message and former frame message

Step (c1), calculates actual interval with equispaced T _sV1deviation ${{\mathrm{\&Delta;<figure-callout\; id="1"\; label="T\; k"\; filenames="HDA0000471899550000031.png"\; state="\{\{state\}\}">T</figure-callout>}}_k}_1={{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA0000471899550000031.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}}_1-{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA0000471899550000031.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}};$

Step (d1), by SV message K ₁-1, K ₁-2 times of reception

, calculate K ₁the actual interval of-1 message and former frame message ;

Step (e1), calculates actual interval

with equispaced T _sV1deviation ${\mathrm{\&Delta;T}}_{k_1-1}=T_{\mathrm{SV}1-K_1-1}-{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA0000471899550000031.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}};$

Step (f1), by K ₁with K ₁the message spacing bias of-1, calculates SV message K ₁the shake time difference that point sends

.

Step (F1), according to what obtain in step (C1), step (D1) and step (E1) , Δ t ₁with Δ T ₁, calculating frequency is f ₁time delay aperiodic of steady-state simulation amount signal

Step (G1), acquisition frequency is f ₁the full time delay of steady-state simulation amount signal after digitized sampling be

Step 3, giving electronic mutual inductor or analog input merge cells incoming frequency is f ₂steady-state simulation amount signal, wherein f ₁≠ f ₂.

Step 4, measuring frequency is f ₂steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, sending shake time difference compensation in conjunction with phase calculation point time difference compensation and SV message, to calculate frequency be f ₂the time delay aperiodic T of steady-state simulation amount signal _{d2_NP}, by time delay aperiodic T _{d2_NP}acquisition frequency is f ₂the full time delay T of steady-state simulation amount signal after digitized sampling _d2=T _{d2_NP}+ m ₂t ₂, T ₂=1/f ₂, m ₂for nonnegative integer.

Acquisition frequency is f ₂the full time delay process of steady-state simulation amount signal after digitized sampling be f with obtaining frequency ₁the process of the full time delay of steady-state simulation amount signal after digitized sampling consistent, specific as follows:

Step (A2), the frequency of calculating input electronic mutual inductor or analog input merge cells is f ₂steady-state simulation amount signal t ₂the phase place in moment

.

Step (B2), calculates the digital quantity SV signal t of electronic mutual inductor or the output of analog input merge cells ₂the phase place in ' moment

, wherein t ₂'≤t ₂, t ₂a point of corresponding SV message of ' moment, this point is t ₂message point or this point of moment electronic mutual inductor or the output of analog input merge cells are t ₂last message point of electronic mutual inductor or the output of analog input merge cells before moment.

Step (C2), by what obtain in step (A2) and step (B2)

with calculating frequency is f ₂steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, and this phase difference is converted to the time

Step (D2), calculates the phase calculation point time difference, t ₂moment and t ₂time difference Δ t between the ' moment ₂=t ₂-t ₂'.

Step (E2), calculates SV message and sends shake time difference Δ T ₂, in detailed process and step (E1), calculate SV message and send time difference Δ T ₁process consistent, specific as follows:

Step (a2), adopts Phase Lock Technique to follow the tracks of the transmission frequency of digital quantity SV signal, the equispaced T of locking SV message _sV2;

Step (b2), by SV message K ₂, K ₂-1 time of reception

, calculate K ₂the actual interval of some message and former frame message

Step (c2), calculates actual interval

with equispaced T _sV2deviation ${\mathrm{\&Delta;T}}_{k2}={T_{\mathrm{SV}2\_K}}_2-T_{\mathrm{SV}2};$

Step (d2), by SV message K ₂-1, K ₂-2 times of reception

, calculate K ₂the actual interval of-1 message and former frame message

;

Step (e2), calculates actual interval

with equispaced T _sV2deviation ${\mathrm{\&Delta;T}}_{k_2-1}=T_{\mathrm{SV}2\_K_2-1}-T_{\mathrm{SV}2};$

Step (f2), by K ₂with K ₂the message spacing bias of-1, calculates SV message K ₂the shake time difference that point sends

.

Step (F2), according to what obtain in step (C2), step (D2) and step (E2)

, Δ t ₂with Δ T ₂, calculating frequency is f ₂time delay aperiodic of steady-state simulation amount signal

Step (G2), acquisition frequency is f ₂the full time delay of steady-state simulation amount signal after digitized sampling be

Step 5, based on sampling group delay principle T _d1=T _d2, calculate m ₁and m ₂, obtain the value of the full time delay of digitized sampling.M ₁and m ₂theory calculates as multiple values, and the number of value and the frequency f of signal ₁and f ₂relevant, frequency f ₁and f ₂more approaching, m ₁and m ₂number fewer; m ₁and m ₂value larger, the time delay of digitized sampling link is larger, in actual application, the time delay of digitized sampling link should be within the specific limits, and can select steady-state simulation amount signal that frequency is close as input signal, thereby determine m ₁and m ₂occurrence, calculate full time delay.

The measuring system of above-mentioned digitized sampling time delay frequency conversion method of measurement as shown in Figure 4, comprises analog output part and collection measure portion, and two parts can adopt and disperse design, and independent control, also can adopt integrated design to realize closed-loop control.

Described analog output part, for tested electronic mutual inductor or analog input merge cells provide steady-state simulation amount signal, provides the secondary singal of the tested electronic mutual inductor of reflection or the input of analog input merge cells simultaneously for gathering measure portion.

In the time of analog output part external connected electronic formula instrument transformer as Fig. 5, described analog output part comprises the standard mutual inductor, up-flow/stepup transformer and the frequency-variable controller that connect successively, described standard mutual inductor is as the linkage unit of analog output part and electronic mutual inductor, simultaneously also as analog output part and the linkage unit that gathers measure portion.The concrete function of above-mentioned parts is as follows:

Frequency-variable controller: for controlling the frequency of a steady-state simulation amount signal of up-flow/stepup transformer output, variable frequency control reaches by changing the input power frequency of up-flow/stepup transformer the object of controlling its output steady-state simulation amount signal frequency.

Up-flow/stepup transformer: produce once large electric current or high voltage, for tested electronic mutual inductor provides a steady-state simulation amount signal input.

Standard mutual inductor: the steady-state simulation amount signal that up-flow/stepup transformer is produced is secondary singal by preset proportion linear transformation, and secondary singal is transferred to collection measure portion, and standard mutual inductor does not change steady-state simulation amount signal one time.

The configuration of up-flow/stepup transformer and standard mutual inductor is determined according to tested electronic mutual inductor type, in the time that tested electronic mutual inductor is current transformer, up-flow/stepup transformer adopts current lifting device, standard mutual inductor adopts standard current transformer, and seal in the loop between current lifting device and tested electronic current mutual inductor, once large current conversion is the little electric current of secondary; In the time being voltage transformer by side electronic mutual inductor, up-flow/stepup transformer adopts stepup transformer, standard mutual inductor adopts standard potential transformer, and is connected on the loop between stepup transformer and tested electronic type voltage transformer, and a high voltage is converted to secondary low-voltage.

In the time of the external analog input merge cells of analog output part as Fig. 6, described analog output part comprises the power amplifier and the frequency-variable controller that connect successively, described power amplifier is as the linkage unit of analog output part and analog input merge cells, simultaneously also as analog output part and the linkage unit that gathers measure portion.The concrete function of above-mentioned parts is as follows:

Frequency-variable controller: for the frequency of power ratio control amplifier output steady-state simulation amount signal, the small-signal that the direct output frequency of variable frequency control is variable, inputs to power amplifier.

Power amplifier: for the small-signal of frequency-variable controller output is enlarged into substation secondary signal, power amplifier can be exported secondary current steady-state simulation amount signal and secondary voltage steady-state simulation amount signal, secondary singal is directly connected to tested analog input merge cells, also transfer to collection measure portion simultaneously, in the time that steady-state simulation amount signal is electric current, the secondary singal line that is connected to collection measure portion seals in the loop of power amplifier and tested merge cells; In the time that steady-state simulation amount signal is voltage, be connected to gather measure portion secondary singal line and be connected to power amplifier and the loop of tested merge cells on.

The secondary singal that described collection measure portion sends in order to gather analog output part, gather the digital quantity SV signal of electronic mutual inductor or the output of analog input merge cells simultaneously, in order to measure and to calculate digitized sampling time delay, the time delay result calculating in order to display measurement.

Described collection measure portion comprises AD modular converter, internal clocking module, SV gathers and time mark module, measuring and calculating module and result display module, described AD modular converter, SV gather with time mark module be all connected with measuring and calculating module, described internal clocking module is for generation of the sampling pulse of AD modular converter, and for SV gather and time mark module temporal information is provided, described AD modular converter is as the linkage unit of analog output part and collection measure portion, the digital quantity SV signal that described SV gathers and time mark module is exported in order to gather electronic mutual inductor or analog input merge cells.The concrete function of above-mentioned parts is as follows:

AD modular converter: for gathering the secondary singal of analog output part, analog quantity is converted to digital quantity signal for measuring and calculating module processing, the sample frequency of AD modular converter should be higher than the sample frequency of measured number sampling element, and sampling pulse is produced by this part internal clocking.

SV gathers and time mark module: for receiving SV message, record SV message and reach the moment, and data in SV message are resolved, extracted, for measuring and calculating module processing; This module can be realized by high-performance FPGA, and temporal information is provided by internal clocking module.

Internal clocking module: for generation of the sampling pulse of AD modular converter, and for SV gather and time mark module temporal information is provided, to guarantee the unification of two module temporal informations; Internal clocking is realized by inner High Precision Crystal Oscillator.

Measuring and calculating module: the measurement of the data of AD modular converter and SV acquisition time mark module being processed to laggard line delay based on aforementioned Time delay measurement method is calculated, and draws the full time delay of going out of measured number sampling element.

Result display module: the final measuring and calculating module result of calculating is shown, result display module can show with patterned way or data list mode.

In sum, the present invention is based on Frequency Conversion Theory, by measuring electronic mutual inductor or the non-integer-period time delay of analog input merge cells to different frequency steady-state simulation amount signal, thereby calculate the inherent delay of digitized sampling link to all frequency signals, comprise non-integer-period time delay and time delay complete cycle, follow the tracks of the transmission frequency of SV message simultaneously based on Phase Lock Technique, compensation SV message sends the time difference, reduce the impact that SV message sends the time difference, improve digitized sampling Time delay measurement accuracy; The present invention can measure time delay complete cycle of digitized sampling link under steady-state simulation amount signal, efficiently solve in the application of electronic mutual inductor and analog input merge cells engineering cannot Measurement accuracy time delay complete cycle problem, guarantee electronic mutual inductor and the reliability application of analog input merge cells in intelligent substation, eliminate the potential safety hazard in electronic mutual inductor and the application of analog input merge cells engineering, improve intelligent substation electrical secondary system operation accuracy, safety, reliability service to intelligent substation are significant.

More than show and described basic principle of the present invention, principal character and advantage.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that in above-described embodiment and specification, describes just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.

Claims (6)

1. a digitized sampling time delay frequency conversion method of measurement, is characterized in that: comprises the following steps,

Step 1, giving electronic mutual inductor or analog input merge cells incoming frequency is f ₁steady-state simulation amount signal;

Step 2, measuring frequency is f ₁steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

sending shake time difference compensation in conjunction with phase calculation point time difference compensation and SV message, to calculate frequency be f ₁the time delay aperiodic T of steady-state simulation amount signal _{d1_NP}, by time delay aperiodic T _{d1_NP}acquisition frequency is f ₁the full time delay T of steady-state simulation amount signal after digitized sampling _d1=T _{d1_NP}+ m ₁t ₁, T ₁=1/f ₁, m ₁for nonnegative integer;

Step 3, giving electronic mutual inductor or analog input merge cells incoming frequency is f ₂steady-state simulation amount signal, wherein f ₁≠ f ₂;

Step 4, measuring frequency is f ₂steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, in conjunction with phase calculation point time difference compensation and and SV message send shake time difference compensation to calculate frequency be f ₂the time delay aperiodic T of steady-state simulation amount signal _{d2_NP}, by time delay aperiodic T _{d2_NP}acquisition frequency is f ₂the full time delay T of steady-state simulation amount signal after digitized sampling _d2=T _{d2_NP}+ m ₂t ₂, T ₂=1/f ₂, m ₂for non-negative positive integer;

Step 5, based on sampling group delay principle T _d1=T _d2, calculate m ₁and m ₂, obtain the value of the full time delay of digitized sampling.

2. a kind of digitized sampling time delay frequency conversion method of measurement according to claim 1, is characterized in that: the process that obtains full time delay in step 2 is,

Step (A1), the frequency of calculating input electronic mutual inductor or analog input merge cells is f ₁steady-state simulation amount signal t ₁the phase place in moment

Step (B1), calculates the digital quantity SV signal t of electronic mutual inductor or the output of analog input merge cells ₁the phase place in ' moment wherein t ₁'≤t ₁, t ₁a point of corresponding SV message of ' moment, this point is t ₁message point or this point of moment electronic mutual inductor or the output of analog input merge cells are t ₁last message point of electronic mutual inductor or the output of analog input merge cells before moment;

Step (C1), by what obtain in step (A1) and step (B1)

with

calculating frequency is f ₁steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

and this phase difference is converted to the time

Step (D1), calculates the phase calculation point time difference, t ₁moment and t ₁time difference Δ t between the ' moment ₁=t ₁-t ₁';

Step (E1), calculates SV message and sends shake time difference Δ T ₁;

Step (F1), according to what obtain in step (C1), step (D1) and step (E1)

, Δ t ₁with Δ T ₁, calculating frequency is f ₁time delay aperiodic of steady-state simulation amount signal

Step (G1), acquisition frequency is f ₁the full time delay of steady-state simulation amount signal after digitized sampling be .

3. a kind of digitized sampling time delay frequency conversion method of measurement according to claim 2, is characterized in that: step (E1) is calculated SV message and sent shake time difference Δ T ₁process,

Step (a1), adopts Phase Lock Technique to follow the tracks of the transmission frequency of digital quantity SV signal, the equispaced T of locking SV message _sV1;

Step (b1), by SV message K ₁, K ₁-1 time of reception

, calculate K ₁the actual interval of some message and former frame message

;

Step (c1), calculates actual interval

with equispaced T _sV1deviation

Step (d1), by SV message K ₁-1, K ₁-2 times of reception

, calculate K ₁the actual interval of-1 message and former frame message

;

Step (e1), calculates actual interval

with equispaced T _sV1deviation

Step (f1), by K ₁with K ₁the message spacing bias of-1, calculates SV message K ₁the shake time difference that point sends

.

4. a kind of digitized sampling time delay frequency conversion method of measurement according to claim 1, is characterized in that: the process that obtains full time delay in step 4 is,

Step (A2), the frequency of calculating input electronic mutual inductor or analog input merge cells is f ₂steady-state simulation amount signal t ₂the phase place in moment

;

Step (B2), calculates the digital quantity SV signal t of electronic mutual inductor or the output of analog input merge cells ₂the phase place in ' moment

, wherein t ₂'≤t ₂, t ₂a point of corresponding SV message of ' moment, this point is t ₂message point or this point of moment electronic mutual inductor or the output of analog input merge cells are t ₂last message point of electronic mutual inductor or the output of analog input merge cells before moment;

Step (C2), by what obtain in step (A2) and step (B2)

with

calculating frequency is f ₂steady-state simulation amount signal through electronic mutual inductor or the forward and backward phase difference of analog input merge cells

, and this phase difference is converted to the time

;

Step (D2), calculates the phase calculation point time difference, t ₂moment and t ₂time difference Δ t between the ' moment ₂=t ₂-t ₂';

Step (E2), calculates SV message and sends shake time difference Δ T ₂;

Step (F2), according to what obtain in step (C2), step (D2) and step (E2) , Δ t ₂with Δ T ₂, calculating frequency is f ₂time delay aperiodic of steady-state simulation amount signal

Step (G2), acquisition frequency is f ₂the full time delay of steady-state simulation amount signal after digitized sampling be

5. a kind of digitized sampling time delay frequency conversion method of measurement according to claim 4, is characterized in that: step (E2) is calculated SV message and sent shake time difference Δ T ₂process as follows,

Step (a2), adopts Phase Lock Technique to follow the tracks of the transmission frequency of digital quantity SV signal, the equispaced T of locking SV message _sV2;

Step (b2), by SV message K ₂, K ₂-1 time of reception , calculate K ₂the actual interval of some message and former frame message

;

Step (c2), calculates actual interval

with equispaced T _sV2deviation

Step (d2), by SV message K ₂-1, K ₂-2 times of reception , calculate K ₂the actual interval of-1 message and former frame message

Step (e2), calculates actual interval

with equispaced T _sV2deviation

Step (f2), by K ₂with K ₂the message spacing bias of-1, calculates SV message K ₂the shake time difference that point sends

.

6. the measuring system based on a kind of digitized sampling time delay frequency conversion method of measurement claimed in claim 1, is characterized in that: comprise analog output part and gather measure portion;

Described analog output part, for tested electronic mutual inductor or analog input merge cells provide steady-state simulation amount signal, provides the secondary singal of the tested electronic mutual inductor of reflection or the input of analog input merge cells simultaneously for gathering measure portion; In the time of analog output part external connected electronic formula instrument transformer, described analog output part comprises the standard mutual inductor, up-flow/stepup transformer and the frequency-variable controller that connect successively, described standard mutual inductor is as the linkage unit of analog output part and electronic mutual inductor, simultaneously also as analog output part and the linkage unit that gathers measure portion; In the time of the external analog input merge cells of analog output part, described analog output part comprises the power amplifier and the frequency-variable controller that connect successively, described power amplifier is as the linkage unit of analog output part and analog input merge cells, simultaneously also as analog output part and the linkage unit that gathers measure portion;

The secondary singal that described collection measure portion sends in order to gather analog output part, gather the digital quantity SV signal of electronic mutual inductor or the output of analog input merge cells simultaneously, in order to measure and to calculate digitized sampling time delay, the time delay result calculating in order to display measurement, described collection measure portion comprises AD modular converter, internal clocking module, SV gathers and time mark module, measuring and calculating module and result display module, described AD modular converter, SV gathers and is all connected with measuring and calculating module with result display module with time mark module, described internal clocking module is for generation of the sampling pulse of AD modular converter, and for SV gather and time mark module temporal information is provided, described AD modular converter is as the linkage unit of analog output part and collection measure portion, the digital quantity SV signal that described SV gathers and time mark module is exported in order to gather electronic mutual inductor or analog input merge cells.

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