CN203352562U - A high-precision digital phase discriminator for a satellite time-offering frequency-calibrating system - Google Patents
A high-precision digital phase discriminator for a satellite time-offering frequency-calibrating system Download PDFInfo
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- CN203352562U CN203352562U CN 201320357570 CN201320357570U CN203352562U CN 203352562 U CN203352562 U CN 203352562U CN 201320357570 CN201320357570 CN 201320357570 CN 201320357570 U CN201320357570 U CN 201320357570U CN 203352562 U CN203352562 U CN 203352562U
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Abstract
The utility model relates to a high-precision digital phase discriminator for a satellite time-offering frequency-calibrating system. The high-precision digital phase discriminator comprises a power supply circuit, a satellite second signal input circuit, a local second signal input circuit, a symbol determining circuit, a rough measuring counter, a differential delay line circuit, a fine measuring counter, a phase difference synthesis circuit, and a phase difference output circuit. The high-precision digital phase discriminator is capable of well achieving time interval measurement with precision within 0.5ns so as to provide reliable guarantee for high-precision digital phase discriminator precision.
Description
Technical field
The utility model belongs to communication technique field, is specifically related to a kind of high accuracy number phase discriminator for satellite time transfer calibrating frequency system.
Background technology
At present, adopt the clock correction between digital method instrumented satellite signal second and local frequency division signal second, it is the key link of whole satellite time transfer calibrating frequency system data input, realize that in FPGA inside detection that high accuracy differs plays vital effect for the overall performance of system, it is determining the precision of system time service.Realize that in FPGA inside time interval measurement changes also referred to as time figure, be TDC(Time-to-Digital Conversion), method has a lot, but all there are the defects such as certainty of measurement is not high, measuring range is little in the whole bag of tricks, can not meet the needs of high accuracy satellite time service system.
The utility model content
The utility model, for solving the problems of the prior art, provides a kind of high accuracy number phase discriminator for satellite time transfer calibrating frequency system, and it can better realize time interval measurement, thereby provides Reliable guarantee for the raising of time service calibrating frequency precision.
The utility model is achieved by the following technical solutions:
A kind of high accuracy number phase discriminator for satellite time transfer calibrating frequency system, it comprises power circuit, satellite signal input circuit second, local second signal input circuit, symbol decision circuit, rough counter, difference delay line circuit, accurate measurement counter, phase difference combiner circuit and phase difference output circuit.
Described satellite signal input circuit second and a local second signal input circuit are input to the symbol decision circuit by signal, described symbol decision circuit output symbol signal SIGN, anticipating signal START and delay signal STOP; Anticipating signal START and delay signal STOP are input to respectively rough counter and difference delay line circuit simultaneously; The output signal of described mark signal SIGN is input to the phase difference combiner circuit.
The output signal of described rough counter is input to the phase difference combiner circuit; The output signal of described difference delay line circuit is input to the accurate measurement counter, and the output signal of described accurate measurement counter is input to the phase difference combiner circuit; The signal of described phase difference combiner circuit is transferred to again the phase difference output circuit, and power circuit is each circuit part power supply.
Preferably, the LT1936 power supply chip that described power circuit is U.S. Linear Tech.
Preferably, described satellite signal input circuit second is the LEA-5T model GPS receiver that U-blox company releases.
Preferably, the EP2C70 model fpga chip that described difference delay line circuit is U.S. ALTERA company.
Preferably, described accurate measurement counter consists of latching logic circuit and two codimg logic circuit.
The utility model compared with prior art, has following significant advantage:
It can better realize precise time interval measurement and precision of phase discrimination the utility model, thereby provides Reliable guarantee for the raising of time service calibrating frequency precision.
The accompanying drawing explanation
Fig. 1 is principle schematic of the present utility model;
Fig. 2 is each parts annexation of the utility model figure;
Fig. 3 is power circuit diagram of the present utility model.
Embodiment
With reference to the accompanying drawings the utility model embodiment is elaborated.
Referring to Fig. 1, Fig. 2, Fig. 3.
A kind of high accuracy number phase discriminator for satellite time transfer calibrating frequency system of the utility model, it comprises power circuit, satellite signal input circuit second, local second signal input circuit, symbol decision circuit, rough counter, difference delay line circuit, accurate measurement counter, phase difference combiner circuit and phase difference output circuit.As shown in Figure 1.
Described satellite signal input circuit second and a local second signal input circuit are input to the symbol decision circuit by signal, described symbol decision circuit output symbol signal SIGN, anticipating signal START and delay signal STOP; Anticipating signal START and delay signal STOP are input to respectively rough counter and difference delay line circuit simultaneously; The output signal of described mark signal SIGN is input to the phase difference combiner circuit.
The output signal of described rough counter is input to the phase difference combiner circuit; The output signal of described difference delay line circuit is input to the accurate measurement counter, and the output signal of described accurate measurement counter is input to the phase difference combiner circuit; The signal of described phase difference combiner circuit is transferred to again the phase difference output circuit,
Described power circuit is each circuit part power supply, and power circuit adopts the LT1936 power supply chip of U.S. Linear Tech, for system provides reliable 3.3V supply voltage, as shown in Figure 2.Its supply voltage computing formula is as follows: Vo=1.2* (R1/R2+1)=1.2 (17.4/10+1)=3.288V.As shown in Figure 3.
Described satellite signal input circuit second is the LEA-5T model GPS receiver that U-blox company releases, and within its second, the signal output accuracy is ± 50ns, and its pulse per second (PPS) output signal 1pps connects the satellite pulse per second (PPS) input of digital phase discriminator.
Described symbol decision circuit adopts the phase relation between digital method judgement satellite input second signal and local frequency division signal second, and draws mark signal SIGN, anticipating signal START and delay signal STOP.The symbol decision circuit relatively with reference to second and the priority of frequency division pulse per second (PPS) rising edge, using leading pulse per second (PPS) as the START signal, hysteresis as the STOP signal, when satellite second, prior to frequency division during second, the SIGN signal designation is 1, otherwise is 0; The SIGN signal connects the phase place combiner circuit for the synthetic output of phase place, and START and STOP signal connect bigness scale and accurate measurement counter, so that further test.
Described thick side counter is general digit counter, and these parts are responsible for calculating the count value of whole clock cycle.
The EP2C70 model fpga chip that described difference delay line circuit is U.S. ALTERA company, utilize its inner high-speed carry chain structure, realizes high-precision time delay.Every grade of delay can reach 71ps.During customization d type flip flop sampling delay line, for fear of the extra wiring time delay in FPGA inside, guarantee the consistency of time delay between tap, d type flip flop and tap should be constrained in same LE.In order to make d type flip flop energy efficiently sampling, should suitably adjust position and the suitable length that increases delay line that the relative first order tap of sampling clock occurs, the assurance sampling clock is fallen in the effective measuring range of delay line all the time.The actual delay line adopts every 6 grades of taps, postpones 426ps between tap.As shown in Figure 2.
Described accurate measurement counter consists of latching logic circuit and two codimg logic circuit, and it is responsible for the accurate measurement count value of time delay tap characterization being latched and encoding and export to phase place combiner circuit part.
Described phase difference combiner circuit part, be responsible for bigness scale and accurate measurement result are exported according to sign bit is synthetic.Its data output format is 32 signed numbers, output phase difference detection result.The definition of concrete position: the D31-sign bit, 0 for just, and 1 for bearing; D30～D6: rough counter output, precision is 10ns; D5～D0: the output of accurate measurement value, precision is 426ps.
The utility model can provide more precise time interval measurement result and precision of phase discrimination for satellite time transfer calibrating frequency system, for the precision of whole system provides powerful guarantee.
Claims (5)
1. the high accuracy number phase discriminator for satellite time transfer calibrating frequency system, it is characterized in that, it comprises power circuit, satellite signal input circuit second, local second signal input circuit, symbol decision circuit, rough counter, difference delay line circuit, accurate measurement counter, phase difference combiner circuit and phase difference output circuit;
Described satellite signal input circuit second and a local second signal input circuit are input to the symbol decision circuit by signal, described symbol decision circuit output symbol signal SIGN, anticipating signal START and delay signal STOP; Anticipating signal START and delay signal STOP are input to respectively rough counter and difference delay line circuit simultaneously; The output signal of described mark signal SIGN is input to the phase difference combiner circuit;
The output signal of described rough counter is input to the phase difference combiner circuit; The output signal of described difference delay line circuit is input to the accurate measurement counter, and the output signal of described accurate measurement counter is input to the phase difference combiner circuit; The signal of described phase difference combiner circuit is transferred to again the phase difference output circuit, and power circuit is each circuit part power supply.
2. the high accuracy number phase discriminator for satellite time transfer calibrating frequency system as claimed in claim 1, is characterized in that, the LT1936 power supply chip that described power circuit is U.S. Linear Tech.
3. the high accuracy number phase discriminator for satellite time transfer calibrating frequency system as claimed in claim 1, is characterized in that, described satellite signal input circuit second is the LEA-5T model GPS receiver that U-blox company releases.
4. the high accuracy number phase discriminator for satellite time transfer calibrating frequency system as claimed in claim 1, is characterized in that, the EP2C70 model fpga chip that described difference delay line circuit is U.S. ALTERA company.
5. the high accuracy number phase discriminator for satellite time transfer calibrating frequency system as claimed in claim 1, is characterized in that, described accurate measurement counter consists of latching logic circuit and two codimg logic circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320357570 CN203352562U (en) | 2013-06-20 | 2013-06-20 | A high-precision digital phase discriminator for a satellite time-offering frequency-calibrating system |
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| CN 201320357570 CN203352562U (en) | 2013-06-20 | 2013-06-20 | A high-precision digital phase discriminator for a satellite time-offering frequency-calibrating system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109085616A (en) * | 2018-08-30 | 2018-12-25 | 桂林电子科技大学 | A kind of satellite timing method, device and storage medium |
| CN114566948A (en) * | 2022-04-15 | 2022-05-31 | 中国电子科技集团公司第二十四研究所 | Temperature monitoring switching power supply circuit based on diode |
-
2013
- 2013-06-20 CN CN 201320357570 patent/CN203352562U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109085616A (en) * | 2018-08-30 | 2018-12-25 | 桂林电子科技大学 | A kind of satellite timing method, device and storage medium |
| CN114566948A (en) * | 2022-04-15 | 2022-05-31 | 中国电子科技集团公司第二十四研究所 | Temperature monitoring switching power supply circuit based on diode |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131218 Termination date: 20140620 |
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| EXPY | Termination of patent right or utility model |