CN103077123A

CN103077123A - Data writing and reading methods and devices

Info

Publication number: CN103077123A
Application number: CN2013100143265A
Authority: CN
Inventors: 朱建华
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2013-01-15
Filing date: 2013-01-15
Publication date: 2013-05-01

Abstract

The embodiment of the invention provides a data writing method, a data writing device, a data reading method and a data reading device. The data writing method comprises the following steps of: in continuous clock cycles, receiving data to be written into the same shared memory equipment in a plurality of pieces of shared memory equipment from a bus, and caching the data, wherein the length of the data received in each clock cycle is the data bit width of the bus, the data bit widths of the pieces of shared memory equipment are the same, and are k times that of the bus, and k is an integer more than or equal to 2; if the reception of the data to be written into the same shared memory equipment is stopped, merging the cached data according to the data bit width of the shared memory equipment; and transmitting the merged data to arbitration equipment, so that the arbitration equipment writes the merged data into the corresponding shared memory equipment according to preset arbitration rules, wherein the data bit width of the arbitration equipment is the same as that of the shared memory equipment.

Description

A kind of data write and read method and device

Technical field

The present invention relates to data processing technique, relate in particular to a kind of data and write and read method and device, belong to field of computer technology.

Background technology

Along with the development of design with manufacturing technology, the system level chip (System On Chip, SOC) that occurred effectively reducing the electronic product cost of development, shortens the construction cycle.Integrated central processing unit (Central Processing Unit, CPU), data-signal are processed (Digital Signal Processing, DSP) kernel, storer and other specialized functional logic modules among the SoC.Wherein, more intense shared data CPU, DSP kernel and other specialized functional logic intermodules, ageing often are stored in the inner storer (Memory).

SOC also generally includes a shared storage controller, this shared storage controller comprises a plurality of bus interface that are connected with bus, be used for reception and be connected in CPU, DSP kernel and other specialized functional logic modules etc. of bus by the read and write access request of bus transmission, and according to the read and write access request storer is carried out read and write access.Because storer is limited by sequential, storer integrated among the SOC is comprised of a plurality of storeies usually.Wherein, for same storer, only can carry out read and write access by a bus interface at one time.

When a bus interface is carried out read and write access to a storer, other bus interface that need to access this storer need be waited for, therefore, bus interface directly affects the time delay of read-write operation on the read and write access efficient of storer, when the same bus interface was read and write relatively large data continuously to same storer, this delay was particularly evident.

Summary of the invention

For defective of the prior art, the invention provides a kind of data and write and read method and device, in order to improve data read-write efficiency, reduce delay.

First aspect provides a kind of method for writing data, comprising:

Within the continuous clock period, the data of same shared storage device from bus reception and buffer memory a plurality of shared storage devices to be written, the data length that each described clock period receives is the data bit width of described bus, the data bit width of described a plurality of shared storage devices is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2;

If stop to receive the data of described same shared storage device to be written, according to the data bit width of described shared storage device, the data of institute's buffer memory are merged;

Data after merging are sent to arbitration equipment, so that described arbitration equipment writes corresponding shared storage device according to the data of default rules of arbitration after with described merging, the data bit width of described arbitration equipment is identical with described shared storage device.

In the possible implementation of the first of first aspect, described within the continuous clock period, receive the also data of buffer memory same shared storage device to be written from data bus, comprising:

Receive write signal, data-signal and address signal from described bus, described address signal is carried out address decoding, with the address of the shared storage device that is identified for writing the entrained data of described data-signal; And buffer memory is corresponding to the entrained data of the data-signal of the continuous reception of same described address signal.

In conjunction with the possible implementation of the first of first aspect, in the possible implementation of the second of first aspect, described data bit width according to described shared storage device merges the data of institute's buffer memory, comprising:

Judge the address of described shared storage device be used to writing described data, whether align with the data bit width of described shared storage device;

If then in each clock period, according to the data bit width of described shared storage device, the data of institute's buffer memory are merged;

If not, the data bit width that then regulate to be used for the data that write to described shared storage device in the first clock period, merge according to the data bit width after regulating, so that from the second clock cycle, align with the data bit width of described shared storage device in address for the shared storage device that writes described data, and according to the data bit width of described shared storage device, described data are merged.

In conjunction with the possible implementation of the second of first aspect, in the third possible implementation of first aspect, describedly described address signal carried out address decoding comprise:

Be mapped to the addressing mode that interweaves of the address of shared storage device according to bus address, described address signal is carried out address decoding;

Correspondingly, the address of determined shared storage device be used to writing the entrained data of described data-signal is for being alternately distributed the address in different shared storage devices.

The third possible implementation in conjunction with first aspect, in the 4th kind of possible implementation of first aspect, described described address signal is carried out address decoding, before the address with the shared storage device that is identified for writing the entrained data of described data-signal, also comprises:

According to the access conflict of described a plurality of shared storage devices, the addressing mode that described bus address is mapped to the address of shared storage device is configured to continuously addressing or the described addressing that interweaves.

Second aspect provides a kind of method for reading data, comprising:

Data read request according to receiving from bus reads corresponding data from shared storage device, the data length that each clock period reads is the data bit width of described shared storage device;

According to the data bit width of described bus, the described data that read are split and buffer memory;

According to the described clock period, the data communication device of described fractionation is crossed described bus to be sent, wherein the data length that sends is the data bit width of described bus each described clock period, wherein, the data bit width of described shared storage device is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2.

In the possible implementation of the first of second aspect, described basis reads corresponding data from the data read request that bus receives from shared storage device, comprising:

From read signal, data-signal and address signal that described bus receives, the data length to described address signal and the indication of described data-signal carries out address decoding, is identified for reading from described shared storage device the address of corresponding data;

According to the data bit width of described address and described shared storage device, from described shared storage device, read described corresponding data.

In conjunction with the possible implementation of the first of second aspect, in the possible implementation of the second of second aspect, described data bit width according to described address and described shared storage device reads described corresponding data from described shared storage device, comprising:

Judge the start address that reads described corresponding data, whether align with the data bit width of described shared storage device;

If then in each clock period, according to the data bit width of described shared storage device, read described corresponding data from the appropriate address of described shared storage device;

If not, then regulate the first clock period began to read described corresponding data from described start address data bit width, so that from the second clock cycle, reading the address of described corresponding data from described shared storage device aligns with the data bit width of described shared storage device, and according to the data bit width of described shared storage device, read described corresponding data.

In conjunction with the possible implementation of the first of second aspect, in the third possible implementation of second aspect, described data length to described address signal and the indication of described data-signal carries out address decoding, comprising:

Be mapped to the addressing mode that interweaves of the address of shared storage device according to bus address, the data length to described address signal and the indication of described data-signal carries out address decoding;

Correspondingly, determined address for read corresponding data from described shared storage device is for being alternately distributed the address in different shared storage devices.

In conjunction with the third possible implementation of second aspect, in the 4th kind of possible implementation of second aspect, described data length to described address signal and the indication of described data-signal, carry out also comprising before the address decoding:

According to the access conflict of described shared storage device, the addressing mode that described bus address is mapped to the address of shared storage device is configured to continuously addressing or the described addressing that interweaves.

The third aspect provides a kind of data transfer apparatus, comprising:

Receive cache module, be used within the continuous clock period, the data of same shared storage device from bus reception and buffer memory a plurality of shared storage devices to be written, the data length that each described clock period receives is the data bit width of described bus, the data bit width of described a plurality of shared storage devices is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2;

Data merge module, if be used for stopping to receive the data of described same shared storage device to be written, according to the data bit width of described shared storage device, the data of institute's buffer memory are merged;

The data writing module, data after being used for merging are sent to arbitration equipment, so that described arbitration equipment writes corresponding shared storage device according to the data of default rules of arbitration after with described merging, the data bit width of described arbitration equipment is identical with described shared storage device.

In the possible implementation of the first of the third aspect, described reception cache module is used for receiving write signal, data-signal and address signal from described bus, described address signal is carried out address decoding, with the address of the shared storage device that is identified for writing the entrained data of described data-signal; And buffer memory is corresponding to the entrained data of the data-signal of the continuous reception of same described address signal.

In conjunction with the possible implementation of the first of the third aspect, in the possible implementation of the second of the third aspect, described data merge module and are used for:

In conjunction with the possible implementation of the first of the third aspect, in the third possible implementation of the third aspect, described reception cache module is used for:

In conjunction with the third possible implementation of the third aspect, in the 4th kind of possible implementation of the third aspect, also comprise:

The addressing mode configuration module is used for the access conflict according to described a plurality of shared storage devices, and the addressing mode that described bus address is mapped to the address of shared storage device is configured to continuously addressing or the described addressing that interweaves.

Fourth aspect provides a kind of data fetch device, comprising:

Data read module is used for reading corresponding data according to the data read request from the bus reception from shared storage device, and the data length that each clock period reads is the data bit width of described shared storage device;

The Data Division module is used for the data bit width according to described bus, and the described data that read are split and buffer memory;

Data transmitting module, being used for that the data communication device of described fractionation is crossed described bus sends, wherein the data length that sends is the data bit width of described bus each described clock period, wherein, the data bit width of described shared storage device is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2.

In the possible implementation of the first of fourth aspect, described data read module is used for:

In conjunction with the possible implementation of the first of fourth aspect, in the possible implementation of the second of fourth aspect, described data read module is used for:

In conjunction with the possible implementation of the first of fourth aspect, in the third possible implementation of fourth aspect, described data read module is used for:

In conjunction with the third possible implementation of fourth aspect, in the 4th kind of possible implementation of fourth aspect, also comprise:

According to method for writing data provided by the invention and device, since the arbitration equipment that adopts and the data bit width of shared storage device be bus data bit width more than or equal to 2 integral multiple, after the data of the same shared storage device to be written that receives the bus transmission, it is carried out buffer memory, and after the reception of finishing data, merge according to the data bit width of the shared storage device data to institute's buffer memory, so that only utilize the less clock period data after merging can be write shared storage device, thereby effectively reduced the running time of bus interface to shared storage device, improved the data write efficiency, significantly reduced owing to bus interface takies the data manipulation delay that shared storage device causes for a long time.

According to method for reading data provided by the invention and device, since the data bit width of the shared storage device that adopts be bus data bit width more than or equal to 2 integral multiple, according to the data bit width of shared storage device after the data of shared storage device, data bit width according to bus splits and buffer memory it, and transmit one by one by bus by the clock cycle, thereby effectively reduced the running time of bus interface to shared storage device, improved the data write efficiency, significantly reduced owing to bus interface takies the data manipulation delay that shared storage device causes for a long time.

Description of drawings

In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is that the data of the embodiment of the invention write the schematic diagram with a kind of typical application scenarios of read method.

Fig. 2 is the schematic flow sheet of the method for writing data of the embodiment of the invention.

Fig. 3 is the sequential chart of an example of the method for writing data of the application embodiment of the invention.

Fig. 4 is the schematic diagram of an example of the addressing that interweaves of the embodiment of the invention.

Fig. 5 shown in Figure 4 interweaves during addressing mode the sequential chart in multi-bus interface access (data writing or reading out data) same sector address space for using.

Fig. 6 is the schematic flow sheet of the method for reading data of the embodiment of the invention.

Fig. 7 is the structural representation of the data transfer apparatus of the embodiment of the invention.

Fig. 8 is the structural representation of the data fetch device of the embodiment of the invention.

Fig. 9 is the structural representation of another data transfer apparatus of the embodiment of the invention.

Figure 10 is the structural representation of another data fetch device of the embodiment of the invention.

Embodiment

Fig. 1 is that the data of the embodiment of the invention write the schematic diagram with a kind of typical application scenarios of read method.As shown in Figure 1, be integrated with a plurality of bus interface on the shared storage controller, bus interface receive transmit on the bus from CPU, DSP, direct memory access (Direct Memory Access, DMA) or arbitrarily after the read-write requests of other module, by moderator corresponding storer is carried out read operation or write operation.The data of the embodiment of the invention write with read method and are for example carried out by bus interface integrated on the shared storage controller among Fig. 1.The below to be being applied to scene shown in Figure 1, the data of the embodiment of the invention write with read method be elaborated.

Fig. 2 is the schematic flow sheet of the method for writing data of the embodiment of the invention.As shown in Figure 2, this method for writing data comprises:

Step 201, within the continuous clock period, the data of same shared storage device from bus reception and buffer memory a plurality of shared storage devices to be written, the data length that each described clock period receives is the data bit width of described bus, the data bit width of described a plurality of shared storage devices is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2;

Step 202 if stop to receive the data of described same shared storage device to be written, according to the data bit width of described shared storage device, merges the data of institute's buffer memory;

Step 203 is sent to arbitration equipment with the data after merging, so that described arbitration equipment writes corresponding shared storage device according to the data of default rules of arbitration after with described merging, the data bit width of described arbitration equipment is identical with described shared storage device.

Particularly, in the method for writing data of the embodiment of the invention, the application data bit wide is the integral multiple of data bit width of bus and multiple more than or equal to 2 arbitration equipment (for example being moderator) and memory device.Bus interface (for example being the interface 0 among Fig. 1) communicates according to data bit width and the bus of bus, namely receive signal and/or transmit signal to bus from bus, and communicate according to k haplotype data bit wide and the arbitration equipment of bus, with the k haplotype data bit wide according to bus storer is carried out read operation or write operation.

Wherein, data bit width is the figure place (bit) that can transmit data in the clock period, and for example the data bit width of bus is 8bit, and then when bus interface received the data of storer to be written from bus, each clock period received the 8bit data.

Fig. 3 is the sequential chart of an example of the method for writing data of the application embodiment of the invention, in the sequential chart shown in Figure 3,4 times of data bit width take the data bit width of arbitration equipment and storer as bus, and the data length that need write continuously a partial data of same storer is that the data bit width of 4 times of buses is example.For ease of explanation, the data bit width of further supposing bus is 8bit, and the data bit width of arbitration equipment and storer is 32bit, and the length that need write continuously a partial data of same storer is 32bit.

For more easy, clear, write data signal (wdata_s), chip selection signal (cs) and the bus interface of clock signal (clk), output data useful signals (valid), bus transmission only are shown to the write data signal (wdata_d) of arbitration equipment transmission among Fig. 3.Wherein, the valid signal is to be used to indicate the write signal that carries out write operation to storer, and wdata_s is used for transmitting data to be written.In addition, but transfer address signal also on the bus, be used to indicate the bus address that writes corresponding data, so that bus interface is mapped to the addressing mode of the address of shared storage device according to the bus address that presets, described address signal is carried out address decoding, with the address of the shared storage device that is identified for writing the entrained data of write data signal.

As shown in Figure 3, bus interface begins to receive the write data signal that transmits on the bus when receiving the valid signal.Bus interface uses 4 clock period (10ns-30ns) to finish reception and the buffer memory of the serial data of 4 8bit, namely receives ' H0, ' H1, ' H2 and ' H3.Bus interface is after being cached with 4 complete 8bit data, with institute's buffer memory ' H0, ' H1 and ' H2 and ' H3 are merged into the data of a 32bit, i.e. ' H3210 can transmit these synthetic 32bit data to arbitration equipment within 1 clock period.

Bus interface transmitted to arbitration equipment in the clock period of these 32bit data, also sent a chip selection signal to arbitration equipment, so that arbitration equipment writes the indicated storer of this chip selection signal with these 32bit data.Arbitration equipment is according to default rules of arbitration, and whether judge currently has other bus interface the indicated storer of chip selection signal is conducted interviews, if having, then wait, if nothing, then within 1 clock period directly with this 32bit writing data into memory.In addition, when there being simultaneously a plurality of bus interface need same storer is carried out data when writing or reading, arbitration equipment can for example adopt the mode of poll or the mode of Priority-based according to default rules of arbitration, selects the bus interface that each clock period conducts interviews to storer.When arbitration equipment write these 32bit data to storer, because both data bit width is 32bit, therefore a clock period can be finished data and write.

In the prior art, the data bit width of bus, arbitration equipment and storer is all identical, and bus interface sends to arbitration equipment according to the clock period with the data that transmit on the bus, and storer is conducted interviews according to the data that receive by arbitration equipment, therefore for the 32bit data that transmit with 4 clock period on the bus shown in Figure 3, then bus interface need take 4 clock period with its write store.And according to the method for writing data of the embodiment of the invention, only need take 1 clock period can be with the whole write stories of these 32bit data.

In above-described embodiment, describe in conjunction with Fig. 1 institute scene, only be used as an example of the method for writing data of the embodiment of the invention.And the shared storage device in the embodiment of the invention is other memory device arbitrarily, and is not limited to storer shown in Figure 1.

Method for writing data according to the embodiment of the invention, since the arbitration equipment that adopts and the data bit width of shared storage device be bus data bit width more than or equal to 2 integral multiple, after the data of the same shared storage device to be written that receives the bus transmission, it is carried out buffer memory, and after the reception of finishing data, merge according to the data bit width of the shared storage device data to institute's buffer memory, so that only utilize the less clock period data after merging can be write shared storage device, thereby effectively reduced the running time of bus interface to shared storage device, improved the data write efficiency, significantly reduced owing to bus interface takies the data manipulation delay that shared storage device causes for a long time.

And the method for writing data of the embodiment of the invention has been realized in the situation of the data bit width that need not expansion bus, to the raising of data write efficiency.Avoided bringing huge expense owing to the data bit width of expansion bus.

Further, in the method for writing data of above-described embodiment, described data bit width according to described shared storage device merges the data of institute's buffer memory, comprising:

If then in each clock period, according to the data bit width of described shared storage device, described data to be written are write the appropriate address of described shared storage device;

If not, then regulate the first clock period write data bit width from described data to described shared storage device, so that from the second clock cycle, align with the data bit width of described shared storage device in address for the shared storage device that writes described data, and according to the data bit width of described shared storage device, described data are write the appropriate address of described shared storage device.

Particularly, because the data bit width of storer is inconsistent with the data bit width of bus, therefore may there be the address for the shared storage device that writes described data of determining according to bus address, situation about not lining up with the data bit width of storer.The below is elaborated with a concrete example.

For example, the data bit width of bus is 8bit, and the data bit width of storer is 4 times of bus, i.e. 32bit.Use byte (8bit) addressing in storer, i.e. a byte of storer address sensing storer, and byte 0 ~ 3 consists of the storage unit of a 32bit, and byte 4 ~ 7 consists of the storage unit of a 32bit, by that analogy.When need to the byte (address) of storage operation be 0 or 4(or other integral multiple of 4) time, be that the address is when aliging with data bit width, can write or read the content of 4 bytes by single job, when for example byte 0 being pointed in the address, need write the data of 32bit, then carrying out single job can write the 32bit data byte 0-3, takes full advantage of the data bit width of 32bit.If need start address point byte 2(or other integral multiple of non-4 of data writing), be that address and data bit width are when unjustified, then need first byte 2-3 in storage unit corresponding to byte 0-3 to be carried out write operation one time, so that align with data bit width in the address, according to the data bit width of 32bit, remaining data is write successive memory cells again.

Further, in the method for writing data of above-described embodiment, describedly described address signal carried out address decoding comprise:

Particularly, in the embodiment of the invention, the employing addressing mode that interweaves is mapped to bus address the address of shared storage device, refer to continuous bus address is alternately mapped to the address space of different sharing memory device, so that when continuous bus address is conducted interviews, access be different shared storage devices.Fig. 4 is the schematic diagram of an example of the addressing that interweaves of the embodiment of the invention.As shown in Figure 4, (Mem0 shown in Figure 4 and Mem1) interweaves as example take two block storages, wherein, the data bit width of storer is 4 times of bus bit wide, be corresponding 4 bus addresss of each storage unit, satisfy 4m ~ (4m+3), wherein m is that the bus address of even number maps to Mem0, satisfy 4m ~ (4m+3), wherein m is that the bus address of odd number maps to Mem1.In order to clearly show that the mapping mode of this addressing that interweaves, among Fig. 4, be that m is 0 at 0 ~ 3(that each storage unit has identified of Mem0 respectively), 8 ~ 11(is that m is 2), 16 ~ 19(is that m is 4) ..., and be that m is 1 at 4 ~ 7(that each storage unit has identified of Mem1), 12 ~ 15(is that m is 3), 20 ~ 23(is that m is 5) ..., to clearly demonstrate the bus address of its mapping.

Fig. 5 shown in Figure 4 interweaves during addressing mode the sequential chart in multi-bus interface access (data writing or reading out data) same sector address space for using.For more easy, clear, the chip selection signal (slv1_cs1) that 1 couple of Mem1 of chip selection signal (slv1_cs0), bus interface that chip selection signal (slv1_cs) that 1 pair of storer of chip selection signal (slv0_cs1), bus interface that 0 couple of Mem1 of chip selection signal (slv0_cs0), bus interface that 0 couple of Mem0 of chip selection signal (slv0_cs), bus interface that clock signal (clk), 0 pair of storer of bus interface conduct interviews and wait for conducts interviews conducts interviews conducts interviews and wait for and 1 couple of Mem0 of bus interface conduct interviews conducts interviews only is shown among Fig. 3.

As shown in Figure 5, (at clock period T2) need to be to same section continuous bus address simultaneously to suppose bus interface 0 and bus interface 1, for example be 0 ~ 7 to conduct interviews, and the priority of supposing bus interface 0 is higher than bus interface 1, therefore when both access conflicts, bus interface 0 priority access, bus interface 1 is waited for.At clock period T2, because the start address of access is 0, bus address 0 mapping Mem0, so at clock period T2,0 couple of Mem0 of bus interface conducts interviews, 1 clock period has been accessed bus address 0 ~ 3 simultaneously; Because bus address 4 ~ 7 maps to Mem1, so at clock period T3,0 couple of Mem1 of bus interface conducts interviews, this moment, Mem0 was idle, can begin to access Mem0 so bus interface 1 has only been waited for a clock period; At clock period T4,1 couple of Mem1 of bus interface conducts interviews.So far, two bus interface within 3 clock period, have namely been finished to the access of same sector address area 0 ~ 7.

If according to prior art, need the storage area of same access bus address 0 ~ 7 correspondence owing to two bus interface, need take respectively 8 clock period, then need altogether 16 clock period to finish the access of two bus interface.If according to the scheme of the embodiment of the invention shown in Figure 2, because 4 bus addresss of a storage unit mapping of storer, so that the access of same bus interface only need take two clock period, 4 clock period can be finished the access of two bus interface; Further, owing to having adopted the access that can hocket of the addressing mode that interweaves, different bus interface, reduce the stand-by period, so just finished the access of two bus interface 3 clock period.Can find out, adopt the addressing mode that interweaves bus address to be mapped to the address of shared storage device, can further effectively reduce the stand-by period of bus interface when having same section bus address of different bus interface accessing, raising postpones efficient.

Further, at the method for writing data of above-described embodiment, described described address signal is carried out address decoding, before the address with the shared storage device that is identified for writing the entrained data of described data-signal, also comprises:

Particularly, can the situation of lower at the access conflict probability (for example add up conflict number of times or time in a period of time, be lower than predetermined threshold value) under, namely the different bus interface accessing with the probability of a slice address area hour, setting addressing mode be to address continuously; In the situation of access conflict probability higher (for example add up conflict number of times or time in a period of time, surpass predetermined threshold value), when namely the different bus interface accessing was higher with the probability of a slice address area, the setting addressing mode was the addressing that interweaves.In this way, can further improve access efficiency for the access situation.

Fig. 6 is the schematic flow sheet of the method for reading data of the embodiment of the invention.As shown in Figure 6, this method for reading data comprises:

Step 601, the data read request according to receiving from bus reads corresponding data from shared storage device, and the data length that each clock period reads is the data bit width of described shared storage device;

Step 602 according to the data bit width of described bus, splits and buffer memory the described data that read;

Step 603, according to the described clock period, the data communication device of described fractionation is crossed described bus to be sent, wherein the data length that sends is the data bit width of described bus each described clock period, wherein, the data bit width of described shared storage device is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2.

Particularly, similar with the method for writing data of above-described embodiment, in the method for reading data of the embodiment of the invention, the application data bit wide is the integral multiple of data bit width of bus and multiple more than or equal to 2 arbitration equipment (for example being moderator) and memory device.Bus interface (for example being the bus interface 0 among Fig. 1) communicates according to data bit width and the bus of bus, namely receive signal and/or transmit signal to bus from bus, and communicate according to k haplotype data bit wide and the arbitration equipment of bus, with the k haplotype data bit wide according to bus storer is carried out read operation or write operation.

In this method for reading data, the performed class of operation of bus interface is similar to the inverse process that operates in the method for writing data of above-described embodiment.Still take the data bit width of bus as 8bit, the data bit width of storer is 32bit, and the required data length that reads is that 32bit is example, then bus interface takies 1 clock period reads the data of required 32bit from storer after, it is split as 4 8bit data, these 4 8bit data are carried out buffer memory, and take 4 clock period and send it to the relevant device of initiating read request, such as CPU, DSP etc. by bus.

If in the prior art, the data bit width of storer is identical with bus, and when being 8bit, then bus interface need take 4 clock period read out 32bit from storer data.And according to the method for reading data of the embodiment of the invention, only need take 1 clock period these 32bit data can be read.

Method for reading data according to the embodiment of the invention, since the data bit width of the shared storage device that adopts be bus data bit width more than or equal to 2 integral multiple, according to the data bit width of shared storage device after the data of shared storage device, data bit width according to bus splits and buffer memory it, and transmit one by one by bus by the clock cycle, thereby effectively reduced the running time of bus interface to shared storage device, improved the data write efficiency, significantly reduced owing to bus interface takies the data manipulation delay that shared storage device causes for a long time.

And the method for reading data of the embodiment of the invention has been realized in the situation of the data bit width that need not expansion bus, to the raising of data reading efficiency.Avoided bringing huge expense owing to the data bit width of expansion bus.

Further, in the method for reading data of above-described embodiment, described basis reads corresponding data from the data read request that bus receives from shared storage device, comprising:

Wherein, write similarly with data, bus interface also sends chip selection signal to arbitration equipment after finishing address decoding, with indication read signal from corresponding memory device.Arbitration equipment receives that arbitration operation performed behind the chip selection signal is identical with data writing process, repeats no more herein.

Further, in the method for reading data of above-described embodiment, described data bit width according to described address and described shared storage device reads described corresponding data from described shared storage device, comprising:

Particularly, the above-mentioned process of being alignd with data bit width in the address, identical with data writing process, so locate to repeat no more.

Further, in the method for reading data of above-described embodiment, described data length to described address signal and the indication of described data-signal carries out address decoding, comprising:

Particularly, the above-mentioned addressing mode that interweaves, and when adopting the mode of the addressing that interweaves that bus address is mapped to the address of shared storage device, bus address is to operating process, the effect of storer, identical with the method for writing data of above-described embodiment, so locate to repeat no more.

Method for reading data according to above-described embodiment, the employing addressing mode that interweaves is mapped to bus address the address of shared storage device, can when having same section bus address of different bus interface accessing, further effectively reduce the stand-by period of bus interface, improve delay efficient.

Further, in the method for reading data of above-described embodiment, described data length to described address signal and the indication of described data-signal, carry out also comprising before the address decoding:

In this way, can further improve access efficiency for the access situation.

Fig. 7 is the structural representation of the data transfer apparatus of the embodiment of the invention.As shown in Figure 7, this data transfer apparatus 70 comprises:

Receive cache module 71, be used within the continuous clock period, the data of same shared storage device from bus reception and buffer memory a plurality of shared storage devices to be written, the data length that each described clock period receives is the data bit width of described bus, the data bit width of described a plurality of shared storage devices is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2;

Data merge module 72, if be used for stopping to receive the data of described same shared storage device to be written, according to the data bit width of described shared storage device, the data of institute's buffer memory are merged;

Data writing module 73, data after being used for merging are sent to arbitration equipment, so that described arbitration equipment writes corresponding shared storage device according to the data of default rules of arbitration after with described merging, the data bit width of described arbitration equipment is identical with described shared storage device.

The data transfer apparatus of above-described embodiment for example is the bus interface among the said method embodiment.In addition, on hardware was realized, above each module all can adopt processor to realize, and, receiving cache module and also can comprise storer and receiver, the data writing module also can comprise transmitter etc., the embodiment of the invention is in this no longer any restriction.

The idiographic flow that the data transfer apparatus executing data of above-described embodiment writes, identical with the method for writing data of above-described embodiment, so locate to repeat no more.

Data transfer apparatus according to the embodiment of the invention, since the arbitration equipment that adopts and the data bit width of shared storage device be bus data bit width more than or equal to 2 integral multiple, after the data of the same shared storage device to be written that receives the bus transmission, it is carried out buffer memory, and after the reception of finishing data, merge according to the data bit width of the shared storage device data to institute's buffer memory, so that only utilize the less clock period data after merging can be write shared storage device, thereby effectively reduced the running time of bus interface to shared storage device, improved the data write efficiency, significantly reduced owing to bus interface takies the data manipulation delay that shared storage device causes for a long time.

Further, in the data transfer apparatus of above-described embodiment, described reception cache module is used for receiving write signal, data-signal and address signal from described bus, described address signal is carried out address decoding, with the address of the shared storage device that is identified for writing the entrained data of described data-signal; And buffer memory is corresponding to the entrained data of the data-signal of the continuous reception of same described address signal.

Further, in the data transfer apparatus of above-described embodiment, described data merge module and are used for:

Further, in the data transfer apparatus of above-described embodiment, described reception cache module is used for:

Further, in the data transfer apparatus of above-described embodiment, also comprise:

Fig. 8 is the structural representation of the data fetch device of the embodiment of the invention.As shown in Figure 8, this data fetch device 80 comprises:

Data read module 81 is used for reading corresponding data according to the data read request from the bus reception from shared storage device, and the data length that each clock period reads is the data bit width of described shared storage device;

Data Division module 82 is used for the data bit width according to described bus, and the described data that read are split and buffer memory;

Data transmitting module 83, being used for that the data communication device of described fractionation is crossed described bus sends, wherein the data length that sends is the data bit width of described bus each described clock period, wherein, the data bit width of described shared storage device is identical, and be described bus data bit width k doubly, k is the integer more than or equal to 2.

The data fetch device of above-described embodiment for example is the bus interface among the said method embodiment.In addition, on hardware is realized, data read module and Data Division module all can adopt processor to realize, data transmitting module can adopt transmitter to realize, and, data read module also can comprise receiver, and the Data Division module also can comprise storer etc., and the embodiment of the invention is in this no longer any restriction.

The idiographic flow that the data fetch device executing data of above-described embodiment reads, identical with the method for reading data of above-described embodiment, so locate to repeat no more.

Data fetch device according to the embodiment of the invention, since the data bit width of the shared storage device that adopts be bus data bit width more than or equal to 2 integral multiple, according to the data bit width of shared storage device after the data of shared storage device, data bit width according to bus splits and buffer memory it, and transmit one by one by bus by the clock cycle, thereby effectively reduced the running time of bus interface to shared storage device, improved the data write efficiency, significantly reduced owing to bus interface takies the data manipulation delay that shared storage device causes for a long time.

Further, in the data fetch device of above-described embodiment, described data read module is used for:

Further, in the data fetch device of above-described embodiment, also comprise:

Fig. 9 is the structural representation of another data transfer apparatus of the embodiment of the invention.As shown in Figure 9, this data transfer apparatus 90 comprises storer 91 and the processor 92 that is connected with storer, wherein: and storage batch processing code in the storer 91, and processor 92 is used for carrying out following the operation for the program code that calls storer 91 storages:

Further, in the data transfer apparatus of above-described embodiment, described processor also is used for calling the program code that storer is stored, receive write signal, data-signal and address signal from described bus, described address signal is carried out address decoding, with the address of the shared storage device that is identified for writing the entrained data of described data-signal; And buffer memory is corresponding to the entrained data of the data-signal of the continuous reception of same described address signal.

Further, in the data transfer apparatus of above-described embodiment, described processor also is used for calling the program code that storer is stored, and carries out following operation:

Figure 10 is the structural representation of another data fetch device of the embodiment of the invention.As shown in figure 10, this data fetch device 100 comprises storer 101 and the processor 102 that is connected with storer, wherein: storage batch processing code in the storer 101, and processor 102 is used for carrying out following the operation for the program code that calls storer 101 storages:

Further, in the data fetch device of above-described embodiment, described processor also is used for calling the program code that storer is stored, and carries out following operation:

One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can be finished by the relevant hardware of programmed instruction.Aforesaid program can be stored in the computer read/write memory medium.This program is carried out the step that comprises above-mentioned each embodiment of the method when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.

It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims

1. a method for writing data is characterized in that, comprising:

2. method for writing data according to claim 1 is characterized in that, and is described within the continuous clock period, receives the also data of buffer memory same shared storage device to be written from data bus, comprising:

3. method for writing data according to claim 2 is characterized in that, described data bit width according to described shared storage device merges the data of institute's buffer memory, comprising:

4. method for writing data according to claim 2 is characterized in that, describedly described address signal is carried out address decoding comprises:

5. method for writing data claimed in claim 4 is characterized in that, described described address signal is carried out address decoding, before the address with the shared storage device that is identified for writing the entrained data of described data-signal, also comprises:

6. a method for reading data is characterized in that, comprising:

7. method for reading data according to claim 6 is characterized in that, described basis reads corresponding data from the data read request that bus receives from shared storage device, comprising:

8. method for reading data according to claim 7 is characterized in that, described data bit width according to described address and described shared storage device reads described corresponding data from described shared storage device, comprising:

9. method for reading data according to claim 7 is characterized in that, described data length to described address signal and the indication of described data-signal carries out address decoding, comprising:

10. method for reading data according to claim 9 is characterized in that, described data length to described address signal and the indication of described data-signal carries out also comprising before the address decoding:

11. a data transfer apparatus is characterized in that, comprising:

12. data transfer apparatus according to claim 11, it is characterized in that, described reception cache module is used for receiving write signal, data-signal and address signal from described bus, described address signal is carried out address decoding, with the address of the shared storage device that is identified for writing the entrained data of described data-signal; And buffer memory is corresponding to the entrained data of the data-signal of the continuous reception of same described address signal.

13. data transfer apparatus according to claim 12 is characterized in that, described data merge module and are used for:

14. data transfer apparatus according to claim 12 is characterized in that, described reception cache module is used for:

15. data transfer apparatus according to claim 14 is characterized in that, also comprises:

16. a data fetch device is characterized in that, comprising:

17. data fetch device according to claim 16 is characterized in that, described data read module is used for:

18. data fetch device according to claim 17 is characterized in that, described data read module is used for:

19. data fetch device according to claim 17 is characterized in that, described data read module is used for:

20. data fetch device according to claim 19 is characterized in that, also comprises: