CN100538738C - Method, the Apparatus and system of the poly-dimensional block data in the visit multiple zone memory - Google Patents
Method, the Apparatus and system of the poly-dimensional block data in the visit multiple zone memory Download PDFInfo
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Abstract
The invention discloses a kind of method of visiting multiple zone memory, comprising:, then visit multiple zone memory and process ends by the memory address of current data row if (a) the current data row is last column of poly-dimensional block data; If current data is capable is not last column of poly-dimensional block data, calculates the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of current data row; (b) by the current data line data of the poly-dimensional block data in the memory address of the current data row visit multiple zone memory; (c) be provided with by the capable state of pre-defined rule according to the capable address relation of a plurality of follow-up datas, and/or the capable state of the corresponding stored row of current data row is provided with the capable corresponding stored row of follow-up data; (d) after being set at the current data row, the next data line of current data row returns step (a).The invention also discloses equipment and system simultaneously based on this method.
Description
Technical field
The present invention relates to data storage technology, relate in particular to a kind of technology of visiting multiple zone memory, more specifically, the present invention aims to provide a kind of method, equipment and system thereof that improves the multiple zone memory bandwidth.
Background technology
Communication and digital media processing need a large amount of memory accesses.Network processing system, image processing system etc. are more and more higher to the demand of memory bandwidth.
Image processing system is used to finish pre-service, aftertreatment, image compression encoding and decoding, image display process, the 2D/3D graphic presentation processing of static and dynamic image etc.Wherein common compression of images encoding and decoding standard comprises JPEG, JPEG2000, MPEG2, MPEG4, H.263, H.264 wait.Generally need a large amount of buffer memory graphic image datas in the image processing process, very big to the visit data amount of storer, require high bandwidth, low delay.Therefore the bandwidth of storer becomes the performance bottleneck of image processing system.
Video, promptly dynamic image is to be made of continuous a series of images frame of time.One two field picture is formed (least unit that pixel is image) by the pixel of two-dimensional array.In video coding usually with macro block as base conditioning unit, a macro block is 16 * 16 pixels.For interlaced scanning system, a picture frame is formed by strange and even.The image data file form is RGB and YCbCr two big classes, and the latter can be divided into different-formats such as 4:2:0,4:2:2,4:4:4 again.Usually three components of YCbCr are deposited respectively, and each component is again by successively all line data being left in one section continuous storage unit in proper order.Each two dimensional image is corresponding to one or more memory cell blocks like this.
Dynamic storage (DRAM), that common is SDRAM and DDR SDRAM, big with capacity, cost is low, advantages such as connected reference Time Bandwidth height obtain widespread use in image processor.DRAM has a plurality of districts (Bank) usually, every Bank has a plurality of storage lines (Row), and every storage line has multiple row (Column), is divided into 4Bank as a monolithic 32Meg x 16 DDR SDRAM storeies, every Bank has the 8K storage line, and each storage line has 1024 memory rows.The unit of the each visit of dynamic storage is a secondary burst (Burst), and the length of Burst is configurable, as can be 4,8 even 256.Dynamic storage is because the restriction of device self character, each burst access at random needs Active (" activation "), Precharge expenses such as (" precharge " or " closing ") usually, only run into row that the next one will deposit be opened capable just the time, just can remove this expense from.Dynamic storage is a kind of many Bank storer.
In the prior art, generally all be that the form with forms data or one-dimensional data conducts interviews to storer (for example DRAM).With the Flame Image Process is example, if store piece image in storer, common way is that piece image is divided into a plurality of one-dimensional datas is capable, writes in the middle of the storer line by line then.With reference to figure 1, illustrate the part flow process of visit many Bank storer (for example DRAM) in the prior art.As shown in the figure, step 10:Active a0 Bank b0 is capable; Step 11: the capable c0 row of read/write a0Bank b0; Step 12:Precharge; Step 13:Active a0 Bank b1 is capable; Step 14: the capable c1 row of read/write a0Bank b1; Step 15:Precharge.As can be seen, the write operation of each data line image all will pass through the last memory lines of having opened of first Precharge, the current row that will operate of Active again, and then image line write in the middle of the storer.Only run into row that the next one will deposit be opened capable just the time, the expense that just can remove Precharge and Active from, but this probability is very little, randomness is very big.So, thereby the technology of existing one-dimensional data reference-to storage is because the one dimension access stencil can't avoid Precharge/Active expense frequent in access process to cause improving the bandwidth availability ratio of many Bank storer.
During to graph and image processing, need carry out a large amount of multidimensional data block access, according to existing technology, can only be by being divided into a plurality of one dimensions even a lot of individual character data accesses, the memory bandwidth utilization factor is very low, becomes the performance bottleneck of graph and image processing.
Summary of the invention
The objective of the invention is to, a kind of method, Apparatus and system of visiting multiple zone memory is provided, effectively improve the bandwidth availability ratio of multiple zone memory.
In order to reach above-mentioned technical purpose, one aspect of the present invention provides a kind of method of visiting multiple zone memory, this method comprises: if (a) the current data row is last column of described poly-dimensional block data, then visit the current data line data of the poly-dimensional block data in the described multiple zone memory by the memory address of described current data row, and process ends; If current data is capable is not last column of described poly-dimensional block data, calculates the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row; (b) visit the current data line data of the poly-dimensional block data in the described multiple zone memory by the memory address of described current data row; (c) be provided with by the capable state of pre-defined rule according to the capable address relation of described a plurality of follow-up datas, and/or the capable state of the corresponding stored row of current data row is provided with the capable corresponding stored row of follow-up data; (d) after being set at the current data row, the next data line of current data row returns step (a).
Preferably, described multiple zone memory is DRAM or SDRAM or DDR SDRAM or DDR2SDRAM or RLDRAM or FCRAM.
Preferably, described multidimensional data format information is 2 dimension data format informations.
Preferably, described step (c) is: the position relation according to the capable memory address of described follow-up data judges whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row, if then activate capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row in advance.
Correspondingly, the present invention provides a kind of multidimensional store access controller of visiting multiple zone memory on the other hand, comprising: judge and finish device, be used to judge if the current data row is last column of poly-dimensional block data, finish after then calling access means, otherwise the call address mapper; Access means is used for sending the command sequence of visiting described multiple zone memory by the memory address of described current data row; Address mapper is used for calculating the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row; The memory line states setting device, be used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the capable address relation of described a plurality of follow-up datas, if, then activate the capable corresponding stored row of follow-up data in advance, and/or auto-precharge current data row corresponding stored row; The device that goes forward one by one is used for the next data line of current data row is set at the current data row.Data Generator, the command sequence that is used for sending according to described access means is sent interrogation signal, is write out or readback data to described multiple zone memory;
Preferably, described memory line states setting device comprises: judgment means is used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the position relation of the capable memory address of described follow-up data; Active device is used for activating in advance the capable corresponding stored row of follow-up data; The auto-precharge device is used for auto-precharge current data row corresponding stored row.
Another aspect of the invention provides a kind of multiport storage controller of visiting multiple zone memory, comprising: a plurality of bus interface modules comprise at least one multidimensional data bus interface module and at least one common status bus interface module; Moderator couples with described a plurality of bus interface modules, is used for selecting a multidimensional data bus interface module or a common status bus interface module at described a plurality of bus interface modules; The store access controller group couples with described moderator, is used to provide memory access control; MUX couples with described store access controller group, is used for selecting a multidimensional store access controller or a generic access controller in described store access controller group.Wherein said store access controller group comprises: the generic access controller is used to provide the access control to one-dimensional data; The multidimensional store access controller is used to provide the access control to multidimensional data; Wherein said multidimensional store access controller comprises: judge to finish device, is used to judge, finish after then calling access means if the current data row is last column of poly-dimensional block data, otherwise the call address mapper; Access means is used for sending the command sequence of visiting described multiple zone memory by the memory address of described current data row; Address mapper is used for calculating the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row; The memory line states setting device is used for being provided with by the capable state of pre-defined rule to capable corresponding stored row of follow-up data and/or current data row corresponding stored row according to the capable address relation of described a plurality of follow-up datas; The device that goes forward one by one is used for the next data line of current data row is set at the current data row.Data Generator, the command sequence that is used for sending according to described access means is sent interrogation signal, is write out or readback data to described multiple zone memory;
Alternatively, also comprise the bit width conversion device that couples with described bus interface module, the low-bit width data-switching that is used for receiving from the outside becomes to be sent to after the high-bit width data and will be sent to the outside after described bus interface module maybe will become the low-bit width data from the high-bit width data-switching that bus interface module receives.
Preferably, described bus is ahb bus or the AXI bus in the AMBA bus.
Preferably, described memory line states setting device comprises: judgment means is used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the position relation of the capable memory address of described follow-up data; Active device is used for activating in advance the capable corresponding stored row of follow-up data; The auto-precharge device is used for auto-precharge current data row corresponding stored row.
Another aspect of the invention provides a kind of information handling system, comprising: message handler, as the source device of access data; With the bus that described message handler couples, be used to transmit data; With the multiport storage controller that described bus couples, be used for the storage of control data; With the memory controller PLIM that described multiport storage controller couples, be used for converting the input and output digital signal of described multiport storage controller to multiple zone memory desired physical signalling; Multiple zone memory with described storage controller interface physical layer block couples is used to store data; Wherein said multiport storage controller comprises: a plurality of bus interface modules comprise at least one multidimensional data bus interface module and at least one common status bus interface module; Moderator couples with described a plurality of bus interface modules, is used for selecting a multidimensional data bus interface module or a common status bus interface module at described a plurality of bus interface modules; The store access controller group couples with described moderator, is used to provide memory access control; MUX couples with described store access controller group, is used for selecting a multidimensional store access controller or a generic access controller in described store access controller group.Wherein said store access controller group comprises: the generic access controller is used to provide the access control to one-dimensional data; The multidimensional store access controller is used to provide the access control to multidimensional data; Wherein said multidimensional store access controller comprises: judge to finish device, is used to judge, finish after then calling access means if the current data row is last column of poly-dimensional block data, otherwise the call address mapper; Access means is used for sending the command sequence of visiting described multiple zone memory by the memory address of described current data row; Address mapper is used for calculating the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row; The memory line states setting device is used for being provided with by the capable state of pre-defined rule to capable corresponding stored row of follow-up data and/or current data row corresponding stored row according to the capable address relation of described a plurality of follow-up datas; The device that goes forward one by one is used for the next data line of current data row is set at the current data row; Data Generator, the command sequence that is used for sending according to described access means is sent interrogation signal, is write out or readback data to described multiple zone memory.
Preferably, described memory line states setting device comprises: judgment means is used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the position relation of the capable memory address of described follow-up data; Active device is used for activating in advance the capable corresponding stored row of follow-up data; The auto-precharge device is used for auto-precharge current data row corresponding stored row.
Implement the present invention, have following beneficial effect:
The method of visit multiple zone memory provided by the invention, memory address and multidimensional data format information (these multidimensional data format informations comprise dimensional information such as length) according to data line to be visited calculate the capable memory address of follow-up data that will visit in advance, the distribution situation of the memory address that the follow-up data that calculates in advance in the visit gap of data line basis is capable, whether decision is provided with these memory line states, thereby the optimization command sequence has improved the access efficiency of storer.For example in multiple zone memory, activate capable corresponding stored row of follow-up data or the auto-precharge current data row corresponding stored row that to visit in advance.Multidimensional data can include but not limited to rectangle, rhombus, cube etc.This method will be used widely in a plurality of fields such as Streaming Media, video, encoding and decoding.There are many storage operations at multidimensional data in these fields, memory access etc. as two dimension, 3-D view, these data are easy to form multidimensional data, if the method for mentioning among use the present invention is stored and is visited, will greatly improve the bandwidth of memory access, solve the memory bandwidth bottleneck problem that present field of media exists.
Description of drawings
Fig. 1 is the part process flow diagram of the method for visit multiple zone memory in the prior art;
Fig. 2 is the structural representation of a kind of information handling system provided by the invention;
Fig. 3 is the structural representation of a kind of multiport storage controller provided by the invention;
Fig. 4 is the structural representation of a kind of multidimensional store access controller provided by the invention;
Fig. 5 is the address budget and the mapping principle block diagram of the address mapper in the multidimensional store access controller that provides among Fig. 4;
A kind of process flow diagram of visiting the method for multiple zone memory of the multidimensional store access controller that provides among Fig. 4 is provided Fig. 6;
Fig. 7 is the bit width conversion synoptic diagram.
Embodiment
With reference to figure 2, illustrate a kind of information handling system provided by the invention, this information handling system can be an a kind of graph and image processing system.As shown in the figure, system 200 comprises message handler 210, bus 220, multiport storage controller 300, memory controller PLIM 301 and many Bank storer 230.
Message handler 210 is source devices of access data, can have a plurality ofly, comprises the message handler (for example video compression decoder of hardware circuit) of CPU (central processing unit) and/or hardware logic.
Bus 220 is the equipment of link information processor 210 and multiport storage controller 300, is used to transmit data.Described bus 220 can comprise uses multiple prior art system bus system, for example the PLB bus of the ahb bus (Advanced High-performance Bus) in the AMBA bus of ARM company definition or its upgraded version AXI bus, IBM Corporation's definition etc.Bus 220 can comprise multiple bus, and among the present invention, bus 220 comprises a bus that can transmit poly-dimensional block data at least.
Memory controller PLIM (PHY) 301 is used for converting the input and output digital signal (containing clock) of multiport storage controller 300 to many Bank storer 230 desired physical signallings.Typical in finishing the desired SSTL2 level signal of DDR SDRAM.Described message handler 210 can be by bus 220 and multiport storage controller 300 many Bank of visit storeies 230.Described visit comprise from described many Bank storer 230 reading of data and in described many Bank storer 230 write data, and described many Bank storer 230 carried out command configuration etc.
Described many Bank storer 230 can be the storer that on-board dram (dynamic RAM) or SDRAM (dynamic synchronous random reference-to storage) or DDR SDRAM (Double Data Rate dynamic synchronous random reference-to storage) or DDR2SDRAM (the 2nd generation Double Data Rate dynamic synchronous random reference-to storage) or RLDRAM (the low dynamic synchronous random reference-to storage that postpones) or FCRAM (random access storage device fast circulates) etc. have many Bank (bank) characteristic.Described many Bank storer 230 can with described multiport storage controller 300 on same chip, also can be independent storage chip.
With reference to figure 3, described multiport storage controller 300 comprises a plurality of bus interface modules, in the present embodiment be two, be respectively AHB interface module 321 and video high performance bus (VAHB) interface module 322 that is used to transmit multidimensional data, can also be a plurality of bus interface modules in actual applications.Described multiport storage controller 300 also comprises the moderator 330 that couples with described a plurality of bus interface modules; The store access controller group 340 that couples with described moderator 330; The MUX 350 that couples with described store access controller group 340.
Described store access controller group 340 comprises generic access controller 343 and multidimensional store access controller 400, certainly, also comprises the refresh unit 342 and the initialization unit 341 that couple with described generic access controller 343 and multidimensional store access controller 400.Wherein, described generic access controller 343 is exactly that common store access controller of the prior art (is compared with described multidimensional store access controller 400, the visit of generic access controller 343 control flat addresss), its control principle is well known to those of ordinary skill in the art, does not repeat them here.Described AHB interface module 321 also is of the prior art, and use matches with generic access controller 343.That is to say that in this preferred embodiment, this multiport storage controller has two bus interface modules and two store access controllers.AHB interface module 321 is used with generic access controller 343; VAHB interface module 322 is used with multidimensional store access controller 400.But above-mentioned two group access equipment can timesharing be visited same many Bank storer (for example many Bank storer 230).Could but how generic access controller 343 and multidimensional store access controller 400 visit same storer? at first the bus that will solve memory side is seized problem.Present embodiment carries out bus arbitration by the method for fair poll, and what make two controllers can time-sharing multiplex to taking of bus.Described moderator 330 and MUX 350 promptly are to realize above-mentioned arbitration function.To solve the problem of map addresses then.If the inconsistent words of the map addresses of two controllers rule, these two kinds of buses just can not be visited data each other mutually so.So present embodiment has been unified the mapping ruler of these two controllers on macroscopic view, two controllers all carry out map addresses according to the order of row, Bank, row exactly, though the data of VAHB interface module 322 are multidimensional operations like this, the data of AHB interface module 321 are one dimension operations, but still can visit data each other mutually.Therefore, present embodiment can realize that a plurality of controller timesharing control same storer, and has realized that the mixing of polytype data bus transmits.
The design of described VAHB interface module 322 is based on the modification that standard A HB interface is done.In order to transmit the ahb bus of multidimensional data and energy compatible universal, present embodiment has carried out special agreement to the address of special-purpose multidimensional bus.Special-purpose multidimensional bus has kept all interface signals of ahb bus, comprises read data (HRDATA), write data (HWDATA), address (HADDR), back-pressure signal (HREADY), transport-type (HTRANS) and transmission size signals such as (HSIZE).It is unique that what done to change is exactly the content of address, promptly with address information be transmitted except address to be visited, also have the multidimensional data format information.In system, described data address to be visited and multidimensional data format information can be integrated into a new information.Be example explanation integration process below with the 2-D data.For example be that 0x300 and length are 4 row with an address to be visited, wide is 5 capable, and memory address is divided into 0 2-D data format information in the ranks and combines.If the address assignment of described VAHB interface module 322 such as following table:
| Bit | Implication |
| [31:28] | The line number m of two-dimensional block |
| [27:24] | The columns n of two-dimensional block |
| [23:21] | The memory address between-line spacing |
| [20:0] | The two-dimensional block first address |
Information after then integrating is: 0x45000300.Length and width, first address and the memory address line space information of two-dimensional blocks of data have been provided in this information.These information will be in follow-up being used in the processing of described multidimensional store access controller 400.Because provided length and width, first address and the memory address line space information of two-dimensional blocks of data in this information, the address of back does not just need to increase progressively one by one as the AHB interface, can remain unchanged.In addition, 322 needs of described VAHB interface module are used this a kind of transport-type of INCR (random length transmission).In addition, the AHB interface operation of the operation of VAHB interface module 322 and standard is the same, has kept the compatibility with ahb bus.When line number m=1, what VAHB interface module 322 was transmitted is one-dimensional data, identical with the AHB interface.
With reference to figure 4, described multidimensional store access controller 400 comprises address mapper 410, control state machine 420 and Data Generator 430.Described address mapper 410 is used to receive the information (for example above-mentioned 0x45000300) of multidimensional (for example two dimension) data format information that come from integration that described VAHB interface module 322 sends and address to be visited, and to memory address (for example above-mentioned 0x300) and dimensional information (for example above-mentioned 4 row 5 row of this information by the current data row that in this information, carries, memory address between-line spacing 0) calculate the capable address of a plurality of follow-up datas in advance by mapping ruler, Budget Principle as shown in Figure 5.In the present embodiment, described address mapper 410 can be calculated down the address of two row in advance, add the address of current data row, the address that has three data lines is sent to described control state machine 420 and sentences for the control that conducts interviews of this control state machine 420, and specifically control law will describe in detail below.It should be noted that the 2-D data here might not be that storage line is visited many Bank storer 230 one by one, also can or stride any storage line, therefore have memory address between-line spacing parameter every storage line.The next line address can obtain according to the memory address and the budget of memory address between-line spacing of current data row: the first memory address of the n data line=first memory address of n-1 data line+memory address between-line spacing.410 pairs of address mapping rulers of described address mapper are also optimized.Common map addresses is to run through behind the storage line of this Bank at once then read next storage line, so just can't avoid Active and Precharge expense, and the map addresses rule of described address mapper 410 is: the storage line that directly forwards next Bank after a row access finishes to, rather than forward the next storage line of this Bank to, because that visit is not same Bank, Precharge at once so just, just can directly visit the storage line of next Bank, the visit of the storage line of current Bank then can be offset the Precharge expense in the read-write of next Bank storage line by being provided with of automatic Precharge, thereby improves the access efficiency of storer.
With reference to figure 5, described control state machine 420 receives a plurality of data lines address of coming from described address mapper 410 and calculating in advance (be the memory address of current data row and with the subsequent rows address of the current data standard of behaviour), memory address with the current data row is that benchmark can be decided next data line memory address and following two data line memory addresss (can also many calculate some data lines in advance certainly), carries out read control in conjunction with the read that sends from described VAHB interface module 322.In conjunction with Fig. 3, in Fig. 3, described multidimensional store access controller 400 is connected with initialization apparatus 214 with refreshing a device 213.Wherein, the initialization OK signal of the refresh signal of described refreshing a device 213 and initialization apparatus 214 is input signals of described control state machine 420.Described refreshing a device 213 is used to refresh the data and the order of multidimensional store access controller 400 and generic access controller 343, and described initialization apparatus 214 then is used for the described multidimensional store access controller 400 of initialization and generic access controller 343.Corresponding, control state machine 420 also has the outwards back-pressure signal of output, is used to notify the external world all set (Ready).
With reference to figure 6, illustrate the process flow diagram that described multidimensional store access controller 400 carries out read control.As shown in the figure, establishing n is the current data row, and this flow process comprises:
Step 600: judge that whether n data line (being the current data row) is last column of poly-dimensional block data to be visited, if then execution in step 601; If not last column, then execution in step 602;
Step 601: visit the n data line, process ends;
Step 602: the memory address of calculating n+1 data line and n+2 data line in advance; (this step is carried out by described address mapper 410, and follow-up program is carried out by control state machine 420 controls)
Step 603: visit the n data line, promptly visit the current data row;
This visit is gone to memory controller PLIM side (PHY) the command sequence control signal of Data Generator 430 and address mapper 410 with generation and is gone to the command signal of many Bank storer 230.The signal of going to Data Generator 430 be designation data maker 430 to many Bank storer 230 write datas or from many Bank storer 230 sense data, the signal of going to address mapper 410 continues to send to control state machine 420 operations such as budget addresses for the indication address mapper;
Step 604: if n+1 data line memory address and n+2 data line memory address are changeed step 608 after not at same Bank, then entering in the step 605 automatically Precharge n data line corresponding stored row and Active n+2 data line corresponding stored row; Otherwise change step 606;
This step is in fact after having visited the n data line, the n+1 data line is that the next line of current data row is about to become the current data row, at this moment owing to predicted the memory address of n+1 data line and n+2 data line (being following two data lines of current data row), whether the memory address that can judge these two data lines is in same Bank, if not at same Bank, but storage line with regard to Active n+2 data line correspondence, and the storage line of automatic Precharge n data line correspondence, for the n+1 data line, before also not visiting it, storage line that just may its next data line correspondence of Active, that is to say, for a multidimensional data block access, need the Bank of its memory address correspondence of independent Active during except first data line visit, all the other each data line memory address place Bank all might do not have accessed before just by Active, and the Precharge of each storage line operation also can be placed on and operates between the every trade conversion, has therefore also saved this expense of Precharge when visit.Like this, to the visit of the most of data lines of poly-dimensional block data, owing to saved Active and Precharge expense, the memory bandwidth utilization factor is improved.
Step 606: whether judge n+1 data line memory address and n+2 data line memory address at same storage line, if, then enter step 607 not at same storage line; Otherwise directly change step 608;
This step is: after having judged the n+1 data line that will visit and its next line promptly the memory address of n+2 data line is positioned at same Bank, continue to judge whether the memory address of two data lines is positioned at same storage line, if be positioned at same storage line, then can carry out the operation of Precharge n data line corresponding stored row, directly visit gets final product, if not at same storage line, the storage line of Precharge n data line correspondence then.
Step 607: execution in step 606 behind the automatic Precharge n data line corresponding stored row;
Step 608: n is changeed step 600 from increasing 1 back, and the next data line that is about to the current data row is set at the current data row.
What deserves to be explained is that judging end, visit, memory line states setting and going forward one by one all is the steering logic of described State Control machine 420, also can be understood as the internal logic subassembly of described State Control machine 420.That is to say, if is these steering logic realifications of State Control machine 420 device, be construed as this mode and shown that described State Control machine 420 can be with multi-form enforcements such as hardware and firmwares, but the those skilled in the art that are not both of this embodiment need not to pay creative work just predictable.
With reference to figure 3, described multiport storage controller 300 can also comprise bit width conversion device 310, and this bit width conversion device 310 couples with described bus interface module.Described bit width conversion device 310 is used for the data bit width of the described VAHB interface module 322 of visit is converted into high-bit width from low-bit width.For example the data bit width of external system is 32bit, convert thereof into for behind the data bit width of 64bit in being input to VAHB interface module 322, perhaps the high-bit width data-switching that will receive from VAHB interface module 322 becomes the low-bit width data and is sent to external system.This bit width conversion device 310 will further improve the access bandwidth to storer.
The present invention is an example with 32bit two dimension bus and 64bit two dimension bus bit width conversion, describes the bit width conversion method.Because of carrying out DoubleWord (double word) alignment in the 64bit transfer address, therefore, when if the bus line command first address of 32bit is not the double word alignment, the first address that needs the 32bit bus side is sent is offset, make the first address double word of 64bit operation align, and be not carry out actual data operations in the address space of expansion, can pass through validity to the byte mask signal controlling corresponding data of storer.
Bit width conversion is mainly carried out conversion to the data columns of two-dimensional block, and the number of data lines m of two-dimensional block is constant.If the columns n of two-dimensional block is an even number, then the columns after the conversion is n/2; If the columns n of two-dimensional block is an odd number, then need columns is expanded conversion again, the columns after the conversion is (n+1)/2.When carrying out data write operation, the 32bit bus data is deposited among the FIFO (first in first out buffer memory) of a 64bit bit wide of modular converter inside, after data reach the FIFO waterline, send the order of 64bit write operation to Memory Controller.When the 32bit bus data all write among the FIFO, the write operation of system bus side was finished.
During read operation, FIFO can convert the data of 32bit bit wide to from the read back data of 64bit bit wide of Memory Controller side at every turn then with corresponding rule.If the columns of two-dimensional block is an odd number, the unnecessary data of will reading back, but, can know which byte is that effectively which is invalid in the 64bit data, and the bit width conversion module can be filtered invalid data automatically according to the odd even feature of n.Fig. 7 is the synoptic diagram of above-mentioned bit width conversion.
What deserves to be explained is that the two dimension that multi-dimensional address is not limited to mention in the above-described embodiments can be three-dimensional, the four-dimension etc.In addition, in the data bit width conversion, also being not limited only to 32bit and being converted to 64bit, also can be that 8bit is converted to 16bit, and 8bit is converted to 32bit etc.In addition, the polytype data bus that provides among the present invention mixes the method for the same storer of visit, both can realize by the corresponding different controller of different buses, also can realize, as long as these data buss all convert a unified interface to and are connected with controller by the corresponding same controller of different buses.
The above is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also are considered as protection scope of the present invention.
Claims (20)
1, a kind of method of visiting poly-dimensional block data in the multiple zone memory is characterized in that, may further comprise the steps:
(a) if the current data row is last column of described poly-dimensional block data, then visit the current data line data of the poly-dimensional block data in the described multiple zone memory by the memory address of described current data row, and process ends;
If current data is capable is not last column of described poly-dimensional block data, calculates the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row;
(b) visit the current data line data of the poly-dimensional block data in the described multiple zone memory by the memory address of described current data row;
(c) judge whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the capable address relation of described a plurality of follow-up datas, if, then activate the capable corresponding stored row of follow-up data in advance, and/or auto-precharge current data row corresponding stored row;
(d) after being set at the current data row, the next data line of current data row returns step (a).
2, a kind of method of visiting poly-dimensional block data in the multiple zone memory as claimed in claim 1 is characterized in that, described multiple zone memory is DRAM or SDRAM or DDR SDRAM or DDR2 SDRAM or RLDRAM or FCRAM.
3, a kind of method of visiting poly-dimensional block data in the multiple zone memory as claimed in claim 1 is characterized in that, described multidimensional data is 2 dimension data.
4, a kind of method of visiting poly-dimensional block data in the multiple zone memory as claimed in claim 1, it is characterized in that described memory address and multidimensional data format information according to described current data row calculated the capable memory address of a plurality of follow-up datas that will visit in advance and comprised:
The first memory address of next data line=the first memory address of current data row+memory address at interval.
5, a kind of method of visiting poly-dimensional block data in the multiple zone memory as claimed in claim 4, it is characterized in that described memory address and multidimensional data format information according to described current data row further comprises after calculating the capable memory address of a plurality of follow-up datas that will visit in advance:
After a storage line visit in proparea finishes, forward the storage line in next district to.
6, a kind of multidimensional store access controller of visiting multiple zone memory is characterized in that, comprising:
Judge to finish device, be used to judge, finish after then calling access means if the current data row is last column of poly-dimensional block data, otherwise the call address mapper;
Access means is used for sending the command sequence of visiting described multiple zone memory by the memory address of described current data row;
Address mapper is used for calculating the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row;
The memory line states setting device, be used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the capable address relation of described a plurality of follow-up datas, if, then activate the capable corresponding stored row of follow-up data in advance, and/or auto-precharge current data row corresponding stored row;
The device that goes forward one by one is used for the next data line of current data row is set at the current data row;
Data Generator, the command sequence that is used for sending according to described access means is sent interrogation signal, is write out or readback data to described multiple zone memory.
7, multidimensional store access controller as claimed in claim 6 is characterized in that, described memory line states setting device comprises:
Judgment means is used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the position relation of the capable memory address of described follow-up data;
Active device is used for activating in advance the capable corresponding stored row of follow-up data;
The auto-precharge device is used for auto-precharge current data row corresponding stored row.
8, multidimensional store access controller as claimed in claim 6 is characterized in that, described multidimensional is 2 dimensions.
9, a kind of multiport storage controller of visiting multiple zone memory comprises:
A plurality of bus interface modules comprise at least one multidimensional data bus interface module and at least one common status bus interface module;
Moderator couples with described a plurality of bus interface modules, is used for selecting a multidimensional data bus interface module or a common status bus interface module at described a plurality of bus interface modules;
The store access controller group couples with described moderator, is used to provide memory access control;
MUX couples with described store access controller group, is used for selecting a multidimensional store access controller or a generic access controller in described store access controller group;
Wherein said store access controller group comprises:
The generic access controller is used to provide the access control to one-dimensional data;
The multidimensional store access controller is used to provide the access control to multidimensional data;
Wherein said multidimensional store access controller comprises:
Judge to finish device, be used to judge, finish after then calling access means if the current data row is last column of poly-dimensional block data, otherwise the call address mapper;
Access means is used for sending the command sequence of visiting described multiple zone memory by the memory address of described current data row;
Address mapper is used for calculating the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row;
The memory line states setting device is used for being provided with by the capable state of pre-defined rule to capable corresponding stored row of follow-up data and/or current data row corresponding stored row according to the capable address relation of described a plurality of follow-up datas;
The device that goes forward one by one is used for the next data line of current data row is set at the current data row;
Data Generator, the command sequence that is used for sending according to described access means is sent interrogation signal, is write out or readback data to described multiple zone memory.
10, the multiport storage controller of visit multiple zone memory as claimed in claim 9, it is characterized in that, also comprise the bit width conversion device that couples with described bus interface module, the low-bit width data-switching that is used for receiving from the outside becomes to be sent to after the high-bit width data and will be sent to the outside after described bus interface module maybe will become the low-bit width data from the high-bit width data-switching that bus interface module receives.
As the multiport storage controller of claim 9 or 10 described visit multiple zone memories, it is characterized in that 11, described bus is ahb bus or the AXI bus in the AMBA bus.
As the multiport storage controller of claim 11 or 12 described visit multiple zone memories, it is characterized in that 12, described memory line states setting device comprises:
Judgment means is used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the position relation of the capable memory address of described follow-up data;
Active device is used for activating in advance the capable corresponding stored row of follow-up data;
The auto-precharge device is used for auto-precharge current data row corresponding stored row.
13, as the multiport storage controller of claim 9 or 10 described visit multiple zone memories, it is characterized in that, also comprise the refresh unit and the initialization unit that couple with described generic access controller and multidimensional store access controller, described refresh unit is used to refresh the data or the order of described generic access controller and multidimensional store access controller; Described initialization unit is used for described generic access controller and the initialization of multidimensional store access controller.
14, a kind of information handling system is characterized in that, comprising:
Message handler is as the source device of access data;
With the bus that described message handler couples, be used to transmit data;
With the multiport storage controller that described bus couples, be used for the storage of control data;
With the memory controller PLIM that described multiport storage controller couples, be used for converting the input and output digital signal of described multiport storage controller to multiple zone memory desired physical signalling;
Multiple zone memory with described storage controller interface physical layer block couples is used to store data;
Wherein said multiport storage controller comprises:
A plurality of bus interface modules comprise at least one multidimensional data bus interface module and at least one common status bus interface module;
Moderator couples with described a plurality of bus interface modules, is used for selecting a multidimensional data bus interface module or a common status bus interface module at described a plurality of bus interface modules;
The store access controller group couples with described moderator, is used to provide memory access control;
MUX couples with described store access controller group, is used for selecting a multidimensional store access controller or a generic access controller in described store access controller group;
Wherein said store access controller group comprises:
The generic access controller is used to provide the access control to one-dimensional data;
The multidimensional store access controller is used to provide the access control to multidimensional data;
Wherein said multidimensional store access controller comprises:
Judge to finish device, be used to judge, finish after then calling access means if the current data row is last column of poly-dimensional block data, otherwise the call address mapper;
Access means is used for sending the command sequence of visiting described multiple zone memory by the memory address of described current data row;
Address mapper is used for calculating the capable memory address of a plurality of follow-up datas that will visit in advance according to the memory address and the multidimensional data format information of described current data row;
The memory line states setting device is used for being provided with by the capable state of pre-defined rule to capable corresponding stored row of follow-up data and/or current data row corresponding stored row according to the capable address relation of described a plurality of follow-up datas;
The device that goes forward one by one is used for the next data line of current data row is set at the current data row;
Data Generator, the command sequence that is used for sending according to described access means is sent interrogation signal, is write out or readback data to described multiple zone memory.
15, information handling system as claimed in claim 14 is characterized in that, described memory line states setting device comprises:
Judgment means is used for judging whether to activate in advance capable corresponding stored row of follow-up data and/or auto-precharge current data row corresponding stored row according to the position relation of the capable memory address of described follow-up data;
Active device is used for activating in advance the capable corresponding stored row of follow-up data;
The auto-precharge device is used for auto-precharge current data row corresponding stored row.
16, as claim 14 or 15 described information handling systems, it is characterized in that, described multiport storage controller also comprises the bit width conversion device that couples with described bus interface module, and the low-bit width data-switching that is used for receiving from the outside becomes to be sent to after the high-bit width data and will be sent to the outside after described bus interface module maybe will become the low-bit width data from the high-bit width data-switching that bus interface module receives.
As claim 14 or 15 described information handling systems, it is characterized in that 17, described bus is ahb bus or the AXI bus in the AMBA bus.
As claim 14 or 15 described information handling systems, it is characterized in that 18, the part address signal packet of described bus contains the multidimensional data format information.
As claim 14 or 15 described information handling systems, it is characterized in that 19, described multiple zone memory is DRAM or SDRAM or DDR SDRAM or DDR2 SDRAM or RLDRAM or FCRAM.
20, as claim 14 or 15 described information handling systems, it is characterized in that, also comprise the refresh unit and the initialization unit that couple with described generic access controller and multidimensional store access controller, described refresh unit is used to refresh the data or the order of described generic access controller and multidimensional store access controller; Described initialization unit is used for described generic access controller and the initialization of multidimensional store access controller.
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| CNB2006100370752A CN100538738C (en) | 2006-08-16 | 2006-08-16 | Method, the Apparatus and system of the poly-dimensional block data in the visit multiple zone memory |
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| CN106502806B (en) * | 2016-10-31 | 2020-02-14 | 华为技术有限公司 | Bus protocol command processing device and related method |
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