CN206804822U - Bank safety chip automatization test system - Google Patents
Bank safety chip automatization test system Download PDFInfo
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- CN206804822U CN206804822U CN201720273894.0U CN201720273894U CN206804822U CN 206804822 U CN206804822 U CN 206804822U CN 201720273894 U CN201720273894 U CN 201720273894U CN 206804822 U CN206804822 U CN 206804822U
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Abstract
The utility model discloses a kind of bank safety chip automatization test system, the system includes V50 test machines, test DUT and manipulator, manipulator and is arranged on V50 test machines, and V50 test machines are connected with test DUT, test DUT is connected with chip to be measured, and manipulator is connected with chip to be measured；Power supply and data signal are sent to chip to be measured by V50 test machines by testing DUT, and the test result information of return is sent to V50 test machines by chip to be measured by testing DUT；Chip to be measured is placed into test section by V50 test machines control machinery hand, and V50 test machines are tested chip to be measured, and test result is returned to manipulator by V50 test machines, and manipulator is classified according to the test result received to chip to be measured.
Description
Technical field
The utility model belongs to the technical field of bank's chip test system, and more particularly to bank safety chip automation is surveyed
Test system.
Background technology
Chip bank card, also known as financial IC card, it is the bank card using chip as medium.Chip card capacity is big, its work
Principle is similar to microcomputer, can be provided simultaneously with multiple functions.Chip bank card is divided into pure chip card and magnetic stripe chip again
Composite card.
The existing usual test process of bank's chip test system is complicated, can not realize automation, it is necessary to which manual intervention, is surveyed
It is low to try efficiency.
The automatization test system of this case mainly provides testing service, test machine and test circuit for bank safety chip
Chip to be measured is connected to by DUT, the test to single chip can be achieved, can be to peace of trying to be the first after test machine connects manipulator
Full chip carries out automatic mass test, and test result test machine tested after electrical parameter preserves, while by core
Defective products in piece screens, and non-defective unit and defective products is respectively put into different TRAY disks at this end of manipulator.
Utility model content
To solve the above problems, the purpose of this utility model is to provide a kind of bank safety chip automatic test system
System, the test system are surveyed using the cooperation of V50 test machines and manipulator to the DC parameter and alternating-current parameter of chip to be measured
Examination, so that the parameters of each chip are normal, and the consistency adjustment per phase parameter is to optimal.
Another purpose of the present utility model is to provide a kind of bank safety chip automatization test system, the test system
System can carry out non-defective unit and divide BIN and defective products to divide BIN.
To achieve the above object, the technical solution of the utility model is as follows.
A kind of bank safety chip automatization test system, including V50 test machines, test DUT and manipulator, the machinery
Hand is arranged on V50 test machines, and the V50 test machines are connected with test DUT, and the test DUT is connected with chip to be measured, and institute
Manipulator is stated to be connected with chip to be measured；Power supply and data signal are sent to core to be measured by the V50 test machines by testing DUT
Piece, and the test result information of return is sent to V50 test machines by chip to be measured by testing DUT；The V50 test machines control
Chip to be measured is placed into test section by manipulator, and the V50 test machines are tested chip to be measured, and the V50 test machines will
Test result returns to manipulator, and the manipulator carries out fine or not classification according to the test result received to chip to be measured.
The V50 test machines are provided with power module and digital channel module, the power module and digital channel module
It is connected with test DUT, the V50 test machines give chip power supply to be measured by power module and test DUT, and the V50 is surveyed
Test-run a machine applies corresponding pumping signal by digital channel module and test DUT to chip to be measured.
Test platform, cylinder, guide rail and support are additionally provided with the V50 test machines, it is flat that the test section is arranged on test
On platform, the guide rail and support are arranged on the top of test section, and the upper end of the manipulator is arranged on support, and the cylinder leads to
Cross guide rail to be connected with carriage drive, and the support moves on guide rail.
Further, the lower end of the manipulator is provided with sucker, the cylinder and sucker drive connection, and the sucker is used
Chip feeding and sub-material to be measured on to test section.
Further, the supply voltage of the power module is one kind in 3.3V, 5V, 5.5V or 2.7V.
The bank safety chip automatization test system that the utility model is realized, by V50 test machines, test DUT and
The cooperation of manipulator, the DC parameter and alternating-current parameter of chip to be measured are tested, so that the items of each chip to be measured
Parameter is normal, and the consistency adjustment per phase parameter is to optimal；Furthermore manipulator judges chip to be measured according to test result
Quality, defective products Effective selection is come out, and non-defective unit is placed into non-defective unit area, defective products is placed into bad area, realized to bank
The automatic test of safety chip and screening.
Brief description of the drawings
Fig. 1 is the block diagram for the bank safety chip automatization test system that the utility model is implemented；
Fig. 2 is the structural representation for the bank safety chip automatization test system that the utility model is implemented.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation
Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only explaining
The utility model, it is not used to limit the utility model.
Bank safety chip automatization test system shown in Figure 1, being realized by the utility model, including V50 are surveyed
Test-run a machine 1, test DUT2 and manipulator 3, manipulator 3 are arranged on V50 test machines 1, and V50 test machines 1 are connected with test DUT2, are surveyed
Examination DUT2 is connected with chip to be measured, and manipulator 3 is connected with chip to be measured；V50 test machines 1 are by testing DUT2 power supply sum
Word signal is sent to chip to be measured, and the test result information of return is sent to V50 test machines by chip to be measured by testing DUT
1；Chip to be measured is placed into test section 15 by the control machinery hand 3 of V50 test machines 1, and V50 test machines 1 are tested chip to be measured,
Test result is returned to manipulator 3 by V50 test machines 1, and manipulator 3 is carried out according to the test result received to chip to be measured
Quality classification.
V50 test machines 1 are provided with power module and digital channel module, power module and digital channel module with test
DUT2 connections, V50 test machines 1 give chip power supply to be measured by power module and test DUT2, and V50 test machines 1 pass through numeral
Channel module and test DUT2 apply corresponding pumping signal to chip to be measured.V50 test machines 1 test every ginseng of chip to be measured
Number, the quality of chip to be measured is judged according to test result, defective products Effective selection is come out.Digital channel module mainly realizes hair
The signal for sending data command to be fed back to chip to be tested and reception chip to be tested.
Referring to Fig. 2, test platform 11, cylinder 12, guide rail 13 and support 14, test section 15 are additionally provided with V50 test machines 1
It is arranged on test platform 11, guide rail 13 and support 14 are arranged on the top of test section 15, and the upper end of manipulator 3 is arranged on support
On 14, cylinder 12 is by guide rail 13 and the drive connection of support 14, and support 14 moves on guide rail 13.
The lower end of manipulator 3 is provided with sucker 5, cylinder 12 and the drive connection of sucker 5, and sucker 5 is used for test section 15
Chip feeding and sub-material to be measured.
The supply voltage of power module is one kind in 3.3V, 5V, 5.5V or 2.7V.
In this test system, V50 test machines 1 have mainly used power module and digital channel module, and power module can
To provide the power supply of fixed output, such as+5V/+15V/-15V/+19V, these pin can one after electricity on V50 test machines 1
The voltage of the straight corresponding numerical value of output, numerical value are unadjustable.RL1-32 is Control position signal, and user's relay can be entered
Row control.DPS1 in figure below, DPS2 are the programmable power supplys in 2 tunnels, it is possible to achieve the free voltage output between 0-15V, and
The output current of the power supply can be measured simultaneously, and this function needs just to have corresponding voltage when testing results program
Output.
In this test system ,+5V fixed power source and the programmable power supplys of DPS1 are used ,+5V power supply passes through test
Interface on DUT2 is powered to RELAY, ensures that RELAY is not powered off in test process, 1 programmable power supply DPS1 passes through in addition
Test DUT2 is connected to the supply pin of chip to be measured, realizes the power supply to chip to be measured and the power supply under different mode state
The accurate measurement of electric current.
Test DUT2 is the interface of V50V50 test machines 1 and chip to be tested, and V50 test machines 1 are by testing DUT2 electricity
Source and data signal give chip to be tested, and chip to be tested is given V50 by DUT the test result information of return and tested again
Machine 1, the test communication being so achieved that between V50 test machines 1 and chip to be tested.
Manipulator 3 plays feeding, and connection, material-distributing action, chip to be measured is put into test section 15 by it, and concurrent enabling signal is given to
V50 test machines 1, V50 test machines 1 are tested, and V50 test machines 1 return again to the object information of test to manipulator 3, machinery
Chip is carried out fine or not classification by hand 3 by the object information received.
In a word, the bank safety chip automatization test system that the utility model is realized, V50 test machines, test are passed through
DUT and manipulator cooperation, the DC parameter and alternating-current parameter of chip to be measured are tested, so that each chip to be measured
Parameters are normal, and the consistency adjustment per phase parameter is to optimal；Furthermore manipulator judges core to be measured according to test result
The quality of piece, defective products Effective selection is come out, and non-defective unit is placed into non-defective unit area, defective products is placed into bad area, realization pair
The automatic test of bank safety chip and screening.
Preferred embodiment of the present utility model is these are only, it is all in this practicality not to limit the utility model
All any modification, equivalent and improvement made within new spirit and principle etc., should be included in guarantor of the present utility model
Within the scope of shield.
Claims (4)
- A kind of 1. bank safety chip automatization test system, it is characterised in that the system include V50 test machines, test DUT and Manipulator, the manipulator are arranged on V50 test machines, and the V50 test machines are connected with test DUT, and the test DUT is with treating Chip connection is surveyed, and the manipulator is connected with chip to be measured.
- 2. bank safety chip automatization test system as claimed in claim 1, it is characterised in that on the V50 test machines Provided with power module and digital channel module, the power module and digital channel module are connected with test DUT.
- 3. bank safety chip automatization test system as claimed in claim 1, it is characterised in that on the V50 test machines Test platform, cylinder, guide rail and support are additionally provided with, the test section is arranged on test platform, and the guide rail and support are set In the top of test section, the upper end of the manipulator is arranged on support, and the cylinder is connected by guide rail with carriage drive, and The support moves on guide rail.
- 4. bank safety chip automatization test system as claimed in claim 3, it is characterised in that the lower end of the manipulator Provided with sucker, the cylinder and sucker drive connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720273894.0U CN206804822U (en) | 2017-03-21 | 2017-03-21 | Bank safety chip automatization test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720273894.0U CN206804822U (en) | 2017-03-21 | 2017-03-21 | Bank safety chip automatization test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206804822U true CN206804822U (en) | 2017-12-26 |
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ID=60730536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720273894.0U Active CN206804822U (en) | 2017-03-21 | 2017-03-21 | Bank safety chip automatization test system |
Country Status (1)
| Country | Link |
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| CN (1) | CN206804822U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108627764A (en) * | 2017-03-21 | 2018-10-09 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system and its control method |
| CN110320458A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Automate chip test system |
| CN110314864A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip detecting method and device based on manipulator |
| CN110320459A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip automated testing method and device |
| CN110320457A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip grabs control method and device |
| CN110320427A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip detecting method and device |
-
2017
- 2017-03-21 CN CN201720273894.0U patent/CN206804822U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108627764A (en) * | 2017-03-21 | 2018-10-09 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system and its control method |
| CN110320458A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Automate chip test system |
| CN110314864A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip detecting method and device based on manipulator |
| CN110320459A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip automated testing method and device |
| CN110320457A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip grabs control method and device |
| CN110320427A (en) * | 2018-03-28 | 2019-10-11 | 北京君正集成电路股份有限公司 | Chip detecting method and device |
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Legal Events
| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190815 Address after: 518000 Guangdong Province Baoan District Hangcheng Street Huangtian Community Huangtian Yangbei Industrial Zone Phase I 4 201, 301, 402 Patentee after: Shenzhen Hualiyu Electronic Technology Co., Ltd. Address before: 518000 Yangbei Industrial Zone, Huangtian, Xixiang Street, Baoan District, Shenzhen City, Guangdong Province, Phase 1, 3, 4, 5, 7 (4th, 3rd floor) Patentee before: SHENZHEN HUAYU SEMICONDUCTOR CO., LTD. |
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| TR01 | Transfer of patent right |