CN206441034U - A kind of voltage clamp circuit - Google Patents
A kind of voltage clamp circuit Download PDFInfo
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- CN206441034U CN206441034U CN201720055994.6U CN201720055994U CN206441034U CN 206441034 U CN206441034 U CN 206441034U CN 201720055994 U CN201720055994 U CN 201720055994U CN 206441034 U CN206441034 U CN 206441034U
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Abstract
The utility model embodiment discloses a kind of voltage clamp circuit, and it includes：Reference voltage source module, for providing reference voltage；Transistor controls module, the input of transistor controls module is connected with the output end of reference voltage source；Anti-phase control module, the output end of anti-phase control module is connected with the control end of transistor controls module；End module is exported, the input of output end module is connected with the output end of transistor controls module.Switched by anti-phase control module by accessing PWM voltage signal controlling transistor control modules between working condition and off working state, the reference voltage that transistor controls module transfer reference voltage source module under working condition is provided gives output end module, output end module is provided and the anti-phase clamp voltage signal of PWM voltage signals according to reference voltage to need to access by the circuit components of voltage limit so that circuit components energy normal work.
Description
Technical field
The utility model is related to analog chip design field, more particularly to a kind of voltage clamp circuit.
Background technology
Clamp circuit (clamping circuit) is that certain part of pulse signal is fixed in given voltage value, and
The circuit of original waveform shape invariance is kept, is widely used in analog chip design field.
The effect of clamp circuit is the direct current that the top or bottom of periodically variable waveform are maintained to a certain determination
On flat.General common clamp circuit is diode clamping circuit, and the clamping action of voltage-regulator diode refers to utilize the pole of voltage stabilizing two
Pipe forward conduction voltage drop is stablized relatively, and the characteristics of numerical value smaller (can be approximately zero sometimes), carrys out the electricity that certain in limiting circuit is put
Position.
Voltage clamping is carried out using diode clamping circuit to have a disadvantage that：Need the voltage-regulator diode of a specific voltage
To carry out clamper, this design technology to chip has higher requirement；Voltage-regulator diode can bring extra lithographic layer and need
Larger area is wanted, increases the cost of chip；In addition, when the effect of voltage clamping is realized when voltage-regulator diode conducting, having
Electric current flows through voltage-regulator diode, inevitably results in extra power dissipation, also has large effect to the efficiency of chip.Therefore,
It is necessary that a kind of can both realize of design carries out voltage clamping to voltage, the requirement of chip design technology, reduction core can be reduced again
Piece cost and the voltage clamp circuit for improving chip efficiency.
Utility model content
To solve Related Technical Issues, the utility model provides a kind of voltage clamp circuit, to need to access by voltage limit
Circuit components provide clamp voltage signal.
To achieve the above object, the utility model embodiment is adopted the following technical scheme that：
A kind of voltage clamp circuit, including：
Reference voltage source module, for providing reference voltage；
Transistor controls module, the input of the transistor controls module and the output end phase of the reference voltage source
Even, for transmitting the reference voltage in the operating condition；
Anti-phase control module, the control end phase of the output end of the anti-phase control module and the transistor controls module
Even, for accessing PWM voltage signals, and the transistor controls module switch operating shape is controlled according to the PWM voltage signals
State and off working state；
End module is exported, the input of the output end module is connected with the output end of the transistor controls module, used
In the clamp voltage signal that circuit components are produced output to according to the reference voltage.
Wherein, the power input of the reference voltage source module is connected with power supply, and first input end access first is biased
Electric current, the second input accesses the second bias current, the reference voltage source module be used for according to first bias current and
The supply voltage of access is converted into the reference voltage by second bias current.
Wherein, the reference voltage source module includes the second PMOS, the 3rd PMOS, the 4th PMOS pipes, the 8th NMOS
Pipe, the 9th NMOS tube, the 7th NMOS tube and second resistance device；
Second PMOS, the 3rd PMOS, the source electrode of the 4th PMOS are connected with the power supply；Second PMOS
Drain electrode of the drain electrode with the 8th NMOS tube and grid be connected；The drain electrode of 3rd PMOS is connected with grid, and with
The drain electrode of the grid of second PMOS and the 9th NMOS pipes is connected；The grid access of 4th PMOS is described
First bias current, drain electrode is connected with the grid of the 9th NOMS pipes, and is connected with one end of the second resistance device, described
The other end of second resistance device is connected with ground wire；The drain electrode of the 7th NOMS pipes with the source electrodes of the 8th NOMS pipes and the
The source electrode of nine NMOS tubes is connected, and grid accesses second bias current, and source electrode is connected with ground wire.
Wherein, the transistor controls module includes the 5th PMOS, and the grid of the 5th PMOS is used as input
It is connected with the output end of the reference voltage source module.
Wherein, the power input of the anti-phase control module is connected with power supply, and first input end accesses the 3rd biased electrical
Stream, control end accesses the PWM voltage signals, the anti-phase control module be used for according to supply voltage, the 3rd bias current and
PWM voltage signals, control the transistor controls module switch operating state and off working state.
Wherein, the anti-phase control module includes the first PMOS, the 6th NMOS tube, the 4th NMOS pipes, the 5th NMOS tube
With the 3rd NMOS tube；
The source electrode of first PMOS is connected as the power input with the power supply, and grid is used as described first
Input accesses the 3rd bias current, drain electrode and output end, the drain electrode of the 3rd NMOS tube of the transistor controls module
And the 5th NOMS pipes drain electrode be connected；The drain electrode of 6th NMOS tube and the control end phase of the transistor controls module
Even, drain electrode of the grid respectively with the draining of the 6th NMOS tube, the grid of the 5th NOMS pipes and the 4th NMOS tube is connected；
The source electrodes of the 6th NOMS pipes, the source electrode of the 4th NMOS tube, the source electrode of the 5th NMOS tube and the 3rd NOMS pipes source electrode it is equal
It is connected with ground wire；The grid of the 4th NOMS pipes, which is connected with the grid of the 3rd NMOS tube and accesses the PWM voltages, to be believed
Number, it is used as the control end of the anti-phase control module.
Wherein, the power input of the output end module is connected with power supply, and output end is defeated with the circuit components
Enter end to be connected, the output end module is used for the pincers for producing output to circuit components according to supply voltage and the reference voltage
Position voltage signal.
Wherein, the output end module includes the first NMOS tube and the second NMOS tube；The drain electrode of the first NMOS pipes is made
Be connected for power input with power supply, grid is connected as input with the output end of the transistor controls module, source electrode with
The drain electrode of second NMOS tube is connected, and source electrode is used as the output end and the input of the circuit components of output end module
It is connected；The grid of second NMOS tube is connected with the control end of the anti-phase control module, and source electrode is connected with ground wire.
Wherein, the circuit components are metal-oxide-semiconductor.
The beneficial effect that the technical scheme that the utility model embodiment is provided is brought：
In the technical program, existed by anti-phase control module by accessing PWM voltage signal controlling transistor control modules
Switch between working condition and off working state, the transistor controls module transfer reference voltage source module under working condition is carried
The reference voltage of confession gives output end module, and output end module accesses the circuit components by voltage limit according to reference voltage for needs
There is provided and the anti-phase clamp voltage signal of PWM voltage signals so that circuit components energy normal work.
Brief description of the drawings
, below will be to the utility model embodiment in order to illustrate more clearly of the technical scheme in the utility model embodiment
The accompanying drawing used required in description is briefly described, it should be apparent that, drawings in the following description are only that this practicality is new
Some embodiments of type, for those of ordinary skill in the art, on the premise of not paying creative work, can be with root
Other accompanying drawings are obtained according to the content and these accompanying drawings of the utility model embodiment.
Fig. 1 is a kind of square frame principle schematic diagram for voltage clamp circuit that the utility model embodiment is provided；
Fig. 2 is a kind of circuit theory schematic diagram for voltage clamp circuit that the utility model embodiment is provided.
Embodiment
To make the utility model technical problem solved, the technical scheme used and the technique effect reached clearer,
The technical scheme of the utility model embodiment is described in further detail below in conjunction with accompanying drawing, it is clear that described reality
It is only a part of embodiment of the utility model to apply example, rather than whole embodiments.Based on the embodiment in the utility model,
The every other embodiment that those skilled in the art are obtained under the premise of creative work is not made, belongs to this practicality new
The scope of type protection.
Fig. 1 and Fig. 2 are refer to, wherein, Fig. 1 is a kind of square frame for voltage clamp circuit that the utility model embodiment is provided
Principle schematic；Fig. 2 is a kind of circuit theory schematic diagram for voltage clamp circuit that the utility model embodiment is provided.
As shown in figure 1, in the circuit of design simulation chip, a kind of voltage clamp circuit, it is characterised in that including：
Reference voltage source module 1, for providing reference voltage；
Transistor controls module 2, the input of transistor controls module 2 is connected with the output end of reference voltage source 1, is used for
Reference voltage is transmitted in the operating condition；
Anti-phase control module 3, the output end of anti-phase control module 3 is connected with the control end of transistor controls module 2, is used for
PWM voltage signals are accessed, and according to the switch operating state of PWM voltage signal controlling transistors control module 2 and off working state；
End module 4 is exported, the input of output end module 4 is connected with the output end of transistor controls module 2, for basis
Reference voltage produces output to the clamp voltage signal of circuit components.
In the circuit of design simulation chip, the voltage that output end module 4 is exported is linked into as the driving voltage of chip
The grid of the circuit components such as metal-oxide-semiconductor, triode, the grid voltage of the circuit components such as metal-oxide-semiconductor, triode access is generally all
Restricted, that is, the grid voltage accessed can not be too high.When the operating voltage VDD of chip is not high, output end module 4 is exported
Driving voltage is not also high, but when the operating voltage VDD of chip it is too high be more than threshold value when, output end module 4 export driving
Voltage is also too high, it is impossible to be linked into the grid of circuit components, therefore, when the operating voltage VDD of chip is too high, it is necessary to limit
The voltage signal that system output end module 4 is exported.
In the present embodiment, by anti-phase control module 3 by accessing PWM voltage signal controlling transistors control module 2
Switch between working condition and off working state, the transmission reference voltage source module of transistor controls module 2 under working condition
1 reference voltage provided gives output end module 4, and output end module 4 accesses the electricity by voltage limit according to reference voltage for needs
Road component is provided and the anti-phase clamp voltage signal of PWM voltage signals so that circuit components energy normal work.
As shown in Fig. 2 wherein, the power input of said reference voltage source module 1 is connected with power supply, and first input end connects
Enter the first bias current IBS1, the second bias current I of the second input accessBS2, reference voltage source module 1 is used for inclined according to first
Put electric current IBS1With the second bias current IBS2The supply voltage VDD of access is converted into reference voltage V 3.
Further, reference voltage source module 1 includes the second PMOS N2, the 3rd PMOS P3, the 4th PMOS P4, the
Eight NMOS tube N8, the 9th NMOS tube N9, the 7th NMOS tube N7 and second resistance device R2；
Second PMOS P2, the 3rd PMOS P3, the 4th PMOS P4 source electrode are connected with power supply；Second PMOS P2
Drain electrode of the drain electrode with the 8th NMOS tube N8 and grid be connected；3rd PMOS P3 drain electrode is connected with grid, and with second
PMOS P2 grid and the 9th NMOS tube P9 drain electrode are connected；4th PMOS P4 grid accesses the first bias current
IBS1, drain electrode is connected with the 9th NOMS pipes N9 grid, and is connected with second resistance device R2 one end, and second resistance device R2's is another
One end is connected with ground wire；Source electrode and nineth NMOS tube N9 source electrode phase of the 7th NOMS pipes N7 drain electrode with the 8th NOMS pipes N8
Even, grid accesses the second bias current IBS2, source electrode is connected with ground wire.
In the present embodiment, reference voltage source module 1 is according to the first bias current I of accessBS1With the second bias current
IBS2, the supply voltage VDD of access is converted into the reference voltage V 3 of no more than given threshold, realizes and is exported in output end module 4
Clamp voltage signal Vout；Wherein, the first bias current IBS1So that the 4th PMOS pipes P4 works, the second bias current IBS2 makes
The 7th PMOS P7 work is obtained, note N8 grid voltage is V4, and N9 grid voltage is V5, then V3 value is related to V4, V4's
Value is related to V5, and V5=IBS1*R2, therefore V3=VGS (N8)-VGS (N9)+V5, VGS (N8) and VGS (N9) points in formula
Not Wei N8 gate source voltage and N9 gate source voltage.
Wherein, above-mentioned transistor controls module 2 includes the 5th PMOS P5, and the 5th PMOS P5 grid is used as input
It is connected with the output end of reference voltage source module 1.In the present embodiment, transistor controls module 2 uses the 5th PMOS P5, leads to
Cross the 5th in running order PMOS P5 to transmit reference voltage V 3, on the basis of the input voltage signal for exporting end module 4
Voltage signal V3 adds the 5th PMOS pipes P5 gate source voltage VGS(P5)。
Wherein, the power input of above-mentioned anti-phase control module 3 is connected with power supply, and first input end accesses the 3rd biased electrical
Flow IBS3, control end access PWM voltage signals V2, anti-phase control module 3 is for according to supply voltage VDD, the 3rd bias current
IBS3With PWM voltage signal V2, the switch operating state of controlling transistor control module 2 and off working state.
Further, anti-phase control module 3 includes the first PMOS P1, the 6th NMOS tube N6, the 4th NMOS tube N4, the 5th
NMOS tube N5 and the 3rd NMOS tube N3；
First PMOS P1 source electrode is connected as power input with power supply, and grid accesses the 3rd as first input end
Bias current IBS3, drain electrode and the output end of transistor controls module 2, the 3rd NMOS tube N3 drain electrode and the 5th NOMS pipes N5
Drain electrode is connected；6th NMOS tube N6 drain electrode is connected with the control end of transistor controls module 2, grid respectively with the 6th NMOS
Pipe N6 drain electrode, the drain electrode of the 5th NOMS pipes N5 grid and the 4th NMOS tube N4 are connected；6th NOMS pipes N6 source electrode,
The source electrode of four NMOS tube N4 source electrode, the 5th NMOS tube N5 source electrode and the 3rd NOMS pipes N3 is connected with ground wire；4th
NOMS pipes N4 grid and the 3rd NMOS tube N3 grid are connected and access PWM voltage signal V2, are used as anti-phase control module 3
Control end.
In the present embodiment, when PWM voltage signals V2 is high level, N3 and N4 conductings so that N5, N6, P1 and P5 are equal
In idle state, P5 does not work so that the voltage of output end module input access is 0V；When PWM voltage signals V2 is
During low level, N3 and N4 cut-offs so that N5, N6, P1 and P5 are in working condition, P5, which works, causes output end module input
Voltage signal V3 adds the 5th PMOS P5 gate source voltage V on the basis of the voltage signal of accessGS(P5), that is, access high voltage letter
Number.
Wherein, the power input of above-mentioned output end module 4 is connected with power supply, the input of output end and circuit components
It is connected, output end module 4 is used for the clamp voltage that circuit components are produced output to according to supply voltage VDD and reference voltage V 3
Signal Vout.
Further, output end module 4 includes the first NMOS tube N1 and the second NMOS tube N2；First NMOS tube N1 drain electrode
It is connected as power input with power supply, grid is connected as input with the output end of transistor controls module 2, source electrode and
Two NMOS tube N2 drain electrode is connected, and source electrode is connected as the output end of output end module 4 with the input of circuit components；The
Two NMOS tube N2 grid is connected with the control end of anti-phase control module 3, and source electrode is connected with ground wire.
In the present embodiment, the voltage V1 that output end module 4 is accessed is controlled by N5 working conditions in transistor controls module 2
System, the low and high level of a PWM voltage signals V2 for receiving the anti-phase input of control module 3 is controlled, and V1 is rendered as and PWM voltages are believed
Number V2 is anti-phase, i.e., V1 is low level when V2 is high level, and V1 is high level when V2 is level；When V1 is high level, Vout=
V1+VGS(N1), according to the relation between the above-mentioned V1 and V3 derived, V4 and V5, Vout=V can be drawnGS(N8)-VGS(N9)-
VGS(N1)+VGS(N5)+IBS1* R2, therefore, appropriate to adjust the first bias current I after selected metal-oxide-semiconductorBS1With second resistance device R2's
Resistance, you can realize in the output output clamp voltage signal of end module 4, the requirement of coincident circuit component grid voltage.
Foregoing circuit component is preferably the metal-oxide-semiconductor MOSFET that the voltage accessed in grid is limited, and source electrode connects during its work
First resistor device R1 one end is connect, the R1 other end is connected with ground wire.
In other embodiments, each PMOS in each module of above-mentioned voltage clamp circuit can be replaced the pole of NPN types three
Pipe, each NMOS tube can be replaced PNP type triode；Or output end mould can also be realized with the pressure stabilization function of voltage-regulator diode
Block accesses restricted voltage, and then realizes that circuit components access clamp voltage signal.But carried out using voltage-regulator diode
Clamper, can there is higher requirement to the design technology of analog chip, and voltage-regulator diode can bring extra lithographic layer and needs
Larger area, increases the production cost of chip, in addition, when the effect of voltage clamping is realized when voltage-regulator diode conducting, meeting
There is electric current to flow through voltage-regulator diode, inevitably result in extra power dissipation, also have large effect to the efficiency of chip.
In the utility model embodiment, in order to exempt limitation of the voltage-regulator diode for design technology, the voltage stabilizing of clamper
The increase and the increase of chip power for the domain layer that diode is brought, it is main that a kind of voltage clamping is designed using metal-oxide-semiconductor
Circuit, the circuit structure, principle are all fairly simple, but can effectively achieve the purpose of clamp output voltage.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, can carried out for a person skilled in the art various bright
Aobvious change, readjust and substitute without departing from protection domain of the present utility model.Therefore, although pass through above example
The utility model is described in further detail, but the utility model is not limited only to above example, is not departing from
In the case that the utility model is conceived, other more equivalent embodiments can also be included, and scope of the present utility model is by appended
Right determine.
Claims (9)
1. a kind of voltage clamp circuit, it is characterised in that including：
Reference voltage source module, for providing reference voltage；
Transistor controls module, the input of the transistor controls module is connected with the output end of the reference voltage source, uses
In transmitting the reference voltage in the operating condition；
Anti-phase control module, the output end of the anti-phase control module is connected with the control end of the transistor controls module, uses
The transistor controls module switch operating state is controlled in access PWM voltage signals, and according to the PWM voltage signals and non-
Working condition；
End module is exported, the input of the output end module is connected with the output end of the transistor controls module, for root
The clamp voltage signal of circuit components is produced output to according to the reference voltage.
2. voltage clamp circuit as claimed in claim 1, it is characterised in that the power input of the reference voltage source module
It is connected with power supply, first input end accesses the first bias current, the second input accesses the second bias current, the reference voltage
Source module is used to the supply voltage of access is converted into the base according to first bias current and second bias current
Quasi- voltage.
3. voltage clamp circuit as claimed in claim 2, it is characterised in that the reference voltage source module includes the 2nd PMOS
Pipe, the 3rd PMOS, the 4th PMOS, the 8th NMOS tube, the 9th NMOS tube, the 7th NMOS tube and second resistance device；
Second PMOS, the 3rd PMOS, the source electrode of the 4th PMOS are connected with the power supply；The leakage of second PMOS
Drain electrode and grid of the pole with the 8th NMOS tube are connected；The drain electrode of 3rd PMOS is connected with grid, and with it is described
The drain electrode of the grid of second PMOS and the 9th NMOS tube is connected；The grid access described first of 4th PMOS is inclined
Electric current is put, drain electrode is connected with the grid of the 9th NOMS pipes, and is connected with one end of the second resistance device, second electricity
The other end of resistance device is connected with ground wire；Source electrode and nineth NMOS of the drain electrode of the 7th NOMS pipes with the 8th NOMS pipes
The source electrode of pipe is connected, and grid accesses second bias current, and source electrode is connected with ground wire.
4. voltage clamp circuit as claimed in claim 1, it is characterised in that the transistor controls module includes the 5th PMOS
Pipe, the grid of the 5th PMOS is connected as input with the output end of the reference voltage source module.
5. voltage clamp circuit as claimed in claim 1, it is characterised in that the power input of the anti-phase control module with
Power supply is connected, and first input end accesses the 3rd bias current, and control end accesses the PWM voltage signals, the anti-phase control mould
Block is used to, according to supply voltage, the 3rd bias current and PWM voltage signals, control the transistor controls module switch operating shape
State and off working state.
6. voltage clamp circuit as claimed in claim 5, it is characterised in that the anti-phase control module includes the first PMOS
Pipe, the 6th NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 3rd NMOS tube；
The source electrode of first PMOS is connected as the power input with the power supply, and grid is used as the described first input
Terminate into the 3rd bias current, drain electrode and the output end of the transistor controls module, the drain electrode of the 3rd NMOS tube and the
The drain electrode of five NOMS pipes is connected；The drain electrode of 6th NMOS tube is connected with the control end of the transistor controls module, grid
Drain electrode of the pole respectively with the draining of the 6th NMOS tube, the grid of the 5th NOMS pipes and the 4th NMOS tube is connected；It is described
The source electrodes of 6th NOMS pipes, the source electrode of the 4th NMOS tube, the source electrode of the 5th NMOS tube and the 3rd NOMS pipes source electrode with ground
Line is connected；The grid of the 4th NOMS pipes is connected with the grid of the 3rd NMOS tube and accesses the PWM voltage signals, makees
For the control end of the anti-phase control module.
7. voltage clamp circuit as claimed in claim 1, it is characterised in that the power input of the output end module and electricity
Source is connected, and output end is connected with the input of the circuit components, and the output end module is used for according to supply voltage and institute
State the clamp voltage signal that reference voltage produces output to circuit components.
8. voltage clamp circuit as claimed in claim 7, it is characterised in that the output end module include the first NMOS tube and
Second NMOS tube；The drain electrode of first NMOS tube is connected as power input with power supply, grid as input with it is described
The output end of transistor controls module is connected, and source electrode is connected with the drain electrode of second NMOS tube, and source electrode is used as output end mould
The output end of block is connected with the input of the circuit components；The grid of second NMOS tube and the anti-phase control module
Control end be connected, source electrode is connected with ground wire.
9. the voltage clamp circuit as described in claim any one of 1-8, it is characterised in that the circuit components are metal-oxide-semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720055994.6U CN206441034U (en) | 2017-01-18 | 2017-01-18 | A kind of voltage clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720055994.6U CN206441034U (en) | 2017-01-18 | 2017-01-18 | A kind of voltage clamp circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206441034U true CN206441034U (en) | 2017-08-25 |
Family
ID=59636373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720055994.6U Expired - Fee Related CN206441034U (en) | 2017-01-18 | 2017-01-18 | A kind of voltage clamp circuit |
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| CN (1) | CN206441034U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110515415A (en) * | 2019-09-26 | 2019-11-29 | 北京集创北方科技股份有限公司 | Voltage adjusting device, power supply chip and electronic equipment |
| CN110597344A (en) * | 2019-09-26 | 2019-12-20 | 北京集创北方科技股份有限公司 | Voltage adjusting device, chip and electronic equipment |
| CN114326899A (en) * | 2021-12-27 | 2022-04-12 | 上海贝岭股份有限公司 | Integrated circuit and clamping circuit thereof |
-
2017
- 2017-01-18 CN CN201720055994.6U patent/CN206441034U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110515415A (en) * | 2019-09-26 | 2019-11-29 | 北京集创北方科技股份有限公司 | Voltage adjusting device, power supply chip and electronic equipment |
| CN110597344A (en) * | 2019-09-26 | 2019-12-20 | 北京集创北方科技股份有限公司 | Voltage adjusting device, chip and electronic equipment |
| CN114326899A (en) * | 2021-12-27 | 2022-04-12 | 上海贝岭股份有限公司 | Integrated circuit and clamping circuit thereof |
| CN114326899B (en) * | 2021-12-27 | 2023-09-15 | 上海贝岭股份有限公司 | Integrated circuit and clamping circuit thereof |
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