CN105116209A - High voltage zero-crossing detection circuit - Google Patents
High voltage zero-crossing detection circuit Download PDFInfo
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- CN105116209A CN105116209A CN201510410421.6A CN201510410421A CN105116209A CN 105116209 A CN105116209 A CN 105116209A CN 201510410421 A CN201510410421 A CN 201510410421A CN 105116209 A CN105116209 A CN 105116209A
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Abstract
The present invention belongs to the electronic circuit technology field, in particular to a high voltage zero-crossing detection circuit. The high voltage zero-crossing detection circuit comprises a comparator circuit, a logic output circuit and an acceleration circuit. The comparator circuit is connected with an external AC input signal, the output end of the comparator circuit is connected with the input end of the logic output circuit, and an output signal of the logic output circuit is fed back to the comparator circuit via the acceleration circuit. The beneficial effects of the present invention are that: a high voltage AC voltage zero-crossing detection problem is solved, and the high voltage zero-crossing detection circuit has the advantages of being simple in structure, low in device requirement and stable in working state, being easy to integrate, and being high voltage resistant.
Description
Technical field
The invention belongs to electronic circuit technology field, relate to a kind of high pressure zero cross detection circuit specifically.
Background technology
Nowadays, the electric energy of nearly all generation is all AC (alternating current or polarity) type, and required for electronic system is then DC (through current or fixed polarity) type.Even the equipment (such as motor) only accepting alternating current traditionally also needs more and more for its microcontroller (embedded to provide the efficiency of Based Intelligent Control and Geng Gao) provides DC to power.Transfer process from AC to DC is called as rectification.Passive diode bridge rectifier is the most widely used circuit of one.In most of occasion, it all embodies the feature that circuit is simple and cost is low.But in high power applications, diode can consume a large amount of power, and when adopting low-voltage input, two intrinsic diode drops significantly will cut down operating voltage.In addition, the power dissipation level promoting conventional diode bridge needs to increase heat radiation workload, diode temperature is remained within limits.Under low power level, perhaps, vacant board area is enough to the requirement meeting heat radiation, but under higher power level, just must lay the huge and heating radiator of heaviness, need to adopt independent circuit board assembly process to pinion or these heating radiators on bolt, thus cause assembly cost to increase.
For the problems referred to above, the N-channel MOS of employing low-loss at present FET substituted for whole 4 diodes in full wave bridge rectifier, significantly to reduce power dissipation and to increase voltage available.Lifting due to power-efficient eliminates heavy heating radiator, therefore reduces power supply size.Providing extra nargin by exempting two intrinsic diode drops in diode bridge, will larger voltage available be obtained in low voltage application, in high-voltage applications, then can effectively reduce power consumption.
But in this novel full wave bridge rectifier circuit, institute's problems faced is: for alternative diode 4 external switch pipes (connected mode is identical with conventional rectifier bridge) open and shut off consistent with the positive-negative half-cycle of input ac voltage.Because traditional comparer can not bear high pressure, under high pressure device is easily breakdown, cannot complete the zero-crossing examination of High Level AC Voltage.
Summary of the invention
To be solved by this invention, be exactly for the problems referred to above, propose a kind of high pressure zero cross detection circuit.
For achieving the above object, the present invention adopts following technical scheme:
A kind of high pressure zero cross detection circuit, as shown in Figure 1, comprise comparator circuit, logical output circuit and accelerating circuit, described comparator circuit connects external communication input signal, and it exports the input end of termination logical output circuit; The output signal of described logical output circuit feeds back to comparator circuit by accelerating circuit; Wherein,
As shown in Figure 2, described comparator circuit is made up of the first diode D1, the second diode D2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the first PMOS P1, the second PMOS P2, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6; Wherein, the positive pole of the first diode D1 connects first via external communication input signal, and its negative pole connects the drain electrode of the first NMOS tube N1; The grid of the first NMOS tube N1 connects enable signal, and it is by ground connection after the 5th resistance R5; The positive pole of the second diode D2 connects the second road external communication input signal, and its negative pole connects the drain electrode of the second NMOS tube N2; The grid of the second NMOS tube N2 connects enable signal, and its source electrode is by ground connection after the 6th resistance R6; The source electrode of the first PMOS P1 is by connecing the source electrode of the second NMOS tube N2 after the first resistance R1, its grid connects the source electrode of the first NMOS tube N1, its drain electrode drain electrode by meeting the second NMOS tube N3 after the 3rd resistance R3; The source electrode of the second PMOS P2 is by connecing the source electrode of the first NMOS tube N1 after the second resistance R2, its grid connects the source electrode of the second NMOS tube N2, its drain electrode drain electrode by meeting the 4th NMOS tube N4 after the 4th resistance R4; The source ground of the 3rd NMOS tube N3; The source ground of the 4th NMOS tube N4;
Described logical output circuit is made up of the first triode Q1, the second triode Q2, the first phase inverter IV1, the second phase inverter IV2, the 3rd phase inverter IV3, the 4th phase inverter IV4, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9 and the tenth resistance R10; Wherein, the base stage of the first triode Q1 connects the tie point of the 3rd resistance R3 and the 3rd NMOS tube N3, and its collector meets power vd D by the 7th resistance R7, its grounded emitter, and its base stage is by being connected with its emitter after the 9th resistance R9; The input termination first triode Q1 of the second phase inverter IV2 and the tie point of the 7th resistance R7, it exports the input end of termination first phase inverter IV1; The output terminal of the first phase inverter IV1 is the first via output terminal of high pressure zero cross detection circuit; The base stage of the second triode Q2 connects the tie point of the drain electrode of the 4th resistance R4 and the 4th NMOS tube N4, and its collector is by meeting power vd D after the 8th resistance R8, its grounded emitter, and its base stage is by connecing its emitter after the tenth resistance R10; The collector of input termination second triode Q2 of the 3rd phase inverter IV3 and the tie point of the 8th resistance R8, it exports the input end of termination the 4th phase inverter IV4; The output terminal of the 4th phase inverter IV4 is the second road output terminal of high pressure zero cross detection circuit;
Described accelerating circuit is made up of the 5th phase inverter IV5, hex inverter IV6, the 7th phase inverter IV7, the 8th phase inverter IV8; Wherein, the input end of the input termination second phase inverter IV2 of the 5th phase inverter IV5, it exports the input end of termination hex inverter IV6; The grid of output termination the 3rd NMOS tube N3 of hex inverter IV6; The input end of input termination the 3rd phase inverter IV3 of the 7th phase inverter IV7, it exports the input end of termination the 8th phase inverter IV8; The grid of output termination the 4th NMOS tube N4 of the 8th phase inverter IV8.
Beneficial effect of the present invention is, determine and detected the problem of High AC voltage zero crossing, and only used 2 high voltage transistors, all the other transistors used are all normal transistor, save area, there is good Technological adaptability, expand the scope of application of circuit, therefore have that structure is simple, low to requirement on devices, stable working state, be easy to integrated and high voltage bearing advantage.
Accompanying drawing explanation
Fig. 1 is the system chart of high pressure zero cross detection circuit of the present invention;
Fig. 2 is the comparator circuit structural representation in high pressure zero cross detection circuit of the present invention;
Fig. 3 is the electrical block diagram of high pressure zero cross detection circuit of the present invention;
Fig. 4 is the simulation result schematic diagram of high pressure zero cross detection circuit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
High pressure zero cross detection circuit of the present invention, as shown in Figure 1, comprise comparator circuit, logical output circuit and accelerating circuit, described comparator circuit connects external communication input signal, and it exports the input end of termination logical output circuit; The output signal of described logical output circuit feeds back to comparator circuit by accelerating circuit; Wherein,
As shown in Figure 2, described comparator circuit is made up of the first diode D1, the second diode D2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the first PMOS P1, the second PMOS P2, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6; Wherein, the positive pole of the first diode D1 meets first via external communication input signal IN1, and its negative pole connects the drain electrode of the first NMOS tube N1; The grid of the first NMOS tube N1 connects enable signal, and it is by ground connection after the 5th resistance R5; The positive pole of the second diode D2 meets the second road external communication input signal IN2, and its negative pole connects the drain electrode of the second NMOS tube N2; The grid of the second NMOS tube N2 connects enable signal, and its source electrode is by ground connection after the 6th resistance R6; The source electrode of the first PMOS P1 is by connecing the source electrode of the second NMOS tube N2 after the first resistance R1, its grid connects the source electrode of the first NMOS tube N1, its drain electrode drain electrode by meeting the second NMOS tube N3 after the 3rd resistance R3; The source electrode of the second PMOS P2 is by connecing the source electrode of the first NMOS tube N1 after the second resistance R2, its grid connects the source electrode of the second NMOS tube N2, its drain electrode drain electrode by meeting the 4th NMOS tube N4 after the 4th resistance R4; The source ground of the 3rd NMOS tube N3; The source ground of the 4th NMOS tube N4;
Described logical output circuit is made up of the first triode Q1, the second triode Q2, the first phase inverter IV1, the second phase inverter IV2, the 3rd phase inverter IV3, the 4th phase inverter IV4, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9 and the tenth resistance R10; Wherein, the base stage of the first triode Q1 connects the tie point of the 3rd resistance R3 and the 3rd NMOS tube N3, and its collector meets power vd D by the 7th resistance R7, its grounded emitter, and its base stage is by being connected with its emitter after the 9th resistance R9; The input termination first triode Q1 of the second phase inverter IV2 and the tie point of the 7th resistance R7, it exports the input end of termination first phase inverter IV1; The output terminal of the first phase inverter IV1 is the first via output terminal OUT1 of high pressure zero cross detection circuit; The base stage of the second triode Q2 connects the tie point of the drain electrode of the 4th resistance R4 and the 4th NMOS tube N4, and its collector is by meeting power vd D after the 8th resistance R8, its grounded emitter, and its base stage is by connecing its emitter after the tenth resistance R10; The collector of input termination second triode Q2 of the 3rd phase inverter IV3 and the tie point of the 8th resistance R8, it exports the input end of termination the 4th phase inverter IV4; The output terminal of the 4th phase inverter IV4 is the second road output terminal OUT2 of high pressure zero cross detection circuit;
Described accelerating circuit is made up of the 5th phase inverter IV5, hex inverter IV6, the 7th phase inverter IV7, the 8th phase inverter IV8; Wherein, the input end of the input termination second phase inverter IV2 of the 5th phase inverter IV5, it exports the input end of termination hex inverter IV6; The grid of output termination the 3rd NMOS tube N3 of hex inverter IV6; The input end of input termination the 3rd phase inverter IV3 of the 7th phase inverter IV7, it exports the input end of termination the 8th phase inverter IV8; The grid of output termination the 4th NMOS tube N4 of the 8th phase inverter IV8.
Principle of work of the present invention is:
N1, IN2 are two input ends of alternating voltage, so IN1-IN2 is assumed to a sinusoidal voltage (usually always setting up like this), two parts can be divided into: positive half cycle and negative half period, the principle of work of high pressure zero cross detection circuit of the present invention under positive-negative half-cycle situation is discussed respectively below in sinusoidal voltage one-period.When input ac voltage is positioned at positive half cycle, namely during IN1>IN2, be clamped to ground by external device (ED) IN2, enable signal EN is effective, is high level, and now N1, N2 open, and D2 blocks electric current and pours in down a chimney into IN2.Now, the branch road of N1 to R5 has the electric current from IN1, contrary, due to IN2 and ground short circuit, the upper also no current of R6 flows through, and the pressure drop on R6 is zero.Therefore, PMOSFET transistor P1 turns off, PMOSFET transistor P2 then conducting, the electric current from IN1 forms current path through R2, P2, R4 and R10, and R10 produces pressure drop, when base-emitter cut-in voltage higher than bipolar transistor Q2 of the current potential of A2, Q2 conducting, drags down the collector potential of Q2, when its turnover voltage lower than phase inverter IV3, IV3 exports high level, makes logic output signal OUT2 become low level after IV4 shaping.Now, the collector low level of Q2 is still low level after IV7, IV8, and N4 pipe turns off.
And R1, P1, R3 place branch road does not have electric current to flow through, R9 can not produce pressure drop, thus Q1 collector is pulled to supply voltage VDD through resistance R7, after IV1, IV2 shaping, export OUT1 is high level, Q1 collector high level makes N3 pipe open after IV5, IV6 simultaneously, drag down A1 level further, reach the effect accelerating upset.When AC-input voltage IN1-IN2 is positioned at negative half period, duty is just contrary with above-mentioned working condition, the output A1 of comparer core circuit is high level, A2 is low level, A1 makes OUT1 be low level after logic output Shaping, A2 is then by making OUT2 be high level after shaping, IV7, IV8 form the upset of feedback accelerating circuit simultaneously.
Fig. 4 is the simulation result of described high pressure zero cross detection circuit.Simulated conditions is: the sinusoidal voltage of IN1-IN2 to be amplitude be 30V, VDD is 7V DC voltage.As shown in the figure, when IN1-IN2 is positioned at positive half cycle, output OUT1 is high level 7V, OUT2 is low level 0V to simulation result; When IN1-IN2 is positioned at negative half period, output OU1 is high level, and OUT2 is low level, meets the above-mentioned analysis to circuit.
In sum, a kind of high pressure zero cross detection circuit described in the invention can be used in AC-DC change-over circuit, realizes the detection to alternating voltage zero-crossing point.
Claims (1)
1. a high pressure zero cross detection circuit, comprises comparator circuit, logical output circuit and accelerating circuit, and described comparator circuit connects external communication input signal, and it exports the input end of termination logical output circuit; The output signal of described logical output circuit feeds back to comparator circuit by accelerating circuit; Wherein,
Described comparator circuit is made up of the first diode D1, the second diode D2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the first PMOS P1, the second PMOS P2, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6; Wherein, the positive pole of the first diode D1 connects first via external communication input signal, and its negative pole connects the drain electrode of the first NMOS tube N1; The grid of the first NMOS tube N1 connects enable signal, and it is by ground connection after the 5th resistance R5; The positive pole of the second diode D2 connects the second road external communication input signal, and its negative pole connects the drain electrode of the second NMOS tube N2; The grid of the second NMOS tube N2 connects enable signal, and its source electrode is by ground connection after the 6th resistance R6; The source electrode of the first PMOS P1 is by connecing the source electrode of the second NMOS tube N2 after the first resistance R1, its grid connects the source electrode of the first NMOS tube N1, its drain electrode drain electrode by meeting the second NMOS tube N3 after the 3rd resistance R3; The source electrode of the second PMOS P2 is by connecing the source electrode of the first NMOS tube N1 after the second resistance R2, its grid connects the source electrode of the second NMOS tube N2, its drain electrode drain electrode by meeting the 4th NMOS tube N4 after the 4th resistance R4; The source ground of the 3rd NMOS tube N3; The source ground of the 4th NMOS tube N4;
Described logical output circuit is made up of the first triode Q1, the second triode Q2, the first phase inverter IV1, the second phase inverter IV2, the 3rd phase inverter IV3, the 4th phase inverter IV4, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9 and the tenth resistance R10; Wherein, the base stage of the first triode Q1 connects the tie point of the 3rd resistance R3 and the 3rd NMOS tube N3, and its collector meets power vd D by the 7th resistance R7, its grounded emitter, and its base stage is by being connected with its emitter after the 9th resistance R9; The input termination first triode Q1 of the second phase inverter IV2 and the tie point of the 7th resistance R7, it exports the input end of termination first phase inverter IV1; The output terminal of the first phase inverter IV1 is the first via output terminal of high pressure zero cross detection circuit; The base stage of the second triode Q2 connects the tie point of the drain electrode of the 4th resistance R4 and the 4th NMOS tube N4, and its collector is by meeting power vd D after the 8th resistance R8, its grounded emitter, and its base stage is by connecing its emitter after the tenth resistance R10; The collector of input termination second triode Q2 of the 3rd phase inverter IV3 and the tie point of the 8th resistance R8, it exports the input end of termination the 4th phase inverter IV4; The output terminal of the 4th phase inverter IV4 is the second road output terminal of high pressure zero cross detection circuit;
Described accelerating circuit is made up of the 5th phase inverter IV5, hex inverter IV6, the 7th phase inverter IV7, the 8th phase inverter IV8; Wherein, the input end of the input termination second phase inverter IV2 of the 5th phase inverter IV5, it exports the input end of termination hex inverter IV6; The grid of output termination the 3rd NMOS tube N3 of hex inverter IV6; The input end of input termination the 3rd phase inverter IV3 of the 7th phase inverter IV7, it exports the input end of termination the 8th phase inverter IV8; The grid of output termination the 4th NMOS tube N4 of the 8th phase inverter IV8.
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| CN201510410421.6A CN105116209A (en) | 2015-07-14 | 2015-07-14 | High voltage zero-crossing detection circuit |
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| CN201510410421.6A CN105116209A (en) | 2015-07-14 | 2015-07-14 | High voltage zero-crossing detection circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105974185A (en) * | 2016-06-23 | 2016-09-28 | 电子科技大学 | Zero cross detection circuit |
| CN106199156A (en) * | 2016-06-23 | 2016-12-07 | 电子科技大学 | A kind of exchange commutation detection circuit |
| CN110398622A (en) * | 2018-04-24 | 2019-11-01 | 艾普凌科有限公司 | Zero cross detection circuit and sensor device |
| CN112816767A (en) * | 2021-02-26 | 2021-05-18 | 西安微电子技术研究所 | Inductive current zero-crossing detection circuit and method |
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| CN104639122A (en) * | 2015-01-28 | 2015-05-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | Zero cross detection circuit for eliminating high frequency burrs |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105974185A (en) * | 2016-06-23 | 2016-09-28 | 电子科技大学 | Zero cross detection circuit |
| CN106199156A (en) * | 2016-06-23 | 2016-12-07 | 电子科技大学 | A kind of exchange commutation detection circuit |
| CN106199156B (en) * | 2016-06-23 | 2018-10-26 | 电子科技大学 | A kind of exchange commutation detection circuit |
| CN110398622A (en) * | 2018-04-24 | 2019-11-01 | 艾普凌科有限公司 | Zero cross detection circuit and sensor device |
| CN112816767A (en) * | 2021-02-26 | 2021-05-18 | 西安微电子技术研究所 | Inductive current zero-crossing detection circuit and method |
| CN112816767B (en) * | 2021-02-26 | 2023-08-08 | 西安微电子技术研究所 | Inductance current zero-crossing detection circuit and method |
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Application publication date: 20151202 |