CN206348782U - ETS voting cards based on FPGA architecture - Google Patents
ETS voting cards based on FPGA architecture Download PDFInfo
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- CN206348782U CN206348782U CN201621465383.0U CN201621465383U CN206348782U CN 206348782 U CN206348782 U CN 206348782U CN 201621465383 U CN201621465383 U CN 201621465383U CN 206348782 U CN206348782 U CN 206348782U
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Abstract
A kind of ETS voting cards based on FPGA architecture, are related to steam turbine technology field, and what is solved is that existing system can not realize the voting logic of complexity and decide by vote the technical problem of time length.The voting card includes FPGA votings module, IOP processing modules, the first connector, the second connector；Each railway digital signal input interface, each railway digital signal output interface of first connector are coupled with each railway digital signal input port, each railway digital signal output port that FPGA decides by vote module；The LVDS sending ports of FPGA voting modules, each road LVDS receiving ports, each road communication port are coupled with the LVDS transmission interfaces, each road LVDS receiving ports, each road serial communication interface of the second connector；Provided with FPGA processing submodule, CPU submodules in the IOP processing modules.The voting card that the utility model is provided, it is adaptable to ETS systems.
Description
Technical field
The utility model is related to steam turbine technology, the technology of more particularly to a kind of ETS voting cards based on FPGA architecture.
Background technology
ETS systems（Turbine emergency interrupting system）In the steam turbine operation control room for being all disposed within thermal power plant, nuclear power plant.
At present, ETS systems are all to realize voting logic using mechanical relay, it is necessary to build table by multiple relays
Certainly logic, the defect that can not be changed with dumb and logic, it is impossible to realize complicated voting logic, and delay time is long,
System response time is slow, influences whether the operation safety of turbine system.
The content of the invention
For defect present in above-mentioned prior art, technical problem to be solved in the utility model is to provide a kind of energy
The complicated voting logic of the realization of fast and flexible, and decide by vote the time short ETS voting cards based on FPGA architecture.
In order to solve the above-mentioned technical problem, a kind of ETS voting cards based on FPGA architecture provided by the utility model, its
It is characterised by：Including FPGA votings module, IOP processing modules, the first connector, the second connector；
The FPGA votings module is provided with multi-path digital signal input port, multi-path digital signal output port, multichannel string
Row COM1,1 road LVDS sending ports, multichannel LVDS receiving ports；
First connector has multi-path digital signal input interface, multi-path digital signal output interface, the first connection
Each railway digital signal input interface of part is each to be coupled with each way that FPGA decides by vote module through a digital signal transmission passage
Word signal input port, each railway digital signal output port of FPGA voting modules is each to be distinguished through a digital signal transmission passage
It is connected to each railway digital signal output interface of the first connector；
Second connector has multi-path serial communication interface, 1 road LVDS transmission interfaces, multichannel LVDS receiving ports,
Each each road for being coupled with FPGA voting modules through a serial-port of each road serial communication interface of second connector serially leads to
Believe port, the LVDS transmissions that the LVDS sending ports of FPGA voting modules are connected to the second connector through a LVDS transmission channels connect
Mouthful, each road LVDS receiving ports of the second connector are each to be coupled with each road that FPGA decides by vote module through a LVDS transmission channel
LVDS receiving ports；
Provided with FPGA processing submodule, CPU submodules in the IOP processing modules, FPGA processing submodule warp therein
Data wire and FPGA voting module interconnections, and FPGA processing submodules are provided with multi-path digital signal input port, the first connection
Each railway digital signal input interface of part is each to be coupled with each road that FPGA handles submodule through a digital signal transmission passage
Digital signal input end mouthful, FPGA processing submodules are interconnected with CPU submodules through data/address bus.
The voting cards of the ETS based on FPGA architecture that the utility model is provided, it is double superfluous using Multipath digital quantity input and multichannel
Remaining digital output goes the operation of the execution units such as field control magnetic valve, and decides by vote module completion to input numeral by FPGA
The voting of signal, tach signal, can fast and flexible the complicated voting logic of realization, and decide by vote that the time is short, voting logic may be used also
So that according to concrete application editor, the operation safety of turbine system can be effectively protected.
Brief description of the drawings
Fig. 1 is the structural representation of the voting cards of the ETS based on FPGA architecture of the utility model embodiment.
Embodiment
Below in conjunction with brief description of the drawings embodiment of the present utility model is described in further detail, but the present embodiment and without
It is every to use similar structure of the present utility model and its similar change in limitation the utility model, the utility model all should be included in
Protection domain, the pause mark in the utility model represents the relation of sum.
As shown in figure 1, a kind of ETS voting cards based on FPGA architecture that the utility model embodiment is provided, its feature
It is：Including FPGA voting module U1, IOP processing modules U2（Input and output processing module）, the first connector J1, second connection
Part J2；
The FPGA voting module U1 are serial provided with 6 railway digital signal input ports, 8 railway digital signal output ports, 3 roads
COM1,1 road LVDS sending ports（Low-voltage differential signal sending port）, 10 road LVDS receiving ports（Low voltage difference
Receiver port）；
The first connector J1 has 6 railway digital signal input interfaces, 8 railway digital signal output interfaces, the first connection
Part J1 6 railway digital signal input interfaces are each to be coupled with the 6 of FPGA voting modules U1 through a numeral signal transmission passage DI
Railway digital signal input port, FPGA voting modules U1 8 railway digital signal output ports are each logical through a digital data transmission
Road DO is coupled with the first connector J1 8 railway digital signal output interfaces；
The second connector J2 has 3 road serial communication interfaces, 1 road LVDS transmission interfaces, 10 road LVDS receiving ports,
Second connector J2 3 road serial communication interfaces are each to go here and there through a serial-port C1 3 tunnels for being coupled with FPGA voting modules U1
Row COM1, FPGA voting modules U1 LVDS sending ports are connected to the second connector J2's through a LVDS transmission channels L_TX
LVDS transmission interfaces, the second connector J2 10 road LVDS receiving ports are respectively coupled with through a LVDS transmission channels L_RX
FPGA voting modules U1 10 road LVDS receiving ports；
Provided with FPGA processing submodule U21, CPU submodules U22 in the IOP processing modules U2（Microprocessor submodule
Block）, FPGA processing submodule U21 therein decide by vote module U1 through data wire and FPGA and interconnected, and FPGA processing submodules U21
Provided with 6 railway digital signal input ports, the first connector J1 6 railway digital signal input interfaces are each through a digital data transmission
Passage DI is coupled with FPGA processing submodules U21 6 railway digital signal input ports, FPGA processing submodule U21 and CPU
Module U22 is interconnected through data/address bus.
In the utility model embodiment, the digital data transmission passage, serial-port, LVDS transmission channels are existing
Technology, digital data transmission passage is the signal circuit for transmitting data signal, and serial-port is to be used to transmit serially
The signal circuit of communication data, LVDS transmission channels are used to transmit LVDS signals（Low-voltage differential signal）.
In the utility model embodiment, the IOP processing modules are prior art, and IOP processing modules are one piece general
Processor plate, can be widely used among different types of IO cards.
The utility model embodiment coordinates signal distribution card to use, and connects 3 tunnel serial communications of the second connector when using
Mouth is connected to the serial communication interface of external devices, the communication of FPGA voting modules and external devices is realized, by the second connector
LVDS transmission interfaces and 10 road LVDS receiving ports be coupled with signal distribution card LVDS transmitting-receiving port, FPGA voting module
LVDS signals are sent to signal distribution card by LVDS transmission interfaces, signal distribution card is received by 10 road LVDS receiving ports
LVDS signals；
6 railway digital signal input interfaces of the first connector are respectively connected to the sampled data of outside input, transfer to FPGA tables
Certainly module is analyzed and processed, and FPGA decides by vote module according to result, exports corresponding by 8 railway digital signal output interfaces
The operation of relevant device in control signal, control turbine system；
In IOP processing modules, FPGA processing submodules mainly undertake I/O signal（Input/output signal）Processing, pass through number
Communicated according to bus with CPU submodules, realize interacting for on-site signal and CPU submodules, CPU submodules are responsible for FPGA voting modules
And FPGA handles the functions such as configuration, the network service of submodule.
Claims (1)
1. a kind of ETS voting cards based on FPGA architecture, it is characterised in that：Including FPGA votings module, IOP processing modules, the
A connection piece, the second connector；
The FPGA voting modules are led to provided with multi-path digital signal input port, multi-path digital signal output port, multi-path serial
Believe port, 1 road LVDS sending ports, multichannel LVDS receiving ports；
First connector has multi-path digital signal input interface, multi-path digital signal output interface, the first connector
Each each railway digital for being coupled with FPGA voting modules through a digital signal transmission passage of each railway digital signal input interface is believed
Number input port, each railway digital signal output port of FPGA voting modules is each to be coupled with through a digital signal transmission passage
Each railway digital signal output interface of first connector；
Second connector has multi-path serial communication interface, 1 road LVDS transmission interfaces, multichannel LVDS receiving ports, second
Each road serial communication interface of connector is each to be coupled with each road serial communication end that FPGA decides by vote module through a serial-port
Mouthful, the LVDS sending ports of FPGA voting modules are connected to the LVDS transmission interfaces of the second connector through a LVDS transmission channels, the
Each road LVDS receiving ports of two connectors are each to be coupled with each road LVDS that FPGA decides by vote module through a LVDS transmission channel
Receiving port；
Provided with FPGA processing submodule, CPU submodules in the IOP processing modules, FPGA therein handles submodule through data
Line and FPGA voting module interconnections, and FPGA processing submodules are provided with multi-path digital signal input port, the first connector
Each railway digital signal input interface is each to be coupled with each railway digital that FPGA handles submodule through a digital signal transmission passage
Signal input port, FPGA processing submodules are interconnected with CPU submodules through data/address bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621465383.0U CN206348782U (en) | 2016-12-29 | 2016-12-29 | ETS voting cards based on FPGA architecture |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621465383.0U CN206348782U (en) | 2016-12-29 | 2016-12-29 | ETS voting cards based on FPGA architecture |
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| Publication Number | Publication Date |
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| CN206348782U true CN206348782U (en) | 2017-07-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106649160A (en) * | 2016-12-29 | 2017-05-10 | 国核自仪***工程有限公司 | ETS voting card based on FPGA architecture |
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2016
- 2016-12-29 CN CN201621465383.0U patent/CN206348782U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106649160A (en) * | 2016-12-29 | 2017-05-10 | 国核自仪***工程有限公司 | ETS voting card based on FPGA architecture |
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