CN103944707B - Full duplex and half-duplex converter and conversion method - Google Patents
Full duplex and half-duplex converter and conversion method Download PDFInfo
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- CN103944707B CN103944707B CN201410198632.3A CN201410198632A CN103944707B CN 103944707 B CN103944707 B CN 103944707B CN 201410198632 A CN201410198632 A CN 201410198632A CN 103944707 B CN103944707 B CN 103944707B
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Abstract
Full duplex and half-duplex converter and conversion method, are related to full duplex and half-duplex operation compatible technique.When its data processing card for solution using RS422 serial communications is directly communicated with the data acquisition card using RS485 serial communications, there is a problem of that loss of data or the bit error rate are high.The present invention is provided with triple gate integrated circuit between half-duplex signal acquisition module and full-duplex data processing module, realizes the transmitting terminal of the serial ports of data processing card 422 and the physical isolation of receiving terminal.By way of each functional module that software is realized receives data feedback mark by inquire-receive module, full and half duplex port communication compatibling problem is solved, in the absence of loss of data and error code phenomenon, it is ensured that the accuracy of data transmit-receive.The present invention is applicable for use with the data processing card of RS422 serial communications and using the communication between the data acquisition card of RS485 serial communications.
Description
Technical field
The present invention relates to full duplex and half-duplex operation compatible technique.
Background technology
As the development of the communication technology, communication form are more and more, become increasingly complex, during signal communication, one
As all use half-duplex and full-duplex communication mode.In the more complex control system of communication interface, it is contemplated that communication interface
Compatibility, data processing card typically uses the full-duplex communication mode based on RS422；Based on transmission speed, distance and net
The demands, the more half-duplex operation mode used based on RS485 of present signal acquisition product such as networkization communication.When being based on
The data processing card of the use RS422 serial communications of self-demand design is straight with the data acquisition card using RS485 serial communications
When tapping into row communication, can there are problems that two：First, sent to data acquisition card in the instruction transmitting terminal of data processing card and read
During data are read in instruction, half-duplex interface has that instruction input is conflicting with data output；Second, Quan Shuan
The receiving terminal of work interface has that data are mixed with input with instruction.Data are transmitted and received and half-duplex operation mode simultaneously
It is contradiction, loss of data or bit error rate problem high can be caused.
The content of the invention
Data processing card the invention aims to solve using RS422 serial communications is led to using RS485 serial ports
When the data acquisition card of letter is directly communicated, there is a problem of that loss of data or the bit error rate are high, there is provided a kind of full duplex and half
Duplexer and conversion method.
At full duplex of the present invention and half-duplex converter, including half-duplex signal acquisition module, full-duplex data
Reason module and triple gate integrated circuit, the full-duplex data processing module include physical layer receiving terminal, physical layer transmitting terminal and
Fpga chip；
Described half-duplex signal acquisition module is using the realization of RS485 chips, described physical layer receiving terminal and physical layer
Transmitting terminal is realized using 422 serial port drive modules；
The data-signal that the 422R+ ports and 422R- ports of physical layer receiving terminal connect triple gate integrated circuit respectively is defeated
Go out+port and data-signal output-port, the 422T+ ports and 422T- ports of physical layer transmitting terminal connect triple gate collection respectively
Into the command signal input+port of circuit and command signal input-port, the I/O+ ports and I/O- ends of triple gate integrated circuit
Mouth connects the 485+ ports and 485- ports of half-duplex signal acquisition module respectively；
The triple gate of fpga chip enables the enable signal input part that signal output part connects triple gate integrated circuit；
The fpga chip be embedded in software realization data reception module, dual port RAM module, calculation process module and
Instruction sending module；
Described data reception module is included with lower unit：
Low level gating signal transmitting element：For sending low level gating signal to triple gate integrated circuit, and at this
Log-on data reads instruction sending unit after unit end of run；
High level cut-off signals transmitting element：For sending high level cut-off signals to triple gate integrated circuit, and at this
Log-on data receives enabler flags transmitting element after unit end of run；
Data receipt unit：It is for receiving the data that physical layer receiving terminal is sent and same after the unit end of run
When log-on data memory cell and instruction send enabler flags transmitting element；
Data storage cell：Data is activation to dual port RAM module for physical layer receiving terminal to be sent is stored, and
The log-on data processing unit after the unit end of run；
Instruction sends enabler flags transmitting element：Enabler flags are sent for sending to instruct to instruction sending module, and
Enabled instruction sends enabler flags judging unit after the unit end of run；
The data that described dual port RAM module is used to send data reception module are stored；
Described instruction sending module is included with lower unit：
Data read command transmitting element：For sending data read command to physical layer transmitting terminal, and in unit fortune
Row starts high level cut-off signals transmitting element after terminating；
Data receiver enabler flags transmitting element：For to data reception module send data receiver enabler flags, and
Log-on data receiving unit after the unit end of run；
Instruction sends enabler flags judging unit：For judging whether that receiving instruction sends enabler flags, and judging to tie
Fruit is terminated full duplex when judged result is no and is changed with half-duplex to start low level gating signal transmitting element when being；
Described calculation process module is included with lower unit：
Data processing unit：For calling the data in dual port RAM module, the data are processed, and in the unit
Log-on data computing judging unit after end of run；
Data operation judging unit：It is for judging whether data operation finishes and complete double to terminate when being in judged result
Work is changed with half-duplex, and when judged result is no, enabled instruction sends mark judging unit.
Full duplex of the present invention is realized with half-duplex conversion method based on following conversion equipments：The conversion equipment
Including half-duplex signal acquisition module, full-duplex data processing module and triple gate integrated circuit, the full-duplex data treatment
Module includes physical layer receiving terminal, physical layer transmitting terminal and fpga chip；
Described half-duplex signal acquisition module is using the realization of RS485 chips, described physical layer receiving terminal and physical layer
Transmitting terminal is realized using 422 serial port drive modules；
The data-signal that the 422R+ ports and 422R- ports of physical layer receiving terminal connect triple gate integrated circuit respectively is defeated
Go out+port and data-signal output-port, the 422T+ ports and 422T- ports of physical layer transmitting terminal connect triple gate collection respectively
Into the command signal input+port of circuit and command signal input-port, the I/O+ ports and I/O- ends of triple gate integrated circuit
Mouth connects the 485+ ports and 485- ports of half-duplex signal acquisition module respectively；
The triple gate of fpga chip enables the enable signal input part that signal output part connects triple gate integrated circuit；
The fpga chip includes data reception module, dual port RAM module, calculation process module and instruction sending module；
The full duplex is comprised the following steps with half-duplex conversion method：
Low level gating signal forwarding step：Data reception module sends low level gating letter to triple gate integrated circuit
Number, and data read command forwarding step is performed after the step terminates；
Data read command forwarding step：Instruction sending module to physical layer transmitting terminal send data read command, and
The step performs high level cut-off signals forwarding step after terminating；
High level cut-off signals forwarding step：Data reception module sends high level shut-off letter to triple gate integrated circuit
Number, and data receiver enabler flags forwarding step is performed after the step terminates；
Data receiver enabler flags forwarding step：Instruction sending module sends data receiver and enables mark to data reception module
Will, and data reception step is performed after the step terminates；
Data reception step：Data reception module receives the data that physical layer receiving terminal is sent, and terminates it in the step
Data storing steps are performed simultaneously afterwards and instruction sends enabler flags forwarding step；
Data storing steps：The data is activation that data reception module sends physical layer receiving terminal to dual port RAM module is entered
Row storage, and data processing step is performed after the step terminates；
Data processing step：Calculation process module calls the data in dual port RAM module, and the data are processed, and
Data operation is performed after the step terminates and judges step；
Data operation judges step：Calculation process module judges whether data operation finishes, and when judged result is to be
Terminate full duplex and half-duplex conversion method, execute instruction transmission mark judges step when judged result is no；
Instruction sends enabler flags forwarding step：Data reception module sends instruction and sends enable mark to instruction sending module
Will, and execute instruction transmission enabler flags judge step after the step terminates；
Instruction sends enabler flags and judges step：Instruction sending module judges whether that receiving instruction sends enabler flags, and
Low level gating signal forwarding step is performed when judged result is to be, full duplex and half-duplex are terminated when judged result is no
Conversion method.
Full duplex of the present invention and half-duplex converter and conversion method, it is double with complete in half-duplex signal acquisition module
Triple gate integrated circuit is provided between work data processing module, what the RS422 of full-duplex data processing module sent and received
Bipolar differential end is carried out with the RS485 bipolar differentials end of half-duplex signal acquisition module respectively by triple gate integrated circuit
Correspondence connection, realizes the transmitting terminal of the serial ports of data processing card 422 and the physical isolation of receiving terminal.Each work(realized by software
Energy module solves full and half duplex port communication compatible by way of inquire-receive module receives data feedback mark
Problem, in the absence of loss of data and error code phenomenon, it is ensured that the accuracy of data transmit-receive.
Brief description of the drawings
Fig. 1 is the theory diagram of the full duplex in implementation method one and implementation method three and half-duplex converter；
Fig. 2 is the logical circuitry of the triple gate integrated circuit in implementation method two and implementation method four；
Fig. 3 is the flow chart of the full duplex described in implementation method three and half-duplex conversion method.
Specific embodiment
Specific embodiment one：Present embodiment is illustrated with reference to Fig. 1, the full duplex described in present embodiment turns with half-duplex
Parallel operation, including half-duplex signal acquisition module 1, full-duplex data processing module 2 and triple gate integrated circuit 3, the full duplex
Data processing module 2 includes physical layer receiving terminal 2-1, physical layer transmitting terminal 2-2 and fpga chip 2-3；
Described half-duplex signal acquisition module 1 is using the realization of RS485 chips, described physical layer receiving terminal 2-1 and thing
Reason layer transmitting terminal 2-2 is realized using 422 serial port drive modules；
The 422R+ ports and 422R- ports of physical layer receiving terminal 2-1 connect the data letter of triple gate integrated circuit 3 respectively
Number output+port and data-signal output-port, the 422T+ ports and 422T- ports of physical layer transmitting terminal 2-2 connect respectively
Command signal input+the port of triple gate integrated circuit 3 and command signal input-port, the I/O+ ends of triple gate integrated circuit 3
Mouth and I/O- ports connect the 485+ ports and 485- ports of half-duplex signal acquisition module 1 respectively；
The triple gate of fpga chip 2-3 enables the enable signal input part of signal output part connection triple gate integrated circuit 3；
The fpga chip 2-3 be embedded in software realization data reception module 2-3-1, dual port RAM module 2-3-2,
Calculation process module 2-3-3 and instruction sending module 2-3-4；
Described data reception module 2-3-1 is included with lower unit：
Low level gating signal transmitting element：For sending low level gating signal to triple gate integrated circuit 3, and at this
Log-on data reads instruction sending unit after unit end of run；
High level cut-off signals transmitting element：For sending high level cut-off signals to triple gate integrated circuit 3, and at this
Log-on data receives enabler flags transmitting element after unit end of run；
Data receipt unit：For receiving the data that physical layer receiving terminal 2-1 sends, and after the unit end of run
Log-on data memory cell and instruction simultaneously sends enabler flags transmitting element；
Data storage cell：Enter for the data is activation of sending physical layer receiving terminal 2-1 to dual port RAM module 2-3-2
Row storage, and the log-on data processing unit after the unit end of run；
Instruction sends enabler flags transmitting element：Enabler flags are sent for sending instruction to instruction sending module 2-3-4,
And enabled instruction sends enabler flags judging unit after the unit end of run；
Described dual port RAM module 2-3-2 is used to be stored the data that data reception module 2-3-1 sends；
Described instruction sending module 2-3-4 is included with lower unit：
Data read command transmitting element：For sending data read command to physical layer transmitting terminal 2-2, and in the unit
High level cut-off signals transmitting element is opened after end of run；
Data receiver enabler flags transmitting element：For sending data receiver enabler flags to data reception module 2-3-1,
And after the unit end of run log-on data receiving unit；
Instruction sends enabler flags judging unit：For judging whether that receiving instruction sends enabler flags, and judging to tie
Fruit is terminated full duplex when judged result is no and is changed with half-duplex to start low level gating signal transmitting element when being；
Described calculation process module 2-3-3 is included with lower unit：
Data processing unit：For calling the data in dual port RAM module 2-3-2, the data are processed, and at this
Log-on data computing judging unit after unit end of run；
Data operation judging unit：It is for judging whether data operation finishes and complete double to terminate when being in judged result
Work is changed with half-duplex, and when judged result is no, enabled instruction sends mark judging unit.
Full duplex described in present embodiment is with half-duplex converter in half-duplex signal acquisition module 1 and full-duplex data
Triple gate integrated circuit 3 is provided between processing module 2, it is bipolar that the RS422 of full-duplex data processing module 2 sends and receives
It is right that property differential ends are carried out with the RS485 bipolar differentials end of half-duplex signal acquisition module 1 respectively by triple gate integrated circuit 3
Should connect, realize the transmitting terminal of the serial ports of data processing card 422 and the physical isolation of receiving terminal.Each function of being realized by software
Module solves full and half duplex port communication compatibility and asks by way of inquire-receive module receives data feedback mark
Topic, in the absence of loss of data and error code phenomenon, it is ensured that the accuracy of data transmit-receive.
Full duplex described in present embodiment is as follows with the operation principle of half-duplex converter：Before data transfer, enter first
Row resets, and during reset, the data reception module 2-3-1 of full-duplex data processing module 2 sends low electricity to triple gate integrated circuit 3
Ordinary mail number；The instruction sending module 2-3-4 of full-duplex data processing module 2 is by the physical layer transmitting terminal 2-2 of 422 serial ports by number
The physical layer transceiver end of 485 serial ports of half-duplex signal acquisition module 1 is sent to according to reading instruction；Data read command is a string
Code, when instruction sending module 2-3-4 detects the end of the code, it is believed that data read command is sent, now,
Data reception module 2-3-1 sends high level cut-off signals to triple gate integrated circuit 3；Half-duplex signal acquisition module 1 is to number
Data receiver enabler flags are sent according to receiver module 2-3-1, shows that reading instruction sends successfully；Half-duplex signal acquisition module 1
The data read command that response is received, is gone here and there by the physical layer transceiver end of 485 serial ports to the 422 of full-duplex data processing module 2
The physical layer receiving terminal 2-1 of mouth sends data；The data that physical layer receiving terminal 2-1 will be received are transmitted to data reception module 2-3-
1；The data storage that data reception module 2-3-1 will be received in dual port RAM module 2-3-2, calculation process module 2-3-3 from
The data are called to be processed in dual port RAM module 2-3-2；Data reception module 2-3-1 sends to instruction sending module 2-3-4
Data is activation enabler flags, show that data reception module 2-3-1 receives data success；Instruction sending module 2-3-4 receives data
After sending enabler flags, repeat the above steps, until data transmit-receive terminates.Instruction sending module 2-3-4 and data reception module
The enabler flags that 2-3-1 sends mutually are high level pulse signal.
Specific embodiment two：With reference to Fig. 1 and Fig. 2 explanation present embodiments, present embodiment is to the institute of implementation method one
The further restriction of the full duplex stated and half-duplex converter, in present embodiment, described triple gate integrated circuit 3 includes the
One triple gate 3-1, the second triple gate 3-2, the 3rd triple gate 3-3, the 4th triple gate 3-4 and not gate 3-5；
The enable letter for enabling signal end and the second triple gate 3-2 of the input of the not gate 3-5, the first triple gate 3-1
Number end links together, and used as the enable signal input part of triple gate integrated circuit 3, the output end of not gate 3-5 connects the simultaneously
The enable signal end for enabling signal end and the 4th triple gate 3-4 of three triple gate 3-3；
The 422T+ ports of the input connection physical layer transmitting terminal 2-2 of the first triple gate 3-1, the second triple gate 3-2's is defeated
Enter the 422T- ports that end connects physical layer transmitting terminal 2-2, the input connection physical layer receiving terminal 2-1's of the 3rd triple gate 3-3
422R+ ports, the 422R- ports of the input connection physical layer receiving terminal 2-1 of the 4th triple gate 3-4；
The output end of the first triple gate 3-1 is connected half-duplex signal collection mould simultaneously with the output end of the 3rd triple gate 3-3
The 485+ ports of block 1, the output end of the second triple gate 3-2 is connected half-duplex signal simultaneously with the output end of the 4th triple gate 3-4
The 485- ports of acquisition module 1.
Be integrated together for four triple gates by the triple gate integrated circuit 3 in present embodiment, and fpga chip 2-3 passes through three
State door enables the low level gating signal that is sent to triple gate integrated circuit 3 of signal output part, the signal by after not gate 3-5 into
It is the high level cut-off signals of the 3rd triple gate 3-3 and the 4th triple gate 3-4, now physical layer transmitting terminal 2-2 passes through the one or three
State door 3-1 and the second triple gate 3-2 sends instruction to the physical layer transceiver end of half-duplex signal acquisition module 1；Instruction has sent
Bi Hou, fpga chip 2-3 sends high level cut-off signals to triple gate integrated circuit 3, and the signal is the first triple gate 3-1 and the
Two triple gate 3-2 high level cut-off signals, but the signal is by after not gate 3-5, as the 3rd triple gate 3-3 and the 4th triple gate
The low level gating signal of 3-4, now the physical layer transceiver end of half-duplex signal acquisition module 1 by the 3rd triple gate 3-3 and
4th triple gate 3-4 sends data to physical layer receiving terminal 2-1.
Triple gate integrated circuit 3 in present embodiment realizes the transmitting terminal and receiving terminal of the serial ports of data processing card 422
Physical isolation, to a certain extent ensure data transmit-receive accuracy.
Specific embodiment three：With reference to Fig. 1 and Fig. 3 explanation present embodiments, the full duplex and half described in present embodiment
Duplexing conversion method is realized based on following conversion equipments：The conversion equipment includes half-duplex signal acquisition module 1, full duplex
Data processing module 2 and triple gate integrated circuit 3, the full-duplex data processing module 2 include physical layer receiving terminal 2-1, thing
Reason layer transmitting terminal 2-2 and fpga chip 2-3；
Described half-duplex signal acquisition module 1 is using the realization of RS485 chips, described physical layer receiving terminal 2-1 and thing
Reason layer transmitting terminal 2-2 is realized using 422 serial port drive modules；
The 422R+ ports and 422R- ports of physical layer receiving terminal 2-1 connect the data letter of triple gate integrated circuit 3 respectively
Number output+port and data-signal output-port, the 422T+ ports and 422T- ports of physical layer transmitting terminal 2-2 connect respectively
Command signal input+the port of triple gate integrated circuit 3 and command signal input-port, the I/O+ ends of triple gate integrated circuit 3
Mouth and I/O- ports connect the 485+ ports and 485- ports of half-duplex signal acquisition module 1 respectively；
The triple gate of fpga chip 2-3 enables the enable signal input part of signal output part connection triple gate integrated circuit 3；
The fpga chip 2-3 includes data reception module 2-3-1, dual port RAM module 2-3-2, calculation process module 2-
3-3 and instruction sending module 2-3-4；
The full duplex is comprised the following steps with half-duplex conversion method：
Low level gating signal forwarding step：Data reception module 2-3-1 sends low level and selects to triple gate integrated circuit 3
Messenger, and data read command forwarding step is performed after the step terminates；
Data read command forwarding step：Instruction sending module 2-3-4 sends digital independent and refers to physical layer transmitting terminal 2-2
Order, and high level cut-off signals forwarding step is performed after the step terminates；
High level cut-off signals forwarding step：Data reception module 2-3-1 sends high level and closes to triple gate integrated circuit 3
Break signal, and data receiver enabler flags forwarding step is performed after the step terminates；
Data receiver enabler flags forwarding step：Instruction sending module 2-3-4 sends data to data reception module 2-3-1
Enabler flags are received, and data reception step is performed after the step terminates；
Data reception step：Data reception module 2-3-1 receives the data that physical layer receiving terminal 2-1 sends, and in the step
It is rapid to terminate to perform data storing steps and instruction transmission enabler flags forwarding step simultaneously afterwards；
Data storing steps：The data is activation that data reception module 2-3-1 sends physical layer receiving terminal 2-1 is to twoport
RAM module 2-3-2 is stored, and data processing step is performed after the step terminates；
Data processing step：Calculation process module 2-3-3 calls the data in dual port RAM module 2-3-2, and the data are entered
Row treatment, and execution data operation judges step after the step terminates；
Data operation judges step：Calculation process module 2-3-3 judges whether data operation finishes, and is in judged result
Terminate full duplex and half-duplex conversion method when being, execute instruction transmission mark judges step when judged result is no；
Instruction sends enabler flags forwarding step：Data reception module 2-3-1 sends to instruction sending module 2-3-4 and instructs
Enabler flags are sent, and execute instruction transmission enabler flags judge step after the step terminates；
Instruction sends enabler flags and judges step：Instruction sending module 2-3-4 judges whether that receiving instruction sends enable mark
Will, and judged result for be when perform low level gating signal forwarding step, judged result for it is no when terminate full duplex with
Half-duplex conversion method.
Full duplex and half-duplex conversion method described in present embodiment, in half-duplex signal acquisition module 1 and full duplex
Triple gate integrated circuit 3 is provided between data processing module 2, what the RS422 of full-duplex data processing module 2 sent and received
Bipolar differential end is entered with the RS485 bipolar differentials end of half-duplex signal acquisition module 1 respectively by triple gate integrated circuit 3
Row correspondence connection, realizes the transmitting terminal of the serial ports of data processing card 422 and the physical isolation of receiving terminal.By each of software realization
Functional module solves full and half duplex port communication simultaneous by way of inquire-receive module receives data feedback mark
Appearance problem, in the absence of loss of data and error code phenomenon, it is ensured that the accuracy of data transmit-receive.
Before data transfer, resetted first, during reset, the data reception module 2-3-1 of full-duplex data processing module 2
Low level signal is sent to triple gate integrated circuit 3；The physical layer transmitting terminal that full-duplex data processing module 2 passes through 422 serial ports
Data read command is sent to 2-2 the physical layer transceiver end of 485 serial ports of half-duplex signal acquisition module 1；Digital independent refers to
After order is sent, data reception module 2-3-1 sends high level cut-off signals to triple gate integrated circuit 3；Half-duplex signal
Acquisition module 1 sends data receiver enabler flags to data reception module 2-3-1, shows that reading instruction sends successfully；Half-duplex
Signal acquisition module 1 responds the data read command for receiving, and is processed to full-duplex data by the physical layer transceiver end of 485 serial ports
The physical layer receiving terminal 2-1 of 422 serial ports of module 2 sends data；The data that physical layer receiving terminal 2-1 will be received are transmitted to data
Receiver module 2-3-1；The data storage that data reception module 2-3-1 will be received in dual port RAM module 2-3-2, at computing
Reason module 2-3-3 calls the data to be processed from dual port RAM module 2-3-2；Data reception module 2-3-1 sends to instruction
Module 2-3-4 sends data is activation enabler flags, shows that data reception module 2-3-1 receives data success；Instruction sending module
After 2-3-4 receives data is activation enabler flags, repeat the above steps, until data transmit-receive terminates.Instruction sending module 2-3-4 with
The enabler flags that data reception module 2-3-1 sends mutually are high level pulse signal.
Specific embodiment four：With reference to Fig. 1 and Fig. 2 explanation present embodiments, present embodiment is to the institute of implementation method three
The further restriction of the full duplex and half-duplex conversion method stated, in present embodiment, described triple gate integrated circuit 3 includes
First triple gate 3-1, the second triple gate 3-2, the 3rd triple gate 3-3, the 4th triple gate 3-4 and not gate 3-5；
The enable letter for enabling signal end and the second triple gate 3-2 of the input of the not gate 3-5, the first triple gate 3-1
Number end links together, and used as the enable signal input part of triple gate integrated circuit 3, the output end of not gate 3-5 connects the simultaneously
The enable signal end for enabling signal end and the 4th triple gate 3-4 of three triple gate 3-3；
The 422T+ ports of the input connection physical layer transmitting terminal 2-2 of the first triple gate 3-1, the second triple gate 3-2's is defeated
Enter the 422T- ports that end connects physical layer transmitting terminal 2-2, the input connection physical layer receiving terminal 2-1's of the 3rd triple gate 3-3
422R+ ports, the 422R- ports of the input connection physical layer receiving terminal 2-1 of the 4th triple gate 3-4；
The output end of the first triple gate 3-1 is connected half-duplex signal collection mould simultaneously with the output end of the 3rd triple gate 3-3
The 485+ ports of block 1, the output end of the second triple gate 3-2 is connected half-duplex signal simultaneously with the output end of the 4th triple gate 3-4
The 485- ports of acquisition module 1.
Be integrated together for four triple gates by the triple gate integrated circuit 3 in present embodiment, and fpga chip 2-3 passes through three
State door enables the low level gating signal that is sent to triple gate integrated circuit 3 of signal output part, the signal by after not gate 3-5 into
It is the high level cut-off signals of the 3rd triple gate 3-3 and the 4th triple gate 3-4, now physical layer transmitting terminal 2-2 passes through the one or three
State door 3-1 and the second triple gate 3-2 sends instruction to the physical layer transceiver end of half-duplex signal acquisition module 1；Instruction has sent
Bi Hou, fpga chip 2-3 sends high level cut-off signals to triple gate integrated circuit 3, and the signal is the first triple gate 3-1 and the
Two triple gate 3-2 high level cut-off signals, but the signal is by after not gate 3-5, as the 3rd triple gate 3-3 and the 4th triple gate
The low level gating signal of 3-4, now the physical layer transceiver end of half-duplex signal acquisition module 1 by the 3rd triple gate 3-3 and
4th triple gate 3-4 sends data to physical layer receiving terminal 2-1.
Claims (2)
1. full duplex and half-duplex converter, including half-duplex signal acquisition module (1), it is characterised in that：It also includes complete double
Work data processing module (2) and triple gate integrated circuit (3), the full-duplex data processing module (2) receive including physical layer
End (2-1), physical layer transmitting terminal (2-2) and fpga chip (2-3)；
Described half-duplex signal acquisition module (1) is using the realization of RS485 chips, described physical layer receiving terminal (2-1) and thing
Reason layer transmitting terminal (2-2) is realized using 422 serial port drive modules；
The 422R+ ports and 422R- ports of physical layer receiving terminal (2-1) connect the data letter of triple gate integrated circuit (3) respectively
Number output+port and data-signal output-port, the 422T+ ports and 422T- ports of physical layer transmitting terminal (2-2) connect respectively
Command signal input+the port and command signal input-port of triple gate integrated circuit (3) are connect, triple gate integrated circuit (3)
I/O+ ports and I/O- ports connect the 485+ ports and 485- ports of half-duplex signal acquisition module (1) respectively；
The triple gate of fpga chip (2-3) enables the enable signal input part of signal output part connection triple gate integrated circuit (3)；
Described triple gate integrated circuit (3) includes the first triple gate (3-1), the second triple gate (3-2), the 3rd triple gate (3-
3), the 4th triple gate (3-4) and not gate (3-5)；
The enable of the input, the enable signal end of the first triple gate (3-1) and the second triple gate (3-2) of the not gate (3-5)
Signal end links together, and used as the enable signal input part of triple gate integrated circuit (3), the output end of not gate (3-5) is simultaneously
Connect the enable signal end of the 3rd triple gate (3-3) and the enable signal end of the 4th triple gate (3-4)；
The 422T+ ports of input connection physical layer transmitting terminal (2-2) of the first triple gate (3-1), the second triple gate (3-2)
The 422T- ports of input connection physical layer transmitting terminal (2-2), the input connection physical layer of the 3rd triple gate (3-3) is received
Hold the 422R+ ports of (2-1), the 422R- ports of input connection physical layer receiving terminal (2-1) of the 4th triple gate (3-4)；
The output end of the first triple gate (3-1) is connected half-duplex signal collection mould simultaneously with the output end of the 3rd triple gate (3-3)
The 485+ ports of block (1), the output end of the second triple gate (3-2) is connected half pair simultaneously with the output end of the 4th triple gate (3-4)
The 485- ports of work signal acquisition module (1)；
Be integrated together for four triple gates by above-mentioned triple gate integrated circuit (3), and fpga chip (2-3) is enabled by triple gate to be believed
The low level gating signal that number output end sends to triple gate integrated circuit (3), the signal is by turning into the 3rd after not gate (3-5)
The high level cut-off signals of triple gate (3-3) and the 4th triple gate (3-4), now physical layer transmitting terminal (2-2) is by the one or three
State door (3-1) and the second triple gate (3-2) send instruction to the physical layer transceiver end of half-duplex signal acquisition module (1)；Instruction
After being sent, fpga chip (2-3) sends high level cut-off signals to triple gate integrated circuit (3), and the signal is the one or three
State door (3-1) and the second triple gate (3-2) high level cut-off signals, but the signal is by after not gate (3-5), as the 3rd tri-state
Door (3-3) and the 4th triple gate (3-4) low level gating signal, now half-duplex signal acquisition module (1) physical layer receipts
Originator sends data by the 3rd triple gate (3-3) and the 4th triple gate (3-4) to physical layer receiving terminal (2-1)；
The fpga chip (2-3) is embedded in data reception module (2-3-1), the dual port RAM module (2-3- of software realization
2), calculation process module (2-3-3) and instruction sending module (2-3-4)；
Described data reception module (2-3-1) is included with lower unit：
Low level gating signal transmitting element：For sending low level gating signal to triple gate integrated circuit (3), and in the list
Log-on data reads instruction sending unit after first end of run；
High level cut-off signals transmitting element：For sending high level cut-off signals to triple gate integrated circuit (3), and in the list
Log-on data receives enabler flags transmitting element after first end of run；
Data receipt unit：It is for receiving the data that physical layer receiving terminal (2-1) is sent and same after the unit end of run
When log-on data memory cell and instruction send enabler flags transmitting element；
Data storage cell：Data is activation to dual port RAM module (2-3-2) for physical layer receiving terminal (2-1) to be sent is entered
Row storage, and the log-on data processing unit after the unit end of run；
Instruction sends enabler flags transmitting element：Enabler flags are sent for sending instruction to instruction sending module (2-3-4), and
Enabled instruction sends enabler flags judging unit after the unit end of run；
Described dual port RAM module (2-3-2) is used to be stored the data that data reception module (2-3-1) is sent；
Described instruction sending module (2-3-4) is included with lower unit：
Data read command transmitting element：For sending data read command to physical layer transmitting terminal (2-2), and in unit fortune
Row opens high level cut-off signals transmitting element after terminating；
Data receiver enabler flags transmitting element：For sending data receiver enabler flags to data reception module (2-3-1), and
The log-on data receiving unit after the unit end of run；
Instruction sends enabler flags judging unit：For judging whether that receiving instruction sends enabler flags, and it is in judged result
Start low level gating signal transmitting element when being, full duplex is terminated when judged result is no and is changed with half-duplex；
Described calculation process module (2-3-3) is included with lower unit：
Data processing unit：For calling the data in dual port RAM module (2-3-2), the data are processed, and in the list
Log-on data computing judging unit after first end of run；
Data operation judging unit：For judging whether data operation finishes, and judged result for be when terminate full duplex with
Half-duplex is changed, and when judged result is no, enabled instruction sends mark judging unit.
2. full duplex and half-duplex conversion method, the method are realized based on following conversion equipments：The conversion equipment includes half
Duplex signaling acquisition module (1), full-duplex data processing module (2) and triple gate integrated circuit (3), at the full-duplex data
Reason module (2) includes physical layer receiving terminal (2-1), physical layer transmitting terminal (2-2) and fpga chip (2-3)；
Described half-duplex signal acquisition module (1) is using the realization of RS485 chips, described physical layer receiving terminal (2-1) and thing
Reason layer transmitting terminal (2-2) is realized using 422 serial port drive modules；
The 422R+ ports and 422R- ports of physical layer receiving terminal (2-1) connect the data letter of triple gate integrated circuit (3) respectively
Number output+port and data-signal output-port, the 422T+ ports and 422T- ports of physical layer transmitting terminal (2-2) connect respectively
Command signal input+the port and command signal input-port of triple gate integrated circuit (3) are connect, triple gate integrated circuit (3)
I/O+ ports and I/O- ports connect the 485+ ports and 485- ports of half-duplex signal acquisition module (1) respectively；
The triple gate of fpga chip (2-3) enables the enable signal input part of signal output part connection triple gate integrated circuit (3)；
Described triple gate integrated circuit (3) includes the first triple gate (3-1), the second triple gate (3-2), the 3rd triple gate (3-
3), the 4th triple gate (3-4) and not gate (3-5)；
The enable of the input, the enable signal end of the first triple gate (3-1) and the second triple gate (3-2) of the not gate (3-5)
Signal end links together, and used as the enable signal input part of triple gate integrated circuit (3), the output end of not gate (3-5) is simultaneously
Connect the enable signal end of the 3rd triple gate (3-3) and the enable signal end of the 4th triple gate (3-4)；
The 422T+ ports of input connection physical layer transmitting terminal (2-2) of the first triple gate (3-1), the second triple gate (3-2)
The 422T- ports of input connection physical layer transmitting terminal (2-2), the input connection physical layer of the 3rd triple gate (3-3) is received
Hold the 422R+ ports of (2-1), the 422R- ports of input connection physical layer receiving terminal (2-1) of the 4th triple gate (3-4)；
The output end of the first triple gate (3-1) is connected half-duplex signal collection mould simultaneously with the output end of the 3rd triple gate (3-3)
The 485+ ports of block (1), the output end of the second triple gate (3-2) is connected half pair simultaneously with the output end of the 4th triple gate (3-4)
The 485- ports of work signal acquisition module (1)；
Be integrated together for four triple gates by above-mentioned triple gate integrated circuit (3), and fpga chip (2-3) is enabled by triple gate to be believed
The low level gating signal that number output end sends to triple gate integrated circuit (3), the signal is by turning into the 3rd after not gate (3-5)
The high level cut-off signals of triple gate (3-3) and the 4th triple gate (3-4), now physical layer transmitting terminal (2-2) is by the one or three
State door (3-1) and the second triple gate (3-2) send instruction to the physical layer transceiver end of half-duplex signal acquisition module (1)；Instruction
After being sent, fpga chip (2-3) sends high level cut-off signals to triple gate integrated circuit (3), and the signal is the one or three
State door (3-1) and the second triple gate (3-2) high level cut-off signals, but the signal is by after not gate (3-5), as the 3rd tri-state
Door (3-3) and the 4th triple gate (3-4) low level gating signal, now half-duplex signal acquisition module (1) physical layer receipts
Originator sends data by the 3rd triple gate (3-3) and the 4th triple gate (3-4) to physical layer receiving terminal (2-1)；
The fpga chip (2-3) includes data reception module (2-3-1), dual port RAM module (2-3-2), calculation process module
(2-3-3) and instruction sending module (2-3-4)；
It is characterized in that：The full duplex is comprised the following steps with half-duplex conversion method：
Low level gating signal forwarding step：Data reception module (2-3-1) sends low level and selects to triple gate integrated circuit (3)
Messenger, and data read command forwarding step is performed after the step terminates；
Data read command forwarding step：Instruction sending module (2-3-4) sends digital independent and refers to physical layer transmitting terminal (2-2)
Order, and high level cut-off signals forwarding step is performed after the step terminates；
High level cut-off signals forwarding step：Data reception module (2-3-1) sends high level and closes to triple gate integrated circuit (3)
Break signal, and data receiver enabler flags forwarding step is performed after the step terminates；
Data receiver enabler flags forwarding step：Instruction sending module (2-3-4) sends data to data reception module (2-3-1)
Enabler flags are received, and data reception step is performed after the step terminates；
Data reception step：Data reception module (2-3-1) receives the data that physical layer receiving terminal (2-1) is sent, and in the step
It is rapid to terminate to perform data storing steps and instruction transmission enabler flags forwarding step simultaneously afterwards；
Data storing steps：The data is activation that data reception module (2-3-1) sends physical layer receiving terminal (2-1) is to twoport
RAM module (2-3-2) is stored, and data processing step is performed after the step terminates；
Data processing step：Calculation process module (2-3-3) calls the data in dual port RAM module (2-3-2), and the data are entered
Row treatment, and execution data operation judges step after the step terminates；
Data operation judges step：Calculation process module (2-3-3) judges whether data operation finishes, and is yes in judged result
When terminate full duplex and half-duplex conversion method, judged result for it is no when execute instruction send mark and judge step；
Instruction sends enabler flags forwarding step：Data reception module (2-3-1) sends to instruction sending module (2-3-4) and instructs
Enabler flags are sent, and execute instruction transmission enabler flags judge step after the step terminates；
Instruction sends enabler flags and judges step：Instruction sending module (2-3-4) judges whether that receiving instruction sends enabler flags,
And low level gating signal forwarding step is performed when judged result is to be, full duplex is terminated when judged result is no with half pair
Work conversion method.
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| WO2018102981A1 (en) * | 2016-12-06 | 2018-06-14 | 吉蒂机器人私人有限公司 | Full-duplex and half-duplex serial port signal conversion circuit, and robot |
| CN107947911B (en) * | 2017-12-29 | 2023-12-01 | 数源科技股份有限公司 | Communication device and communication method for realizing half-duplex analog full duplex based on upper computer RS485 communication |
| CN110457244B (en) * | 2018-05-08 | 2021-09-17 | 深圳市优必选科技有限公司 | Serial port communication mode conversion method, system and processor |
| CN108989708B (en) * | 2018-07-25 | 2021-01-08 | 长芯盛（武汉）科技有限公司 | Low-speed control signal photoelectric conversion module of universal multimedia interface |
| CN111245583B (en) * | 2018-11-29 | 2022-04-19 | 瑞昱半导体股份有限公司 | Network communication device and method |
| CN117336380B (en) * | 2023-12-01 | 2024-03-05 | 浙江国利信安科技有限公司 | Network communication system, method, apparatus and medium for communication |
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