CN206134145U - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN206134145U CN206134145U CN201621155519.8U CN201621155519U CN206134145U CN 206134145 U CN206134145 U CN 206134145U CN 201621155519 U CN201621155519 U CN 201621155519U CN 206134145 U CN206134145 U CN 206134145U
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- 239000002184 metal Substances 0.000 claims abstract description 355
- 229910052751 metal Inorganic materials 0.000 claims abstract description 355
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000009413 insulation Methods 0.000 claims description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 208000034699 Vitreous floaters Diseases 0.000 claims 22
- 239000000463 material Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000012447 hatching Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The utility model discloses a display panel and display device. The display panel comprises a substrate, wherein a chip alignment mark, a plurality of first metal wires, a plurality of second metal wires and a plurality of connecting parts are arranged on the substrate; each connecting part is respectively connected with a first metal wire and a second metal wire, the first metal wire is used for connecting the first end of the connecting part and the metal wiring in the display area, and the second metal wire is used for connecting the second end of the connecting part and an external circuit; the plurality of connecting parts are arranged in at least two rows and are arranged along the direction vertical to the row direction of the connecting parts, and the plurality of first metal wires and the plurality of second metal wires are respectively arranged at two opposite sides of the plurality of connecting parts; the chip alignment mark, and the first metal wire and the second metal wire which are arranged adjacent to the connecting parts in the row direction are positioned on the same metal layer. The embodiment of the utility model provides a technical scheme has avoided the line ball phenomenon that a plurality of connecting portions and first metal wire or second metal wire take place, has improved display panel's yield.
Description
Technical field
The utility model is related to display technology field, more particularly to a kind of display floater and display device.
Background technology
With the continuous development of Display Technique, display floater is gradually applied in each electronic product.
The non-display area of display floater is provided with binding region in prior art, for the control core that display floater provides signal
Piece is bundled in the region.In order to improve the accuracy of control chip binding, chip alignment mark is provided with binding region,
For coordinating the positioning for completing chip with the alignment mark that is correspondingly arranged on control chip.Except chip alignment mark, area is bound
Also include multiple connecting portions that correspondence control chip pin is arranged in domain, and for realizing in multiple connecting portions and display floater
Portion's cabling or external circuit connection a plurality of connecting line, wherein alignment mark, multiple connecting portions and for realize connecting portion with
The connecting line of display floater inside cabling connection is located at same metal level, for realizing the connection that connecting portion is connected with external circuit
Line is located at another metal level.
During alignment mark, multiple connecting portions and a plurality of connecting line is formed, due to film layer contraposition deviation and
Practical structures size and the presence of preset structure dimensional discrepancy, for the less connecting portion of spacing and connecting line, often can press
Line phenomenon, the yield for causing display floater declines.
Utility model content
The utility model embodiment provides a kind of display floater and display device, to avoid the generation of line ball phenomenon, improves
The yield of display floater.
In a first aspect, the utility model embodiment provides a kind of display floater, the display floater includes：
Viewing area and the non-display area around the viewing area；
The non-display area includes binding region, and the binding region includes substrate, on the substrate chip pair is provided with
Position mark, a plurality of first metal wire, a plurality of second metal wire and multiple connecting portions；
Wherein, the plurality of connecting portion is used to bind control chip；
Each described connecting portion connects respectively first metal wire and second metal wire, and described first
Metal wire is used to connect the first end of the connecting portion and the metal routing in the viewing area, and second metal wire is used for
Connect the second end and the external circuit of the connecting portion；
The plurality of connecting portion is arranged at least two rows, and along the vertical direction of the connecting portion line direction, it is described a plurality of
First metal wire and a plurality of second metal wire are respectively arranged at the relative both sides of the plurality of connecting portion；
The chip alignment mark, and the first metal being disposed adjacent with the plurality of connecting portion on the line direction
Line and the second metal wire are located at same metal level.
Alternatively, a plurality of first metal wire, a plurality of second metal wire, the plurality of connecting portion and the core
Piece alignment mark is located at the first metal layer.
Alternatively, the viewing area includes insulation multi-strip scanning line arranged in a crossed manner and a plurality of data lines, described a plurality of to sweep
Retouch line or a plurality of data lines is located at the first metal layer.
Alternatively, a plurality of first metal wire, a plurality of second metal wire and the chip alignment mark are located at
Second metal layer, the plurality of connecting portion is in the 3rd metal level.
Alternatively, the viewing area includes insulation multi-strip scanning line arranged in a crossed manner and a plurality of data lines, described a plurality of to sweep
Line is retouched positioned at the second metal layer, a plurality of data lines is located at the 3rd metal level.
Alternatively, the viewing area includes insulation multi-strip scanning line arranged in a crossed manner and a plurality of data lines, a plurality of number
The second metal layer is located at according to line, the multi-strip scanning line is located at the 3rd metal level.
Alternatively, the plurality of connecting portion, a plurality of second metal wire and the chip alignment mark are located at the 4th
Metal level, in a plurality of first metal wire Part I be located at fifth metal layer, in addition to the Part I other first
Metal wire is located at the 4th metal level.
Alternatively, the plurality of connecting portion is arranged in two rows, and the first metal wire of connecting portion connection is located at described in different rows
Different metal layer.
Alternatively, the first metal wire positioned at the fifth metal layer connects with a line connecting portion away from the external circuit
Connect.
Alternatively, positioned at first metal wire and the first metal wire positioned at the fifth metal layer of the 4th metal level
It is crisscross arranged successively.
Alternatively, the viewing area includes insulation multi-strip scanning line arranged in a crossed manner and a plurality of data lines, described a plurality of to sweep
Line is retouched positioned at the 4th metal level, a plurality of data lines is located at fifth metal layer.
Alternatively, the first metal wire positioned at the 4th metal level is electrically connected respectively with corresponding scan line, positioned at institute
The first metal wire for stating fifth metal layer is electrically connected respectively with corresponding data wire.
Alternatively, the viewing area includes insulation multi-strip scanning line arranged in a crossed manner and a plurality of data lines, a plurality of number
The 4th metal level is located at according to line, the multi-strip scanning line is located at the fifth metal layer.
Alternatively, the first metal wire positioned at the 4th metal level is electrically connected respectively with corresponding data wire, positioned at institute
The first metal wire for stating fifth metal layer is electrically connected respectively with corresponding scan line.
Alternatively, positioned at first metal wire and the first metal positioned at the fifth metal layer of the 4th metal level
Line is electrically connected with the scan line, or is electrically connected with the data wire.
Alternatively, the plurality of connecting portion, a plurality of first metal wire and the chip alignment mark are located at the 6th
Metal level, in a plurality of second metal wire Part I be located at the 7th metal level, in addition to the Part I other second
Metal wire is located at the 6th metal level.
Alternatively, the plurality of connecting portion is arranged in two rows, and the second metal wire of connecting portion connection is located at described in different rows
Different metal layer.
Alternatively, the second metal wire positioned at the 7th metal level connects with a line connecting portion near the external circuit
Connect.
Alternatively, positioned at second metal wire and the second metal wire positioned at the 7th metal level of the 6th metal level
It is crisscross arranged successively.
Alternatively, the viewing area includes insulation multi-strip scanning line arranged in a crossed manner and a plurality of data lines, described a plurality of to sweep
Line is retouched positioned at the 6th metal level, a plurality of data lines is located at the 7th metal level.
Alternatively, the viewing area includes insulation multi-strip scanning line arranged in a crossed manner and a plurality of data lines, a plurality of number
The 6th metal level is located at according to line, the multi-strip scanning line is located at the 7th metal level.
Second aspect, the utility model embodiment additionally provides a kind of display device, and the display device includes first party
Display floater described in face.
The technical scheme that the utility model embodiment is provided, by the binding region of display floater non-display area, inciting somebody to action
Chip alignment mark and the first metal wire being disposed adjacent with multiple connecting portions on the line direction of connecting portion and the second metal
Line is arranged at same metal level, it is to avoid the line ball that multiple connecting portions occur with adjacent first metal wire or the second metal wire shows
As improve the yield of display floater.
Description of the drawings
It is of the present utility model by reading the detailed description made to non-limiting example made with reference to the following drawings
Other features, objects and advantages will become more apparent upon：
Fig. 1 is the structural representation of the display floater that the utility model embodiment is provided；
Fig. 2 is the structural representation of another display floater that the utility model embodiment is provided；
Fig. 3 is the structural representation of another display floater that the utility model embodiment is provided；
Fig. 4 is the structural representation of another display floater that the utility model embodiment is provided；
Fig. 5 is the structural representation of another display floater that the utility model embodiment is provided；
Fig. 6 is the structural representation of another display floater that the utility model embodiment is provided；
Fig. 7 is the structural representation of another display floater that the utility model embodiment is provided；
Fig. 8 is the structural representation of another display floater that the utility model embodiment is provided；
Fig. 9 is the structural representation of the display device that the utility model embodiment is provided.
Specific embodiment
With reference to the accompanying drawings and examples the utility model is described in further detail.It is understood that herein
Described specific embodiment is used only for explanation the utility model, rather than to restriction of the present utility model.Further need exist for
It is bright, for the ease of description, the part related to the utility model rather than full content are illustrate only in accompanying drawing.
Fig. 1 is the structural representation of the display floater that the utility model embodiment is provided.As shown in figure 1, display floater 10
Including viewing area 100 and the non-display area 200 around viewing area 100, non-display area 200 includes binding region 210.Binding region
210 include substrate (not shown), and chip alignment mark 214, a plurality of first metal wire 211, many is provided with substrate (not shown)
The second metal wire of bar 212 and multiple connecting portions 213.Wherein, multiple connecting portions 213 are used to bind control chip, each connection
Portion 213 connects respectively first metal wire 211 and second metal wire 212.First metal wire 211 is used to connect connecting portion
Metal routing in 213 first end and viewing area 100, specifically, the metal routing in viewing area 100 includes multi-strip scanning
Line 110, a plurality of data lines 120 and a plurality of other metal routing (not shown), the second metal wire 212 is used to connect connecting portion
213 the second end and external circuit (not shown).Multiple connecting portions 213 are arranged at least two rows, and along the row side of connecting portion 213
To vertical direction Y of X, a plurality of first metal wire 211 and a plurality of second metal wire 212 are respectively arranged at the phase of multiple connecting portions 213
To both sides.Chip alignment mark 214, and the first metal wire being disposed adjacent with multiple connecting portions 213 on line direction X
211 and second metal wire 212 be located at same metal level.
It should be noted that in FIG, chip alignment mark 214 is shaped as four discrete squares, now, control
The alignment mark being correspondingly arranged on chip is cross, with four discrete foursquare seam shapes in chip alignment mark 214
It is identical.During the actual laminating of control chip, operator can observe chip alignment mark 214 with control by transparent substrate
Mosaic status between the alignment mark being correspondingly arranged on coremaking piece, by the position and angle that adjust control chip control is capable of achieving
Coremaking piece is accurately positioned.Can realize it is chimeric with the alignment mark on control chip in the case of, chip alignment mark 214
Can also be other shapes.
Also, it should be noted that Fig. 1 only includes five companies of two row connecting portions 213 and often row setting so that binding region 210 is interior
Illustrate as a example by socket part 213 and non-limiting, line number, connecting portion 213 quantity that often row arranged of the present embodiment to connecting portion 213
And the arrangement mode of connecting portion 213 is not specifically limited in each row.Additionally, adjacent with multiple connecting portions 213 on line direction X
The first metal wire 211 and the second metal wire 212 for arranging refers to first arranged close to each connecting portion 213 on line direction X
The metal wire 212 of metal wire 211 and second.It should be noted that according to the difference of the arrangement mode of multiple connecting portions 213, with each company
What socket part 213 was disposed adjacent is probably two the first metal wires 211, it may be possible to two the second metal wires 212, it is also possible to
First metal wire 211 and second metal wire 212.
The technical scheme that the present embodiment is provided, by the binding region 210 of the non-display area 200 of display floater 10, inciting somebody to action
Chip alignment mark 214 and the first metal wire 211 being disposed adjacent with multiple connecting portions 213 on the line direction X of connecting portion
Same metal level is arranged at the second metal wire 212, it is to avoid film layer contraposition deviation and practical structures size and preset structure
The line ball phenomenon that multiple connecting portions 213 occur with adjacent first metal wire, 211 or second metal wire 212 caused by dimensional discrepancy,
Improve the yield of display floater 10.
It should be noted that the structure with identical hatching pattern is arranged with layer in Fig. 1, the knot with different hatching patterns
The different layer of structure is arranged.Additionally, for it is clearer explanation binding region 210 in each structure facilities, Fig. 1 is to binding region 210
It is amplified, therefore, the proportionate relationship in display floater 10 shown in Fig. 1 between each structure is different from actual ratio relation.This reality
It is identical with Fig. 1 with new other accompanying drawings situation, subsequently repeat no more.
Exemplary, as shown in figure 1, a plurality of first metal wire 211, a plurality of second metal wire 212, multiple connecting portions 213
And chip alignment mark 214 may be located at the first metal layer.I.e. a plurality of first metal wire 211, a plurality of second metal wire 212,
Multiple connecting portions 213 and chip alignment mark 214 are arranged with layer.
Referring to Fig. 1, viewing area 100 includes insulation multi-strip scanning line 110 arranged in a crossed manner and a plurality of data lines 120, a plurality of
Scan line 110 may be located at the first metal layer, and a plurality of data lines 120 may be located at other metal levels outside the first metal layer.
I.e. a plurality of first metal wire 211, a plurality of second metal wire 212, multiple connecting portions 213, chip alignment mark 214 and multi-strip scanning
Line 110 is arranged with layer, and is arranged with the different layer of a plurality of data lines 120.
Optional, or a plurality of data lines 120 is located at the first metal layer, and multi-strip scanning line 110 is located at the first metal
Other metal levels outside layer, as shown in Figure 2.I.e. a plurality of first metal wire 211, a plurality of second metal wire 212, multiple connecting portions
213rd, chip alignment mark 214 is arranged with a plurality of data lines 120 with layer, and same material shape can be adopted in same processing step
Into.
It should be noted that by a plurality of first metal wire 211, a plurality of second metal wire 212, multiple connecting portions 213 and
Chip alignment mark 214 is arranged with multi-strip scanning line 110 or a plurality of data lines 120 with layer so that a plurality of first metal wire 211,
A plurality of second metal wire 212, multiple connecting portions 213, chip alignment mark 214 and multi-strip scanning line 110 or a plurality of data lines
120 can be formed in same processing step using same material, reduce one-time process step, advantageously reduce technique difficult
Degree.
Fig. 3 is the structural representation of another display floater that the utility model embodiment is provided.As shown in figure 3, showing
Panel 30 includes viewing area 100 and the non-display area 200 around viewing area 100, and non-display area 200 includes binding region 210.Tie up
Region 210 is determined including substrate (not shown), chip alignment mark 214, a plurality of first metal wire are provided with substrate (not shown)
211st, a plurality of second metal wire 212 and multiple connecting portions 213.Wherein, multiple connecting portions 213 are used to bind control chip, often
Individual connecting portion 213 connects respectively first metal wire 211 and second metal wire 212.First metal wire 211 is used to connect
Metal routing in the first end of connecting portion 213 and viewing area 100, specifically, the metal routing in viewing area 100 includes many
Bar scan line 110, a plurality of data lines 120 and a plurality of other metal routing (not shown), the second metal wire 212 is used to connect company
Second end of socket part 213 and external circuit (not shown).Multiple connecting portions 213 are arranged at least two rows, and along connecting portion 213
Vertical direction Y of line direction X, a plurality of first metal wire 211 and a plurality of second metal wire 212 are respectively arranged at multiple connecting portions
213 relative both sides.A plurality of first metal wire 211, a plurality of second metal wire 212 and chip alignment mark 214 are located at second
Metal level, multiple connecting portions 213 are located at the 3rd metal level.I.e. a plurality of first metal wire 211, a plurality of second metal wire 212 and
Chip alignment mark 214 is arranged with layer, and multiple connecting portions 213 are arranged with layer and arranged with the different layer of said structure.
Referring to Fig. 3, viewing area 100 includes insulation multi-strip scanning line 110 arranged in a crossed manner and a plurality of data lines 120, a plurality of
Scan line 110 may be located at second metal layer, and a plurality of data lines 120 may be located at the 3rd metal level.I.e. a plurality of first metal wire
211st, a plurality of second metal wire 212, chip alignment mark 214 and multi-strip scanning line 110 are arranged with layer, multiple connecting portions 213 with
A plurality of data lines 120 is arranged with layer and arranged with the different layer of said structure.The each structure arranged with layer can be in same processing step
Middle employing same material is formed, to reduce the beneficial effect of technology difficulty.
Optional, or a plurality of data lines 120 is located at second metal layer, and multi-strip scanning line 110 is located at the 3rd metal
Layer, as shown in Figure 4.I.e. a plurality of first metal wire 211, a plurality of second metal wire 212, chip alignment mark 214 and many datas
Line 120 is arranged with layer, and multiple connecting portions 213 are arranged with layer with multi-strip scanning line 110 and arranged with the different layer of said structure.
Fig. 5 is the structural representation of another display floater that the utility model embodiment is provided.As shown in figure 5, showing
Panel 50 includes viewing area 100 and the non-display area 200 around viewing area 100, and non-display area 200 includes binding region 210.Tie up
Region 210 is determined including substrate (not shown), chip alignment mark 214, a plurality of first metal wire are provided with substrate (not shown)
211st, a plurality of second metal wire 212 and multiple connecting portions 213.Wherein, multiple connecting portions 213 are used to bind control chip, often
Individual connecting portion 213 connects respectively first metal wire 211 and second metal wire 212.First metal wire 211 is used to connect
Metal routing in the first end of connecting portion 213 and viewing area 100, specifically, the metal routing in viewing area 100 includes many
Bar scan line 110, a plurality of data lines 120 and a plurality of other metal routing (not shown), the second metal wire 212 is used to connect company
Second end of socket part 213 and external circuit (not shown).Multiple connecting portions 213 are arranged at least two rows, and along connecting portion 213
Vertical direction Y of line direction X, a plurality of first metal wire 211 and a plurality of second metal wire 212 are respectively arranged at multiple connecting portions
213 relative both sides.Multiple connecting portions 213, a plurality of second metal wire 212 and chip alignment mark 214 are located at the 4th metal
Layer, the first metal wire of Part I 211/1 is located at fifth metal layer in a plurality of first metal wire 211, except the gold medal of Part I first
Other first metal wires (metal wire of Part II first) 211/2 outside category line 211/1 are located at the 4th metal level.I.e. multiple connections
Portion 213, a plurality of second metal wire 212, chip alignment mark 214 and the first metal wire of a plurality of Part II 211/2 set with layer
Put, the first metal wire of a plurality of Part I 211/1 is arranged with layer and arranged with the different layer of said structure.The each structure arranged with layer can
To be formed using same material in same processing step, to reduce technology difficulty.
Exemplary, as shown in figure 5, multiple connecting portions 213 can be arranged in two rows, the connecting portion 213 of different rows connects
The first metal wire 211 be located at different metal layer.It should be noted that the line direction X of connecting portion 213 can be with multi-strip scanning line
110 bearing of trend is identical, also can there is an angle with the bearing of trend of multi-strip scanning line 110, and the present embodiment does not do to this to be had
Body is limited.
Optionally, the first metal wire 211 positioned at fifth metal layer can be with a line connecting portion 213 away from external circuit
Connection.I.e. as shown in figure 5, the first metal wire of a plurality of Part I 211/1 can be with a line connecting portion 213 away from external circuit
Connection.It should be noted that external circuit is arranged at the outside of display floater 50, typically external test circuitry, for
Functional test is carried out to display floater 50 before unbound control chip.The first metal wire of a plurality of Part I 211/1 and multiple companies
Socket part 213, a plurality of second metal wire 212, chip alignment mark 214 and the different layer of the first metal wire of a plurality of Part II 211/2
Arrange, although under the influence of film layer contraposition deviation and practical structures size and preset structure dimensional discrepancy, a plurality of first
Dividing the forming position of the first metal wire 211/1 can have deviation with former design attitude, but due on the line direction X of connecting portion 213
Be disposed adjacent with the first metal wire of each Part I 211/1 for the first metal wire 211 rather than connecting portion 213 so that will not go out
Now with the line ball problem of connecting portion 213.
Referring to Fig. 5, the first metal wire 211 positioned at the 4th metal level and the first metal wire 211 positioned at fifth metal layer
Can be crisscross arranged successively.I.e. as shown in figure 5, the first metal wire of a plurality of Part II 211/2 and the gold medal of a plurality of Part I first
Category line 211/1 can be crisscross arranged successively.It is such to be provided with beneficial to the overall occupancy for reducing multiple connecting portions 213 on substrate
Area, can reach the beneficial effect for reducing the area of display floater 50.
Further, viewing area 100 includes insulation multi-strip scanning line 110 arranged in a crossed manner and a plurality of data lines 120, a plurality of
Scan line 110 may be located at the 4th metal level, and a plurality of data lines 120 may be located at fifth metal layer.I.e. multiple connecting portions 213,
A plurality of second metal wire 212, chip alignment mark 214 and the first metal wire of a plurality of Part II 211/2 and multi-strip scanning line
110 are arranged with layer, and the first metal wire of a plurality of Part I 211/1 is arranged and different with said structure with a plurality of data lines 120 with layer
Layer is arranged.Such setting advantageously reduces one-time process step, and then reduces technology difficulty.
Accordingly, for the scan line 110 and data wire 120 by control chip for viewing area 100 provides signal
Situation, the first metal wire 211 positioned at the 4th metal level can be electrically connected respectively with corresponding scan line 110, positioned at five metals
First metal wire 211 of category layer can be electrically connected respectively with corresponding data wire 120.The i.e. a plurality of metal wire of Part II first
211/2 can electrically connect respectively with corresponding scan line 110, the first metal wire of a plurality of Part I 211/1 can respectively with it is right
The data wire 120 answered is electrically connected.In this case, the multiple connecting portions being connected with the first metal wire of a plurality of Part II 211/2
213 and control chip each scanning signal transmission pin connection, it is multiple with what the first metal wire of a plurality of Part I 211/1 was connected
Each data signal transmission pin connection of connecting portion 213 and control chip.
Optional, or a plurality of data lines 120 is located at the 4th metal level, and multi-strip scanning line 110 is located at fifth metal
Layer, as shown in Figure 6.Accordingly, the first metal wire 211 positioned at the 4th metal level can be electric with corresponding data wire 120 respectively
Connection, the first metal wire 211 positioned at fifth metal layer can be electrically connected respectively with corresponding scan line 110.I.e. a plurality of second
The first metal wire of part 211/2 can be electrically connected respectively with corresponding data wire 120, the first metal wire of a plurality of Part I 211/
1 can electrically connect respectively with corresponding scan line 110.In this case, it is connected with the first metal wire of a plurality of Part II 211/2
Multiple connecting portions 213 and control chip each data signal transmission pin connection, with the metal wire of a plurality of Part I first
Multiple connecting portions 213 of 211/1 connection and each scanning signal transmission pin connection of control chip.
Optionally, for the display panel structure shown in Fig. 5 and Fig. 6, positioned at the 4th metal level the first metal wire 211 with
And can also electrically connect with scan line 110 positioned at the first metal wire 211 of fifth metal layer, or it is electric with data wire 120
Connection.I.e. a plurality of the first metal wire of Part II 211/2 and the first metal wire of a plurality of Part I 211/1 can with scanning
Line 110 is electrically connected, or is electrically connected with data wire 120.Now, it is connected with the first metal wire of a plurality of Part II 211/2
Multiple connecting portions 213 and multiple connecting portions 213 for being connected with the first metal wire of a plurality of Part I 211/1 are and control chip
The transmission pin connection of each scanning signal, or connect with each data signal transmission pin of control chip.Exemplary, it is right
In the display floater 50 shown in Fig. 5, when the first metal wire of a plurality of Part II 211/2 and the metal wire of a plurality of Part I first
211/1 with scan line 110 when electrically connecting, due to multi-strip scanning line 110 and the same layer of the first metal wire of a plurality of Part II 211/2
Arrange, thus formed simultaneously in each structure in forming the 4th metal level the first metal wire of a plurality of Part II 211/2 with it is a plurality of
The connecting line of scan line 110.And a plurality of the first metal wire of Part I 211/1 is arranged with the different layer of multi-strip scanning line 110,
Realize that connection then needs to use overline structure.
Fig. 7 is the structural representation of another display floater that the utility model embodiment is provided.As shown in fig. 7, showing
Panel 70 includes viewing area 100 and the non-display area 200 around viewing area 100, and non-display area 200 includes binding region 210.Tie up
Region 210 is determined including substrate (not shown), chip alignment mark 214, a plurality of first metal wire are provided with substrate (not shown)
211st, a plurality of second metal wire 212 and multiple connecting portions 213.Wherein, multiple connecting portions 213 are used to bind control chip, often
Individual connecting portion 213 connects respectively first metal wire 211 and second metal wire 212.First metal wire 211 is used to connect
Metal routing in the first end of connecting portion 213 and viewing area 100, specifically, the metal routing in viewing area 100 includes many
Bar scan line 110, a plurality of data lines 120 and a plurality of other metal routing (not shown), the second metal wire 212 is used to connect company
Second end of socket part 213 and external circuit (not shown).Multiple connecting portions 213 are arranged at least two rows, and along connecting portion 213
Vertical direction Y of line direction X, a plurality of first metal wire 211 and a plurality of second metal wire 212 are respectively arranged at multiple connecting portions
213 relative both sides.Multiple connecting portions 213, a plurality of first metal wire 211 and chip alignment mark 214 are located at the 6th metal
Layer, the second metal wire of Part I 212/1 in a plurality of second metal wire 212 is located at the 7th metal level, except a plurality of Part I
Other second metal wires 212 (metal wire of Part II second) 212/2 outside second metal wire 212/1 are located at the 6th metal level.
I.e. multiple connecting portions 213, a plurality of first metal wire 211, chip alignment mark 214 and the metal wire of a plurality of Part II second
212/2 is arranged with layer, and the second metal wire of a plurality of Part I 212/1 is arranged with layer and arranged with the different layer of said structure.
As shown in fig. 7, multiple connecting portions 213 can be arranged in two rows, the second metal wire of the connection of different rows connecting portion 213
212 are located at different metal layer.Specifically, the second metal wire of a plurality of Part I 212/1 be located at the 7th metal level, a plurality of second
The second metal wire 212/2 is divided to be located at the 6th metal level.
Optionally, the second metal wire 212 positioned at the 7th metal level can be with a line connecting portion 213 near external circuit
Connection.I.e. as shown in fig. 7, the second metal wire of a plurality of Part I 212/1 can be with a line connecting portion 213 near external circuit
Connection.
Referring to Fig. 7, positioned at second metal wire 212 and the second metal wire 212 positioned at the 7th metal level of the 6th metal level
Can be crisscross arranged successively.I.e. a plurality of the second metal wire of Part II 212/2 and the second metal wire of a plurality of Part I 212/1 can
To be crisscross arranged successively.
Further, viewing area 100 includes insulation multi-strip scanning line 110 arranged in a crossed manner and a plurality of data lines 120, a plurality of
Scan line 110 may be located at the 6th metal level, and a plurality of data lines 120 may be located at the 7th metal level.I.e. multiple connecting portions 213,
A plurality of first metal wire 211, chip alignment mark 214 and the second metal wire of a plurality of Part II 212/2 and multi-strip scanning line
110 are arranged with layer, and the second metal wire of a plurality of Part I 212/1 is arranged with a plurality of data lines 120 with layer.With each knot that layer is arranged
Structure can be formed in same processing step using same material, to reduce technology difficulty.
Optional, or a plurality of data lines 120 is located at the 6th metal level, and multi-strip scanning line 110 is located at the 7th metal
Layer, as shown in Figure 8.Fig. 8 is the structural representation of another display floater that the utility model embodiment is provided, and shown in Fig. 7
The structure of display floater is compared, and difference is the layered relationship of viewing area data wire and scan line, and other something in common are not
Repeating.
Fig. 9 is the structural representation of the display device that the utility model embodiment is provided.As shown in figure 9, display device 90
Including the display floater 910 that this practical any embodiment is provided.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various bright
Aobvious change, readjust and substitute without departing from protection domain of the present utility model.Therefore, although by above example
The utility model is described in further detail, but the utility model is not limited only to above example, without departing from
In the case that the utility model is conceived, more other Equivalent embodiments can also be included, and scope of the present utility model is by appended
Right determine.
Claims (22)
1. a kind of display floater, it is characterised in that include：
Viewing area and the non-display area around the viewing area；
The non-display area includes binding region, and the binding region includes substrate, chip register guide is provided with the substrate
Note, a plurality of first metal wire, a plurality of second metal wire and multiple connecting portions；
Wherein, the plurality of connecting portion is used to bind control chip；
Each described connecting portion connects respectively first metal wire and second metal wire, first metal
Line is used to connect the first end of the connecting portion and the metal routing in the viewing area, and second metal wire is used to connect
Second end of the connecting portion and external circuit；
The plurality of connecting portion is arranged at least two rows, and along the vertical direction of the connecting portion line direction, described a plurality of first
Metal wire and a plurality of second metal wire are respectively arranged at the relative both sides of the plurality of connecting portion；
The chip alignment mark, and the first metal wire for being disposed adjacent with the plurality of connecting portion on the line direction and
Second metal wire is located at same metal level.
2. display floater according to claim 1, it is characterised in that a plurality of first metal wire, described a plurality of second
Metal wire, the plurality of connecting portion and the chip alignment mark are located at the first metal layer.
3. display floater according to claim 2, it is characterised in that the viewing area includes arranged in a crossed manner a plurality of of insulation
Scan line and a plurality of data lines, the multi-strip scanning line or a plurality of data lines are located at the first metal layer.
4. display floater according to claim 1, it is characterised in that a plurality of first metal wire, described a plurality of second
Metal wire and the chip alignment mark are located at second metal layer, and the plurality of connecting portion is in the 3rd metal level.
5. display floater according to claim 4, it is characterised in that the viewing area includes arranged in a crossed manner a plurality of of insulation
Scan line and a plurality of data lines, the multi-strip scanning line is located at the second metal layer, and a plurality of data lines is located at described the
Three metal levels.
6. display floater according to claim 4, it is characterised in that the viewing area includes arranged in a crossed manner a plurality of of insulation
Scan line and a plurality of data lines, a plurality of data lines is located at the second metal layer, and the multi-strip scanning line is located at described the
Three metal levels.
7. display floater according to claim 1, it is characterised in that the plurality of connecting portion, a plurality of second metal
Line and the chip alignment mark are located at the 4th metal level, and Part I is located at fifth metal in a plurality of first metal wire
Layer, other first metal wires in addition to the Part I are located at the 4th metal level.
8. display floater according to claim 7, it is characterised in that the plurality of connecting portion is arranged in two rows, different rows
First metal wire of the connecting portion connection is located at different metal layer.
9. display floater according to claim 8, it is characterised in that positioned at the fifth metal layer the first metal wire with
Connect away from a line connecting portion of the external circuit.
10. display floater according to claim 9, it is characterised in that positioned at the first metal wire of the 4th metal level
It is crisscross arranged successively with the first metal wire positioned at the fifth metal layer.
11. display floaters according to claim 7, it is characterised in that the viewing area includes that insulation is arranged in a crossed manner more
Bar scan line and a plurality of data lines, the multi-strip scanning line is located at the 4th metal level, and a plurality of data lines is located at the 5th
Metal level.
12. display floaters according to claim 11, it is characterised in that positioned at the first metal wire of the 4th metal level
Electrically connect with corresponding scan line respectively, the first metal wire positioned at the fifth metal layer is electrically connected respectively with corresponding data wire
Connect.
13. display floaters according to claim 7, it is characterised in that the viewing area includes that insulation is arranged in a crossed manner more
Bar scan line and a plurality of data lines, a plurality of data lines is located at the 4th metal level, and the multi-strip scanning line is located at described
Fifth metal layer.
14. display floaters according to claim 13, it is characterised in that positioned at the first metal wire of the 4th metal level
Electrically connect with corresponding data wire respectively, the first metal wire positioned at the fifth metal layer is electrically connected respectively with corresponding scan line
Connect.
15. display floaters according to claim 11 or 13, it is characterised in that positioned at the first gold medal of the 4th metal level
Category line and the first metal wire positioned at the fifth metal layer electrically connect with the scan line, or with the data wire
Electrical connection.
16. display floaters according to claim 1, it is characterised in that the plurality of connecting portion, a plurality of first metal
Line and the chip alignment mark are located at the 6th metal level, and Part I is located at the 7th metal in a plurality of second metal wire
Layer, other second metal wires in addition to the Part I are located at the 6th metal level.
17. display floaters according to claim 16, it is characterised in that the plurality of connecting portion is arranged in two rows, it is different
Second metal wire of the row connecting portion connection is located at different metal layer.
18. display floaters according to claim 17, it is characterised in that positioned at the second metal wire of the 7th metal level
It is connected with a line connecting portion near the external circuit.
19. display floaters according to claim 18, it is characterised in that positioned at the second metal wire of the 6th metal level
It is crisscross arranged successively with the second metal wire positioned at the 7th metal level.
20. display floaters according to claim 16, it is characterised in that the viewing area includes that insulation is arranged in a crossed manner more
Bar scan line and a plurality of data lines, the multi-strip scanning line is located at the 6th metal level, and a plurality of data lines is located at described
7th metal level.
21. display floaters according to claim 16, it is characterised in that the viewing area includes that insulation is arranged in a crossed manner more
Bar scan line and a plurality of data lines, a plurality of data lines is located at the 6th metal level, and the multi-strip scanning line is located at described
7th metal level.
22. a kind of display devices, it is characterised in that including the display floater described in any one of claim 1-21.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621155519.8U CN206134145U (en) | 2016-10-31 | 2016-10-31 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621155519.8U CN206134145U (en) | 2016-10-31 | 2016-10-31 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206134145U true CN206134145U (en) | 2017-04-26 |
Family
ID=58574903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621155519.8U Active CN206134145U (en) | 2016-10-31 | 2016-10-31 | Display panel and display device |
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| Country | Link |
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| CN (1) | CN206134145U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108375849A (en) * | 2018-04-27 | 2018-08-07 | 武汉华星光电技术有限公司 | Array substrate and chip bonding method |
| CN113516910A (en) * | 2020-04-09 | 2021-10-19 | 上海和辉光电有限公司 | Display panel and binding region planarization method thereof |
| CN113675221A (en) * | 2021-08-18 | 2021-11-19 | 惠科股份有限公司 | Display panel driving device, driving circuit and display device |
| CN114283706A (en) * | 2021-12-28 | 2022-04-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
-
2016
- 2016-10-31 CN CN201621155519.8U patent/CN206134145U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108375849A (en) * | 2018-04-27 | 2018-08-07 | 武汉华星光电技术有限公司 | Array substrate and chip bonding method |
| CN113516910A (en) * | 2020-04-09 | 2021-10-19 | 上海和辉光电有限公司 | Display panel and binding region planarization method thereof |
| CN113675221A (en) * | 2021-08-18 | 2021-11-19 | 惠科股份有限公司 | Display panel driving device, driving circuit and display device |
| CN114283706A (en) * | 2021-12-28 | 2022-04-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
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