CN206133249U - Coil control system a little based on DSP and FPGA - Google Patents

Abstract

The utility model discloses a coil control system a little based on DSP and FPGA, including DSP peripheral circuit and FPGA peripheral circuit, DSP peripheral circuit and the peripheral circuit connection of FPGA, the RST of the peripheral circuit power supply monitoring module of DSP and DSP chip is connected, and the manual reset is connected with the power monitoring module, and SDRAM, FLASH all are connected with the EMIF of DSP chip, RS422 receiver and full duplex RS422 transceiver all are connected with an optical coupling isolator among the FPGA peripheral circuit RS422 bus module, RS232 receiver and RS232 send the ware and all are connected with the 2nd optical coupling isolator among the RS232 bus module, CAN bus transceiver, the 3rd optical coupling isolator and CAN bus controller connect gradually among the CAN bus module, an optical coupling isolator, the 2nd optical coupling isolator and CAN bus controller all are connected with the FPGA chip, level matching module all is connected with the FPGA chip with the buffering chip in mileage and second pulse signal module. The utility model discloses combine FPGA and DSP to compromise speed and flexibility, improve data acquisition speed, precision and system stability.

Description

Micro- disk control system based on DSP and FPGA

Technical field

This utility model is related to a kind of control system, and in particular to the micro- disk control system based on DSP and FPGA.

Background technology

In the current of computer extensive application, data acquisition is one non-in computer digital animation and control field Often important aspect, it is that connection computer digit process is increasingly intended to digitized processing.Data acquisition technology is information One important branch of science, it is with sensor technology, signal detection and process, computer technology and electronics lamp subject Based on formed integrated application technology-oriented discipline.The collection of research information data, storage, process and control etc. radar, Communication, the underwater sound, remote sensing, geological prospecting, vibration engineering, Non-Destructive Testing, speech processes, intelligent instrument, industry automatic control and The numerous areas such as bioscience engineering have a wide range of applications.But there are problems that some could be improved in prior art, Such as sensor data acquisition speed is slower, and the data precision for being gathered is relatively low, and the system stability of whole data processing also has Wait to improve.

With the fast development of processor technology, the data collecting system with embedded computer system as core is being surveyed Dominant position is occupied in amount field, data collecting system be exactly by collection in worksite to data processed, transmitted, shown and stored Deng the equipment of operation.Generally, data collecting system is made up of three parts, and Part I is the pre- place to analogue signal Reason, is mainly filtered to signal and amplifies.Part II is analog/digital conversion, is to be easy to by analog-signal transitions Processed digital signal.Part III is process, storage and the display and output of result of digital signal.

Utility model content

Technical problem to be solved in the utility model is that acquisition speed is slow, precision is low, system stability is poor, purpose It is to provide based on micro- disk control system of DSP and FPGA, FPGA can solve the problem that the number of the Signal Pretreatment algorithm process of low layer According to big, processing speed is had high demands but the relatively simple problem of operating structure, DSP can solve the problem that the data of high-rise Processing Algorithm Amount lower level, algorithm is few, but the complicated problem of the control structure of algorithm, speed and motility are taken into account with reference to FPGA and DSP, together When meet the processing requirement of bottom layer signal and highest level signal.

This utility model is achieved through the following technical solutions：

Based on micro- disk control system of DSP and FPGA, including DSP peripheral circuits and FPGA peripheral circuit, the DSP is peripheral Circuit connects with FPGA peripheral circuit；The DSP peripheral circuits include dsp chip, Power Monitoring Unit, hand-reset, SDRAM and FLASH, the Power Monitoring Unit is connected with the RST of dsp chip, and the hand-reset is connected with Power Monitoring Unit, described SDRAM, FLASH are connected with the EMIF of dsp chip；The selection of FLASH mainly considers reliability, capacity, access time, writes week Phase and erasing cycle, power consumption and the compatibility with dsp chip.

EMIF is external memory bus interface, and the CE0 spaces of the interface are connected to a piece of synchronous DRAM （SDRAM）, a piece of FLASH memory for depositing program of CE1 spaces connection, CE3 and CE4 spaces are connected to FPGA peripheries electricity Road；GPIO is universaling I/O port, GPIO and interrupt signal（INT）It is connected to FPGA peripheral circuit.The reset circuit of DSP refer to for Dsp system provides initializing signal so as to return to a process of initial condition, and there is provided a hand-reset；Electricity Power Monitoring Unit chip used in the monitoring module of source, is capable of the state of automatic identification dsp chip and sends reset signal.

FPGA peripheral circuit include fpga chip, RS422 bus modules, RS232 bus modules, CAN module and Mileage and pps pulse per second signal module, the RS422 bus modules include RS422 receptors, full duplex RS422 transceiver and first Optical coupling isolator, the RS422 receptors and full duplex RS422 transceiver are connected with the first optical coupling isolator；The RS232 Bus module includes RS232 receptors, RS232 transmitters and the second optical coupling isolator, and the RS232 receptors and RS232 send out Device is sent to be connected with the second optical coupling isolator；The CAN module include CAN transceiver, the 3rd optical coupling isolator and CAN controller, the CAN transceiver, the 3rd optical coupling isolator and CAN controller are sequentially connected；Described One optical coupling isolator, the second optical coupling isolator and CAN controller are connected with fpga chip；The mileage and pulse per second (PPS) are believed Number module includes level match module and buffer chip, and the level match module and buffer chip are connected with fpga chip.

FPGA is mainly the bridge of DSP peripheral circuits, and the peripheral hardware in addition to FPGA will first pass through FPGA and be driven, complete Transmitting-receiving, data prediction and packing into data etc., in order that the communication between FPGA peripheral circuit and DSP peripheral circuits is more Convenient and flexible, the external bus interface and its two-way chip selection signal CE2 and CE3 of DSP peripheral circuits are all connected to FPGA, and Several universal input/output interfaces of DSP（GPIO）With external interrupt input interface（INT）Also it is connected with fpga chip.RS422 What RS422 was received in bus module is gyro data, and gyro data is referred to and utilizes inertance element（Gyroscope and accelerometer）Survey The acceleration of motion and angular velocity information of amount carrier.What RS232 bus modules were received is GPS, barometrical information.

Further, the micro- disk control system based on DSP and FPGA, the DSP peripheral circuits also include buffer module, institute State buffer module to be connected with the jtag interface of dsp chip.Jtag interface be used for be connected with external emulator, be easy to program debugging with Download, buffer module can make jtag interface and the more preferable exchange data of emulator.

Further, the micro- disk control system based on DSP and FPGA, also including the first active crystal oscillator and the second active crystalline substance Shake, the first active crystal oscillator is connected with fpga chip, the second active crystal oscillator is connected with the CLK of dsp chip.Active crystal oscillator It is a complete agitator, it does not need the internal oscillator of DSP, signal quality is good, more stable, and connected mode letter It is single, it is not necessary to complicated configuration circuit.

This utility model compared with prior art, has the following advantages and advantages：

1st, in this utility model, FPGA can solve the problem that the data of the Signal Pretreatment algorithm process of low layer are big, to processing speed Degree has high demands but the relatively simple problem of operating structure, and DSP can solve the problem that the data volume lower level of high-rise Processing Algorithm, algorithm It is few, but the complicated problem of the control structure of algorithm, speed and motility are taken into account with reference to FPGA and DSP, improve data acquisition speed Degree, precision and system stability；

2nd, in this utility model, using Power Monitoring Unit and hand-reset, hand-reset is artificial action, according to using Person needs flexibly control resetting time, and Power Monitoring Unit uses the shape of Power Monitoring Unit chip automatic identification dsp chip State, can automatically send reset signal.

Description of the drawings

Accompanying drawing described herein is used for providing further understanding this utility model embodiment, constitutes the one of the application Part, does not constitute the restriction to this utility model embodiment.In the accompanying drawings：

Fig. 1 is this utility model structural representation.

Specific embodiment

To make the purpose of this utility model, technical scheme and advantage become more apparent, with reference to embodiment and accompanying drawing, The utility model is described in further detail, and exemplary embodiment of the present utility model and its explanation are only used for explaining this Utility model, is not intended as to restriction of the present utility model.

Embodiment

As shown in figure 1, the micro- disk control system based on DSP and FPGA, including DSP peripheral circuits and FPGA peripheral circuit, The DSP peripheral circuits include dsp chip, Power Monitoring Unit, hand-reset, SDRAM and FLASH, the Power Supply Monitoring mould Block is connected with the RST of dsp chip, and the hand-reset is connected with Power Monitoring Unit, described SDRAM, FLASH with DSP cores The EMIF connections of piece.

EMIF is external memory bus interface, when RAM capacity can not meet system program and data storage in dsp chip When, memory expansion just need to be carried out outside piece, EMIF must be passed through when dsp chip accesses chip external memory, what EMIF was supported deposits Reservoir type includes synchronization burst static state RAM（SBSRAM）, synchronous dynamic ram（SDRAM）, asynchronous device, outside shared storage The device in device space.Dsp chip selects the EMIF of TMS320C6713, TMS320C6713 to realize that nothing is sewed up to above-mentioned memorizer Mouthful, the whole space outerpace capacity of EMIF is 64MB, is divided into four space CE0-CE3, and each CE space is mutually completely independent, EMIF data-bus widths are 32Bit, while supporting the depositor of 8/16Bit.Because dsp chip does not possess power down program storage Ability, so DSP peripheral circuits must be provided with a piece of rom chip for power down save routine, uses here FLASH.FLASH is a kind of high speed, electrically erasable, rewritable nonvolatile memory, is quite suitable for Digital Signal Processing System.FLASH chip selects SST39VF3201, and the chip has wider read-write voltage range（2.7V~3.6V）, it is wider Operating temperature range（- 40 degrees Celsius ~+85 degrees Celsius）Read or write speed faster, can be supporting the erasing mode of Three models. Dsp chip is set to 16Bit external ROM loading modes, when upper electric automatically with 16Bit patterns read CE1 spaces company 1KB contents in the external ROM for connecing are loaded into internal program memory and run, and the program more than 1KB is accomplished by by program Design carries out second load process to DSP.

Due to the memory headroom for there was only 256Kbyte in dsp chip piece, capacity have chosen for 2M* according to design requirement Outside high-speed memory of the SDRAM chips of 32bit as DSP.SDRAM chips are from semiconductor company of Micron Technology MT48LC2M32B2TG, the chip has technical grade operating temperature range（- 40 degrees Celsius ~+85 degrees Celsius）, can support to be up to The clock rate of 166MHz, SDRAM is assigned as the CE0 spaces of dsp chip.

The reset circuit of DSP to be referred to and provide initializing signal for dsp system so as to return to a mistake of initial condition Journey, TMS320C6713 chips are resetted by RESET, Low level effective, and input pulse width requires to be less than 100ns, at this In embodiment, the reset circuit of dsp chip adopts a piece of power management chip for core, and the chip is from TI companies TPS3836K33DBV, its input of Power Monitoring Unit all the way is connected to 3.3V power supplys, plays detection 3.3V supply voltages Effect, its threshold voltage is 2.93V, and when supply voltage is less than 2.93V, the chip will reset DSP.When voltage is higher than again 2.93V after, the chip will time delay for a period of time（10ms or 200ms are optional）After discharge reset signal（Output high level）.By In when 1.2V core voltages are abnormal 3.3VI/O voltages have been ready in the design of regulated power supply also without the circuit of output Logic, so only needing individually to monitor 3.3V voltages, so that it may realize 1.2V and 3.3V wherein have a power down or it is abnormal just can be with Dsp chip is set to reset, so as to be integrated with electrification reset and abnormity of power supply two functions of reset.Another road of TPS3836K33DBV The watchdog reset that monitoring is connected to hand-reset and is produced by FPGA, will drag down the level of the pin during hand-reset.Again Watchdog pulse signal is sent by GPIO pin FPGA of DSP, is supervised in the module of one watchdog function of FPGA internal builds The pulse that control DSP is sended over, when pulse is abnormal, FPGA will drag down the input pin of monitoring chip, and flip chip answers it Bit DSP, is so achieved that the Integrated design of hand-reset and watchdog reset function.TMS320C6713 is integrated with standard Jtag interface, for connection system plate and emulator, debugging emulation and download program is carried out by the interface to DSP.

FPGA peripheral circuit include fpga chip, RS422 bus modules, RS232 bus modules, CAN module and Mileage and pps pulse per second signal module, the RS422 bus modules include RS422 receptors, full duplex RS422 transceiver and first Optical coupling isolator, the RS422 receptors and full duplex RS422 transceiver are connected with the first optical coupling isolator；The RS232 Bus module includes RS232 receptors, RS232 transmitters and the second optical coupling isolator, and the RS232 receptors and RS232 send out Device is sent to be connected with the second optical coupling isolator；The CAN module include CAN transceiver, the 3rd optical coupling isolator and CAN controller, the CAN transceiver, the 3rd optical coupling isolator and CAN controller are sequentially connected；Described One optical coupling isolator, the second optical coupling isolator and CAN controller are connected with fpga chip；The mileage and pulse per second (PPS) are believed Number module includes level match module and buffer chip, and the level match module and buffer chip are connected with fpga chip.

RS232 is STD bus most widely used in asynchronous communication, and using negative logic, information source end -5V ~ -15V is logic Level"1", 5V ~+15V is level "0".Receiving terminal -3V ~ -15V is logical one level, and 3V ~+15V is level "0", and noise holds It is limited to 2V.This signal level is different from the Transistor-Transistor Logic level of routine, needs electrical level transferring chip to realize the conversion of TTL to RS232. RS232 buses include that two-way RS232 is received and 2 road RS232 send.Pass through optical coupling isolator between RS232 bus ends and FPGA Isolation, RS232 bus ends are powered and are provided by the isolation voltage stabilizing 3.3V of power pack, to realize the requirement of electrical isolation.Bus is received Dual pathways RS232 transceiving chip MAX3232ESE of the chip from MAXIM companies is sent out, it has low in energy consumption, baud rate high and valency The low advantage of lattice.External capacitor is only 0.1uF or 1uF, supply voltage 3.3V, and traffic rate is up to 120kbps, operating temperature model Enclose is -40 degrees Celsius ~+85 degrees Celsius.Isolation optocoupler is from the miniature high-speed data opto-coupler chip FODM8071 for flying million companies, work Make temperature range for -40 degrees Celsius ~+110 degrees Celsius, up to 20Mbit/s, compatible 3.3V/5V powers and is message transmission rate System.

RS422 and RS232 maximum difference is that RS422 receives and dispatches mode using balanced type difference, is passed using two lines Defeated signal, has been inherently eliminated grounding interference.The anti-strong antijamming capability of which, transmission range is farther out.In the present embodiment, RS422 bus runs have six tunnels, wherein three road RS422 are simply received, in addition three tunnels are full duplexs.RS422 bus ends and FPGA Isolated by optical coupling isolator, realize the requirement that electrical equipment is isolated.Three road RS422 receive total from 4 passage RS422 of Maxim Line reception chip MAX3096ESE, running voltage 3.3V, up to 10Mbps, 3 tunnel full duplexs RS422 communications are from complete for traffic rate Duplexing RS422 communication chips MAX3490, its running voltage is 3.3V, and traffic rate is also selected up to 10Mbps, isolation optocoupler Fly the miniature high-speed data opto-coupler chip FODM8071 of million companies.

Data are connected through optocoupler after CAN transceiver with CAN controller in CAN module, by CAN controller to the decoding data that receives, then by decoded data is activation to FPGA.CAN transceiver is CAN total Physical connection between line communication controler and physical bus, it can provide the differential transmitting capacity and CAN controller of bus Differential receiving ability.CAN transceiver selects the SN65HVD230QDQ1 of TI companies, supply voltage in the present embodiment 3.3V, low-power consumption, compatible PCA82C250 pins, traffic rate up to 1Mbps, with Thermal shutdown defencive function, operating temperature model Enclose -40 degrees Celsius ~+125 degrees Celsius.Isolation optocoupler is from the miniature high-speed data opto-coupler chip FODM8071 for flying million companies.CAN Bus control unit is the core of bus communication, is responsible for carrying out the data in bus the work of coding and decoding.CAN in the present embodiment Bus control unit is from the MCP2515 of Microchip companies, and it is a independent control Area Network protocol controller, complete It is complete to support CANV2.0B technical specifications.The device can send and receive standard or growth data frame and remote frame.MCP2515 is certainly Two examination mask registers and six acceptance filtenng depositors of band can filter out undesired message, therefore reduce place The expense of reason device.The connection of MCP2515 and FPGA is realized by standard Serial Peripheral interface.

Mileage signal and pps pulse per second signal are pulse signals, and its low level is 1V to the maximum, and high level is 4.5V ~ 12V, is needed System is counted to it, and mileage signal directly can not be connected with FPGA, this be because signal level characteristic is not corresponded, therefore mileage believe Number a level match buffer circuit is first passed through, do being connected to FPGA after corresponding level buffer and shaping and counted accordingly Number is processed.

Based on micro- disk data handling system of DSP, also including the first active crystal oscillator and the second active crystal oscillator, the present embodiment In, the frequency of the first active crystal oscillator and the second active crystal oscillator adopts 4.096MHz, the first active crystal oscillator and fpga chip Connection, the second active crystal oscillator is connected with the CLK of dsp chip.Active crystal oscillator is a complete agitator, and it need not The internal oscillator of DSP, signal quality is good, more stable, and connected mode is simple, it is not necessary to complicated configuration circuit.

Above-described specific embodiment, is entered to the purpose of this utility model, technical scheme and beneficial effect One step is described in detail, be should be understood that and be the foregoing is only specific embodiment of the present utility model, is not used to limit Fixed protection domain of the present utility model, all any modifications within spirit of the present utility model and principle, made, equivalent are replaced Change, improve, should be included within protection domain of the present utility model.

Claims (3)

1. micro- disk control system of DSP and FPGA is based on, it is characterised in that including DSP peripheral circuits and FPGA peripheral circuit, institute State DSP peripheral circuits to be connected with FPGA peripheral circuit；The DSP peripheral circuits include dsp chip, Power Monitoring Unit, manually Reset, SDRAM and FLASH, the Power Monitoring Unit is connected with the RST of dsp chip, the hand-reset and Power Supply Monitoring mould Block connects, and described SDRAM, FLASH are connected with the EMIF of dsp chip；

The FPGA peripheral circuit include fpga chip, RS422 bus modules, RS232 bus modules, CAN module and Mileage and pps pulse per second signal module, the RS422 bus modules include RS422 receptors, full duplex RS422 transceiver and first Optical coupling isolator, the RS422 receptors and full duplex RS422 transceiver are connected with the first optical coupling isolator；The RS232 Bus module includes RS232 receptors, RS232 transmitters and the second optical coupling isolator, and the RS232 receptors and RS232 send out Device is sent to be connected with the second optical coupling isolator；The CAN module include CAN transceiver, the 3rd optical coupling isolator and CAN controller, the CAN transceiver, the 3rd optical coupling isolator and CAN controller are sequentially connected；Described One optical coupling isolator, the second optical coupling isolator and CAN controller are connected with fpga chip；The mileage and pulse per second (PPS) are believed Number module includes level match module and buffer chip, and the level match module and buffer chip are connected with fpga chip.

2. the micro- disk control system based on DSP and FPGA according to claim 1, it is characterised in that DSP peripheries electricity Road also includes buffer module, and the buffer module is connected with the jtag interface of dsp chip.

3. the micro- disk control system based on DSP and FPGA according to claim 1, it is characterised in that also have including first Source crystal oscillator and the second active crystal oscillator, the first active crystal oscillator is connected with fpga chip, the second active crystal oscillator and dsp chip CLK connection.