CN105893307B - A kind of high speed big data quantity information processing system - Google Patents
A kind of high speed big data quantity information processing system Download PDFInfo
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- CN105893307B CN105893307B CN201610192967.3A CN201610192967A CN105893307B CN 105893307 B CN105893307 B CN 105893307B CN 201610192967 A CN201610192967 A CN 201610192967A CN 105893307 B CN105893307 B CN 105893307B
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- G06F13/38—Information transfer, e.g. on bus
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Abstract
A kind of high speed big data quantity information processing system is related to integrated navigation and technical field of image processing, including multi-core DSP processing module, FPGA data preprocessing module, High-speed Interface Card and other accessory circuits composition.Wherein, multi-core DSP processing module is data core processing module, is responsible for the functions such as data processing, Informationflow Control, external information exchange.The functions such as FPGA data preprocessing module is responsible for external data encoding and decoding pretreatment, logic control, image are shown.High-speed Interface Card includes high speed Ethernet interface, Spacewire interface, high-speed expansion interface etc., is realized and external high speed data transfer.Other accessory circuit modules of system include clock module, power module etc.；The high-speed data processing system that the present invention realizes can be used for running three Integrated Navigation Algorithm of IMU/GPS/ starlight, compared to the system schema of the more plates of single DSP, more DSP veneers or the more plates of more DSP, there are the distinguishing features such as high, at low cost, the strong, rich interface of processing capacity of integrated level.
Description
Technical field
The present invention relates to a kind of integrated navigation and technical field of image processing, at especially a kind of high speed big data quantity information
Reason system.
Background technique
In the technical fields such as integrated navigation and image procossing, a large amount of navigation data and image are to real time signal processing ability
It is required that it is higher and higher, data processing complexity is increasing, integrated navigation is required using can carry out matched method automatically, and
And quite high precision and very high real-time are required, these require that the research to image matching algorithm is more deep.And it is same
When its application environment have stringent limitation again to system power dissipation, size, due to being limited by single dsp processor resource,
High-speed data collecting and processing and in real time analysis, signal largely handle and in terms of be not able to satisfy its requirement.Therefore it needs
Arithmetic speed is faster, capacity is bigger, the lower digital processing platform of power consumption realizes these functional requirements.Based on monokaryon DSP's
Signal processing implementation is difficult to adapt to the new demand that macrooperation amount is handled in real time, and traditional DSP interconnection technique is by multiple lists
Core DSP is linked together with high-speed interface, the real-time Transmission abilities of data, main control dsp processor resource overhead will
The bottleneck for becoming system with the increase from processing dsp processor quantity of series winding, to limit at the extension and reality of system
The raising of rationality energy can not sufficiently meet the processing requirement of big, strong real-time the field of signal processing of data volume, while this
The system architecture of sample can bring the problem of power consumption and size aspect.
Summary of the invention
It is an object of the invention to overcome the above-mentioned deficiency of the prior art, a kind of high speed big data quantity information processing system is provided
System, the system are had a clear superiority in terms of power consumption and chip area, execution efficiency using multi-core DSP, and it is real that high speed may be implemented
When the miniaturization of parallel processing platform, low power dissipation design, significantly improve the Signal and Information Processing ability of information processing system.
Above-mentioned purpose of the invention is achieved by following technical solution:
A kind of high speed big data quantity information processing system, including High-speed Interface Card, multi-core DSP circuit module, FPGA number
Data preprocess module and accessory circuit module；
High-speed Interface Card: teledata, data and the bus data between information processing board that external equipment transmits are received；It connects
Data request signal between the multi-core DSP circuit module teledata request signal transmitted and plate is received, at teledata and information
Data are sent to multi-core DSP circuit module between reason plate；Receive the bus differential request of data that FPGA data preprocessing module transmits
Bus data is sent to FPGA data preprocessing module by signal；
Multi-core DSP circuit module: teledata request signal is sent to High-speed Interface Card, High-speed Interface Card is received and passes
The teledata come；Data request signal receives at the information that High-speed Interface Card transmits to High-speed Interface Card between transmission board
Data between reason plate；Receive the state preprocessed data that FPGA data preprocessing module transmits；Mould is pre-processed when receiving FPGA data
After the state control signal that block transmits, multi-core DSP module is between data, state preprocessed data teledata, information processing board
Information fusion is carried out, generates standardization status information, and standardization status information is transmitted back to FPGA data preprocessing module；
FPGA data preprocessing module: the serial data and analog signal that external system transmits are received；Serial data is turned
It is changed to bus differential data request signal, bus differential data request signal is sent to High-speed Interface Card；Receive high quick access
The bus data that mouth mold block transmits；Convert analog signals into digital signal；Bus data and digital signal are successively filtered
Wave, denoising, encoding and decoding pre-process generation state preprocessed data, and state preprocessed data is sent to multi-core DSP circuit module；
State control signal is sent to multicore DSP circuit block；Receive the standardization status information that multi-core DSP circuit module transmits；
Accessory circuit module: DSP clock signal and DSP power supply are provided for multi-core DSP circuit module；Locate in advance for FPGA data
It manages module and FPGA clock signal and FPGA power supply is provided.
In a kind of above-mentioned high speed big data quantity information processing system, the High-speed Interface Card include gigabit network interface,
Spacewire interface and RapidIO interface；The teledata that the transmission of kilomega network interface external equipment comes is more receiving
After the teledata request signal that core DSP circuit block transmits, by remote data transmission to multicore DSP circuit block；RapidIO
Data between the information processing board that interface external equipment transmits, the data between receiving the plate that multi-core DSP circuit module transmits
After request signal, data between information processing board are transmitted to multi-core DSP circuit module；Spacewire interface external equipment
The bus data transmitted, after receiving the bus differential data request signal that FPGA data preprocessing module transmits, by bus
Data are transmitted to FPGA data preprocessing module.
In a kind of above-mentioned high speed big data quantity information processing system, the multi-core DSP circuit module includes multi-core DSP mould
Block, Flash module, DDR module and EEPROM module；
Multi-core DSP module: teledata request signal is sent to High-speed Interface Card；Receive what High-speed Interface Card transmitted
Teledata is sent to DDR module by teledata；Data request signal receives high speed to High-speed Interface Card between transmission board
Data between information processing board are sent to Flash module by data between the information processing board that interface module transmits；Receive FPGA data
The state preprocessed data that preprocessing module transmits；After receiving the state control signal that FPGA data preprocessing module transmits,
Multi-core DSP module carries out information fusion to data, state preprocessed data teledata, information processing board, generates standardization
Status information, and standardization status information is transmitted back to FPGA module；
DDR module: it receives multi-core DSP module and transmits teledata, store teledata；When multi-core DSP circuit module connects
After receiving the state control signal that transmits of FPGA data preprocessing module, the teledata of storage is transmitted to multicore DSP circuit block；
Flash module: receiving data between the information processing board that multi-core DSP module transmits, and stores data between information processing board；
After multi-core DSP circuit module receives the state control signal that FPGA data preprocessing module transmits, transmit at the information of storage
Data are to multicore DSP circuit block between managing plate；
EEPROM module receives the state preprocessed data storage signal of multi-core DSP storage system, storage system status
Preprocessed data；After multi-core DSP circuit module receives the state control signal that FPGA data preprocessing module transmits, transmission is deposited
The system mode preprocessed data of storage is to multicore DSP circuit block；
In a kind of above-mentioned high speed big data quantity information processing system, FPGA data preprocessing module include FPGA module,
Extend 422 serial port modules and AD acquisition module；
It extends 422 serial port modules: receiving the serial data that external system transmits；When the serial ports for receiving FPGA module and transmitting
After data acquisition control signal, data reading, filtering, denoising, decoding process are successively carried out to serial data, generate bus differential
Data request signal is sent to High-speed Interface Card by FPGA module；And the inside of serial data write-in FPGA module is delayed
It deposits；
AD acquisition module: it receives external system and transmits analog signal；It is controlled when receiving the AD conversion that FPGA module transmits
After signal, data acquisition, AD conversion are carried out to analog signal, digital signal is sent to by the digital signal after generating AD conversion
FPGA module；
FPGA module: serial port data acquisition control signal is sent to 422 serial port modules of extension；Receive 422 serial ports moulds of extension
The serial data that block transmits, and the inner buffer of FPGA module is written；It receives and receives the bus differential that 422 serial port modules of extension transmit
Data request signal；Bus differential data request signal is sent to High-speed Interface Card；Receive what High-speed Interface Card transmitted
Bus data；It sends AD conversion and controls signal to AD acquisition module；Number letter after receiving the AD conversion that AD acquisition module transmits
Number；Receive the bus data that High-speed Interface Card transmits；Digital signal and bus data are successively filtered, denoised, compiles solution
Code pretreatment generation state preprocessed data, is sent to multi-core DSP circuit module for state preprocessed data；FPGA module is sent
Signal is controlled to multi-core DSP circuit module, receives the standardization status information that multi-core DSP circuit module is sent.
In a kind of above-mentioned high speed big data quantity information processing system, the accessory circuit module include clock module and
Power module；Clock module provides clock signal for multi-core DSP circuit module and FPGA data preprocessing module；Power module is
Multi-core DSP circuit module and FPGA data preprocessing module provide power supply.
In a kind of above-mentioned high speed big data quantity information processing system, the clock module includes multiple clock sources, respectively
1 road 66.67MHZ clock signal, 3 road 100MHZ clock signals, 2 road 312.5MHZ clocks letter are provided for multi-core DSP circuit module
Number；1 road 50MHZ clock source is provided for FPGA.
In a kind of above-mentioned high speed big data quantity information processing system, the multi-core DSP module is to teledata, information
Data, state preprocessed data are successively filtered denoising, image segmentation, image enhancement processing between processing board, are then counted
According to registration, by coordinate transform and unit conversion, the teledata received, data, state are pre-processed between information processing board
Data are transformed into unified expression-form, carry out data fusion using Kalman filtering algorithm, obtain fused system standard
Change status information.
In a kind of above-mentioned high speed big data quantity information processing system, external system and high speed big data quantity information processing system
The rate that data double-way transmits between system is 12500M/min data bit, SpaceWire bus in high speed big data quantity system
Message transmission rate is 200Mbps.
In a kind of above-mentioned high speed big data quantity information processing system, the multi-core DSP module is provided with support 10/
The high speed data transfer with remote terminal is realized in the kilomega network port of 100/1000Mbps data transmission bauds.
In a kind of above-mentioned high speed big data quantity information processing system, the multi-core DSP circuit module memory capacity:
SDRAM--4Gbit；Bandwidth > 200MB/s；Solid-state memory has 512Mb capacity, E2PROM:1M using NAND FLASH.
The invention has the following advantages over the prior art:
(1) present invention is different from background technique, using the parallel-processing hardware framework based on FPGA+ multi-core DSP.Pass through
High performance DSP, the floating-point operation per second that can be performed several hundred G times, is well positioned to meet the demand of complicated algorithm.To some knots
The relatively simple bottom layer signal processing of structure, is realized using FPGA hardware.The processing speed and FPGA that dsp chip can be taken into account can weigh
The flexibility of configuration, different types of processing task in classifying rationally system, plays respective excellent in terms of software and hardware two
Gesture effectively improves the execution efficiency of algorithm in system.
(2) multi-core DSP circuit module multi-core DSP runs the parallel processing algorithm based on MPI, efficiently solves combination and leads
The parallel processing for data of navigating, the 1/7 of 8 core parallel processing time minimum monokaryons；System memory size: SDRAM--4Gbit
(4*64M*16bit), bandwidth > 200MB/s；Solid-state memory has 512Mb (64M*8bit) capacity using NAND FLASH,
E2PROM:1M.Substantially increase system memory space and efficiency, realize multi-signal it is real-time, facilitate transmission, magnanimity to deposit
The signal processing requirements such as storage, information fusion；
(3) FPGA data preprocessing module is the Data Stream Processing applied in front end, executes the pre- places such as data acquisition, filtering
Reason task realizes the sending and receiving of SpaceWire or LVDS bus data, external data A/D conversion and RS422 serial ports
Image and data pretreatment；Within 60 second time, achievable 12500M between external system and high speed big data quantity system
The high speed data bus interface data transmission rate of the transmitted in both directions of data bit, system can reach 200Mbps, conveniently realize remote
Data, the acquisition of Spacewire bus data and transmission etc. require between number of passes evidence, plate；
(4) the high-speed data processing system that the present invention realizes can be used for running three integrated navigation of IMU/GPS/ starlight calculation
Method, compared to the system schema of the more plates of single DSP, more DSP veneers or the more plates of more DSP, processing energy high, at low cost with integrated level
The distinguishing features such as the strong, rich interface of power.
Detailed description of the invention
Fig. 1 is high speed big data quantity information processing system structural block diagram of the present invention；
Fig. 2 is high speed big data quantity information processing system circuit diagram of the present invention；
Fig. 3 is FPGA data preprocessing module SpaceWire signal drive circuit figure of the present invention；
Fig. 4 is high speed interface module SpaceWire signal drive circuit figure of the present invention.
Specific embodiment
The present invention is described in further detail in the following with reference to the drawings and specific embodiments:
The rate of data double-way transmission is between high speed big data quantity information processing system and external system of the present invention
12500M/min, SpaceWire bus data transfer rate is 200Mbps in high speed big data quantity system.
It is as shown in Figure 1 high speed big data quantity information processing system structural block diagram, as seen from the figure, a kind of high speed big data quantity
Information processing system, including High-speed Interface Card, multi-core DSP circuit module, FPGA data preprocessing module and accessory circuit mould
Block；
High-speed Interface Card: teledata, data and the bus data between information processing board that external equipment transmits are received；It connects
Data request signal between the multi-core DSP circuit module teledata request signal transmitted and plate is received, at teledata and information
Data are sent to multi-core DSP circuit module between reason plate；Receive the bus differential request of data that FPGA data preprocessing module transmits
Bus data is sent to FPGA data preprocessing module by signal；
Wherein, High-speed Interface Card includes gigabit network interface, Spacewire interface and RapidIO interface；Gigabit network interface
The teledata that external equipment transmission comes is received, after receiving the teledata request signal that multi-core DSP circuit module transmits,
By remote data transmission to multicore DSP circuit block；Number between the information processing board that RapidIO interface external equipment transmits
According to data between information processing board being transmitted to more between receiving the plate that multi-core DSP circuit module transmits after data request signal
Core DSP circuit block；The bus data that Spacewire interface external equipment transmits is receiving FPGA data pretreatment
After the bus differential data request signal that module transmits, by bus data transfer to FPGA data preprocessing module.
Multi-core DSP circuit module: teledata request signal is sent to High-speed Interface Card, High-speed Interface Card is received and passes
The teledata come；Data request signal receives at the information that High-speed Interface Card transmits to High-speed Interface Card between transmission board
Data between reason plate；Receive the state preprocessed data that FPGA data preprocessing module transmits；Mould is pre-processed when receiving FPGA data
After the state control signal that block transmits, multi-core DSP module is between data, state preprocessed data teledata, information processing board
Information fusion is carried out, generates standardization status information, and standardization status information is transmitted back to FPGA data preprocessing module；It is more
Core DSP circuit block memory capacity: SDRAM--4Gbit；Bandwidth > 200MB/s；Solid-state memory is had using NANDFLASH
512Mb capacity, E2PROM:1M.
Wherein, multi-core DSP circuit module includes multi-core DSP module, Flash module, DDR module and EEPROM module；Its
In
Multi-core DSP module: teledata request signal is sent to High-speed Interface Card；Receive what High-speed Interface Card transmitted
Teledata is sent to DDR module by teledata；Data request signal receives high speed to High-speed Interface Card between transmission board
Data between information processing board are sent to Flash module by data between the information processing board that interface module transmits；Receive FPGA data
The state preprocessed data that preprocessing module transmits；After receiving the state control signal that FPGA data preprocessing module transmits,
Multi-core DSP module carries out information fusion to data, state preprocessed data teledata, information processing board, generates standardization
Status information, and standardization status information is transmitted back to FPGA module；
Multi-core DSP module is successively filtered data, state preprocessed data teledata, information processing board
It makes an uproar, image segmentation, image enhancement processing, then carries out Registration of Measuring Data, it is remote what is received by coordinate transform and unit conversion
Data, state preprocessed data are transformed into unified expression-form between number of passes evidence, information processing board, using Kalman filtering algorithm
Data fusion is carried out, fused system standardization status information is obtained.
Multi-core DSP module is provided with the kilomega network port for supporting 10/100/1000Mbps data transmission bauds, realizes and remote
The high speed data transfer of journey terminal.
DDR module: it receives multi-core DSP module and transmits teledata, store teledata；When multi-core DSP circuit module connects
After receiving the state control signal that transmits of FPGA data preprocessing module, the teledata of storage is transmitted to multicore DSP circuit block；
Flash module: receiving data between the information processing board that multi-core DSP module transmits, and stores data between information processing board；
After multi-core DSP circuit module receives the state control signal that FPGA data preprocessing module transmits, transmit at the information of storage
Data are to multicore DSP circuit block between managing plate；
EEPROM module receives the state preprocessed data storage signal of multi-core DSP storage system, storage system status
Preprocessed data；After multi-core DSP circuit module receives the state control signal that FPGA data preprocessing module transmits, transmission is deposited
The system mode preprocessed data of storage is to multicore DSP circuit block.
FPGA data preprocessing module: the serial data and analog signal that external system transmits are received；Serial data is turned
It is changed to bus differential data request signal, bus differential data request signal is sent to High-speed Interface Card；Receive high quick access
The bus data that mouth mold block transmits；Convert analog signals into digital signal；Bus data and digital signal are successively filtered
Wave, denoising, encoding and decoding pre-process generation state preprocessed data, and state preprocessed data is sent to multi-core DSP circuit module；
State control signal is sent to multicore DSP circuit block；Receive the standardization status information that multi-core DSP circuit module transmits；
Wherein, FPGA data preprocessing module includes FPGA module, 422 serial port modules of extension and AD acquisition module；
It extends 422 serial port modules: receiving the serial data that external system transmits；When the serial ports for receiving FPGA module and transmitting
After data acquisition control signal, data reading, filtering, denoising, decoding process are successively carried out to serial data, generate bus differential
Data request signal is sent to High-speed Interface Card by FPGA module；And the inside of serial data write-in FPGA module is delayed
It deposits；
AD acquisition module: it receives external system and transmits analog signal；It is controlled when receiving the AD conversion that FPGA module transmits
After signal, data acquisition, AD conversion are carried out to analog signal, digital signal is sent to by the digital signal after generating AD conversion
FPGA module；
FPGA module: serial port data acquisition control signal is sent to 422 serial port modules of extension；Receive 422 serial ports moulds of extension
The serial data that block transmits, and the inner buffer of FPGA module is written；It receives and receives the bus differential that 422 serial port modules of extension transmit
Data request signal；Bus differential data request signal is sent to High-speed Interface Card；Receive what High-speed Interface Card transmitted
Bus data；It sends AD conversion and controls signal to AD acquisition module；Number letter after receiving the AD conversion that AD acquisition module transmits
Number；Receive the bus data that High-speed Interface Card transmits；Digital signal and bus data are successively filtered, denoised, compiles solution
Code pretreatment generation state preprocessed data, is sent to multi-core DSP circuit module for state preprocessed data；FPGA module is sent
Signal is controlled to multi-core DSP circuit module, receives the standardization status information that multi-core DSP circuit module is sent.
Accessory circuit module: DSP clock signal and DSP power supply are provided for multi-core DSP circuit module；Locate in advance for FPGA data
It manages module and FPGA clock signal and FPGA power supply is provided.
Wherein, accessory circuit module includes clock module and power module；Clock module be multi-core DSP circuit module and
FPGA data preprocessing module provides clock signal；Power module is multi-core DSP circuit module and FPGA data preprocessing module
Power supply is provided.
Clock module includes multiple clock sources, and respectively multi-core DSP circuit module provides 1 road 66.67MHZ clock signal, 3
Road 100MHZ clock signal, 2 road 312.5MHZ clock signals；1 road 50MHZ clock source is provided for FPGA.
It is illustrated in figure 2 high speed big data quantity information processing system circuit diagram, as seen from the figure, the choosing of multi-core DSP chip
With the newest 8 core high-performance processor TMS320C6678 chip of TI company, the height with external equipment is realized by High-speed Interface Card
Fast data exchange, operation Multi-task Concurrency program realize the high speed processing of the navigation data including image.
DDR3SDRAM memory provides external storage resources to multi-core DSP processor.DDR3 SDRAM memory is by 4
DDR3 memory chip K4B1G1646X-HCH9 parallel connection is constituted, monolithic memory capacity 1Gbit, four 256MB*8bit in total.
Flash uses Nor Falsh chip, is connect by SPI interface with dsp chip, is the memory module of system program.
Eeprom chip M24M01-HRMN6TP and DSP pass through I2The connection of C bus, the startup program for storage system.
It is illustrated in figure 2 high speed big data quantity information processing system circuit diagram, as seen from the figure:
Multi-core DSP circuit module
Multi-core DSP circuit module is core data processing module, including multi-core DSP, Flash circuit, DDR circuit and
Multi-core DSP chip described in eeprom circuit selects the newest 8 core high-performance processor TMS320C6678 chip of TI company, passes through height
Fast interface module realization is exchanged with the high-speed data of external equipment, and operation Multi-task Concurrency program realizes leading including image
The high speed processing for data of navigating.The DDR circuit uses DDR3 memory, hosted control when operation as DSP program.DDR3 is deposited
Four parallel connections of reservoir, are connect by the DDR3EMIF interface of DSP with DSP.The Flash uses Nor Falsh chip, passes through
SPI interface is connect with dsp chip, is the program storage block of system.The EEPROM and DSP pass through I2The connection of C bus, is used for
The startup program of storage system.
Multi-core DSP circuit module is the workbench that multi-core DSP processor carries out Digital Signal Processing.Fig. 2 gives more
The interface circuit figure of core DSP circuit block.
Multi-core DSP chip selects the newest 8 core high-performance processor TMS320C6678 chip of TI company, passes through high-speed interface
Module realization is exchanged with the high-speed data of external equipment, and operation Multi-task Concurrency program realizes the navigation data including image
High speed processing.
DDR3SDRAM memory provides external storage resources to multi-core DSP processor.DDR3 SDRAM memory is by 4
DDR3 memory chip K4B1G1646X-HCH9 parallel connection is constituted, monolithic memory capacity 1Gbit, four 256MB*8bit in total.
Flash uses Nor Falsh chip, is connect by SPI interface with dsp chip, is the memory module of system program.
Eeprom chip M24M01-HRMN6TP and DSP pass through I2The connection of C bus, the startup program for storage system.
FPGA data preprocessing module
FPGA data preprocessing module realizes the functions such as external data encoding and decoding pretreatment, logic control, data storage, packet
Include fpga chip, 422 serial port modules of extension and AD acquisition module.The fpga chip selects the XC3S200A core of Xilinx company
Piece.422 serial port modules of the extension are combined by FPGA, parallel-serial conversion chip TL16C752B, 422 serial port chip IL422
At.The AD acquisition module realizes that the data of 8 tunnel analog quantitys acquire by FPGA connection AD conversion chip, to the secondary voltage of system
It is monitored.It is connected between FPGA and dsp chip by spi bus, FPGA interior design has FIFO memory, and dsp chip is logical
The FIFO memory inside spi bus read-write FPGA is crossed, and then realizes the number between the peripheral hardware being connected with various high-speed interfaces
According to communication.
FPGA data preprocessing module includes the FPGA-XC3S200A chip of Xilinx, based on MAX9152EUE's
SpaceWire driving circuit acquires electricity based on the AD of MAX1166BCUP A/D conversion chip and CD4051BCMTC isolating chip
Road.
AD Acquisition Circuit is responsible for completing the acquisition for the analog quantity that secondary system voltage and other needs are observed, and A/D chip is selected
MAX1166BCUP every time can be acquired an analog quantity Analog-VO.The AD of FPGA control MAX1166BCUP was acquired
Journey.The analog input Analog-VO of MAX1166BCUP passes through a multichannel disconnecting switch device CD4051BCMTC from 8 road moulds
Quasi- input is selected.Effective simulation input amount of CD4051BCMTC is mainly the secondary voltage of system, CD4051BCMTC's
Control input is FPGA-AD-ctlA, FPGA-AD-ctlB and FPGA-AD-ctlC respectively from the signal of FPGA.
422 serial port modules are extended to control chip TL16C752B, 422 serial port chip IL422 by FPGA, serial ports and combine
At.The control signal of FPGA is input to TL16C752B chip, uses TL16C752B's by generating different chip selection signal selections
UARTA, UARTB or UARTC, the data line of FPGA are connected to the data port of chip TL16C752B, complete the reading of serial data
It takes or is written.
High-speed Interface Card
High-speed Interface Card realizes the high speed data transfer with external equipment, including high speed gigabit network interface, Spacewire
Interface and RapidIO interface etc..
The high speed Ethernet interface is a gigabit networking interface, is used for Remote data service, and dsp chip passes through inside
SGMII interfacing between network layer phy chip realize gigabit networking communication.The dsp chip TMS320C6678 that the present invention uses
There are two external SGMII interface, ether exchange and network exchange module, the present invention to use the 88E1111 of Marvell company for tool
The connection of physical chip realization gigabit networking.The analog signal with modulation data that network RJ45 interface sends over is passed through
A/D conversion becomes digital signal, is transferred to MAC chip by receiving unit then in turn through after balanced, shaping filter and decoding,
Realize the reception of data.
The RapidIO interface is connect for the communication for interconnecting and designing between high performance embedded system chip chamber and plate
Mouthful, 4 RapidIO interfaces of dsp chip are connected to FMC connector, realize the communication of RapidIO interface.Serial RapidIO-
For SRIO for interconnecting and designing between high performance embedded system chip chamber and plate, it will be that embedded system is mutual in the following more than ten years
Optimal selection even.TMS320C6678 provides 4 RapidIO interfaces, and 4 serial RapidIO interfaces are connected to by this programme
FMC connector, facilitates system to extend.
The SpaceWire interface be ESA joint European Space company and academia formulate jointly towards AEROSPACE APPLICATION
Novel high speed data bus standard, have the characteristics that high speed full duplex, simple and flexible, protocol open, in the present invention FPGA
By driving part MAX9152EUE connection SpaceWire interface, FPGA runs Verilog program and realizes SpaceWire data
Send and receive, SpaceWire agreement is verified existing by the codec logic SPW-IP in FPGA.
It is illustrated in figure 3 FPGA data preprocessing module SpaceWire signal drive circuit figure, is illustrated in figure 4 high speed
Data interface module SpaceWire signal drive circuit figure, as seen from the figure, FPGA preprocessing module is as SpaceWire bus
The controller of interface module extends SpaceWire interface, the signal wire FPGA_ of FPGA by MAX9152EUE driving element
SPW-TXD0-P and FPGA_SPW-TXD0-N, FPGA_SPW-TXS0-P and FPGA_SPW-TXS0-N, FPGA_SPW-TXD1-P
Divide after MAX9152EUE driving output with FPGA_SPW-TXD1-N, FPGA_SPW-TXS1-P and FPGA_SPW-TXS1-N
Not as the differential output signal SPW-TXD0-P and SPW-TXD0-N of SpaceWire bus, SPW-TXS0-P and SPW-TXS0-
N, SPW-TXD1-P and SPW-TXD1-N, SPW-TXS1-P and SPW-TXS1-N.The differential input signal line of SpaceWire bus
SPW-RXD0-P and SPW-RXD0-N, SPW-RXS0-P and SPW-RXS0-N, SPW-RXD1-P and SPW-RXD1-N, SPW-
RXS1-P and SPW-RXS1-N after MAX9152EUE drives as the input signal FPGA_SPW-RXD0-P of FPGA and
FPGA_SPW-RXD0-N, FPGA_SPW-RXS0-P and FPGA_SPW-RXS0-N, FPGA_SPW-RXD1-P and FPGA_SPW-
RXD1-N, FPGA_SPW-RXS1-P and SPW-RXS1-N.
Accessory circuit module
Accessory circuit module includes clock module and power module etc..The clock module includes multiple clock sources, system
The each clock source needed using ICS85431 and CDCL6010RGZ clock chip generation system.The power supply of the accessory circuit
Module generates the power supply signal of multiple voltage value, and power module passes through UCD922, TPS4620, TPS54622 and TPS54231 etc.
Power supply chip generates the power supply signal of these different voltages values, uses for modules such as DSP and FPGA.
Clock circuit module is cascaded by two panels clock control chip CDCE62005RGZT, outside first clock chip
25MHZ crystal oscillator is connect, after being configured by FPGA to its register, first clock chip generates 2 road 100MHZ (as second
The input of piece clock chip), 1 road 66.67MHZ (use of DDR3 memory), two kinds of clock signals.The clock signal of 100MHZ is again
It is input to second clock chip CDCE62005RGZT, after being configured by FPGA to its register, second clock chip
Three road 100MHZ, 2 road 312.5MHZ clock signals are generated, are used for system modules.Clock circuit further includes a 50MHZ
Crystal oscillator, output supply FPGA are used.
Modules required voltage includes several electricity such as 1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V in system
Pressure, in the present invention using multi-beam power chip come voltage signal needed for generation system.System power supply inputs 12V, provides DSP core
- 0.75V that core module uses, 1V voltage, 1.2V, 1.5V, 1.8V, 1.2V, 3.3V voltage, the 1V voltage used for FPGA,
3.3V voltage signal, 5V voltage signal generate 1.5V and 0.75 voltage signal as input, by LTC3618 chip, pass through
AIC1084 generates 1.8V voltage signal all the way, generates 2 road 1.8V voltages, 2.5V voltage and 1.2V voltage by LTS3507 and believes
Number.
Implementation result:
It is different from background technique, the present invention is by using the parallel-processing hardware framework based on FPGA+ multi-core DSP, FPGA
Processing unit realize SpaceWire or LVDS bus data send and receive and the pretreatment of image data, multi-core DSP fortune
The row achievable parallel processing algorithm based on MPI, effective solution integrated navigation data high-speed, in real time, facilitate transmission, magnanimity
The processing requirements such as storage.
The content that description in the present invention is not described in detail belongs to the well-known technique of those skilled in the art.
Claims (8)
1. a kind of high speed big data quantity information processing system, it is characterised in that: including High-speed Interface Card, multi-core DSP circuit mould
Block, FPGA data preprocessing module and accessory circuit module；
High-speed Interface Card: teledata, data and the bus data between information processing board that external equipment transmits are received；It receives more
Data request signal between the core DSP circuit block teledata request signal transmitted and plate, by teledata and information processing board
Between data be sent to multi-core DSP circuit module；The bus differential data request signal that FPGA data preprocessing module transmits is received,
Bus data is sent to FPGA data preprocessing module；The High-speed Interface Card includes that gigabit network interface, Spacewire connect
Mouth and RapidIO interface；The teledata that the transmission of kilomega network interface external equipment comes, is receiving multi-core DSP circuit mould
After the teledata request signal that block transmits, by remote data transmission to multicore DSP circuit block；Outside RapidIO interface
Data between the information processing board that portion's equipment transmits, between receiving the plate that multi-core DSP circuit module transmits after data request signal,
Data between information processing board are transmitted to multi-core DSP circuit module；The number of buses that Spacewire interface external equipment transmits
According to after receiving the bus differential data request signal that FPGA data preprocessing module transmits, extremely by bus data transfer
FPGA data preprocessing module；
Multi-core DSP circuit module: teledata request signal is sent to High-speed Interface Card, receives what High-speed Interface Card transmitted
Teledata；Data request signal receives the information processing board that High-speed Interface Card transmits to High-speed Interface Card between transmission board
Between data；Receive the state preprocessed data that FPGA data preprocessing module transmits；It is passed when receiving FPGA data preprocessing module
After the state control signal come, multi-core DSP module carries out data, state preprocessed data teledata, information processing board
Information fusion generates standardization status information, and standardization status information is transmitted back to FPGA data preprocessing module；
The multi-core DSP circuit module includes multi-core DSP module, Flash module, DDR module and EEPROM module；
Multi-core DSP module: teledata request signal is sent to High-speed Interface Card；Reception High-speed Interface Card transmits long-range
Teledata is sent to DDR module by data；Data request signal receives high-speed interface to High-speed Interface Card between transmission board
Data between information processing board are sent to Flash module by data between the information processing board that module transmits；FPGA data is received to locate in advance
The state preprocessed data that reason module transmits；After receiving the state control signal that FPGA data preprocessing module transmits, multicore
DSP module carries out information fusion to data, state preprocessed data teledata, information processing board, generates standardization state
Information, and standardization status information is transmitted back to FPGA module；
DDR module: it receives multi-core DSP module and transmits teledata, store teledata；When multi-core DSP circuit module receives
After the state control signal that FPGA data preprocessing module transmits, the teledata of storage is transmitted to multicore DSP circuit block；
Flash module: receiving data between the information processing board that multi-core DSP module transmits, and stores data between information processing board；When more
After core DSP circuit block receives the state control signal that FPGA data preprocessing module transmits, the information processing board of storage is transmitted
Between data to multicore DSP circuit block；
EEPROM module receives the state preprocessed data storage signal of multi-core DSP storage system, and storage system status is located in advance
Manage data；After multi-core DSP circuit module receives the state control signal that FPGA data preprocessing module transmits, storage is transmitted
System mode preprocessed data is to multicore DSP circuit block；
FPGA data preprocessing module: the serial data and analog signal that external system transmits are received；Serial data is converted to
Bus differential data request signal is sent to High-speed Interface Card by bus differential data request signal；Receive high-speed interface mould
The bus data that block transmits；Convert analog signals into digital signal；Bus data and digital signal are successively filtered, gone
It makes an uproar, encoding and decoding pretreatment generation state preprocessed data, state preprocessed data is sent to multi-core DSP circuit module；It sends
State control signal is to multicore DSP circuit block；Receive the standardization status information that multi-core DSP circuit module transmits；
Accessory circuit module: DSP clock signal and DSP power supply are provided for multi-core DSP circuit module；Mould is pre-processed for FPGA data
Block provides FPGA clock signal and FPGA power supply.
2. a kind of high speed big data quantity information processing system according to claim 1, it is characterised in that: FPGA data is located in advance
Reason module includes FPGA module, 422 serial port modules of extension and AD acquisition module；
It extends 422 serial port modules: receiving the serial data that external system transmits；When the serial data for receiving FPGA module and transmitting
After acquisition control signal, data reading, filtering, denoising, decoding process are successively carried out to serial data, generate bus differential data
Request signal is sent to High-speed Interface Card by FPGA module；And serial data is written to the inner buffer of FPGA module；
AD acquisition module: it receives external system and transmits analog signal；Signal is controlled when receiving the AD conversion that FPGA module transmits
Afterwards, data acquisition, AD conversion are carried out to analog signal, digital signal is sent to FPGA by the digital signal after generating AD conversion
Module；
FPGA module: serial port data acquisition control signal is sent to 422 serial port modules of extension；422 serial port modules of extension are received to pass
The serial data come, and the inner buffer of FPGA module is written；It receives and receives the bus differential data that 422 serial port modules of extension transmit
Request signal；Bus differential data request signal is sent to High-speed Interface Card；Receive the bus that High-speed Interface Card transmits
Data；It sends AD conversion and controls signal to AD acquisition module；Digital signal after receiving the AD conversion that AD acquisition module transmits；It connects
Receive the bus data that High-speed Interface Card transmits；Digital signal and bus data are successively filtered, denoised, encoding and decoding are located in advance
Generation state preprocessed data is managed, state preprocessed data is sent to multi-core DSP circuit module；FPGA module is sent to multicore
DSP circuit block controls signal, receives the standardization status information that multi-core DSP circuit module is sent.
3. a kind of high speed big data quantity information processing system according to claim 1, it is characterised in that: the attached electricity
Road module includes clock module and power module；Clock module is that multi-core DSP circuit module and FPGA data preprocessing module mention
For clock signal；Power module provides power supply for multi-core DSP circuit module and FPGA data preprocessing module.
4. a kind of high speed big data quantity information processing system according to claim 3, it is characterised in that: the clock module
Including multiple clock sources, respectively multi-core DSP circuit module provides 1 road 66.67MHZ clock signal, 3 road 100MHZ clocks letter
Number, 2 road 312.5MHZ clock signals；1 road 50MHZ clock source is provided for FPGA.
5. a kind of high speed big data quantity information processing system according to claim 1, it is characterised in that: the multicore
DSP module is successively filtered denoising, image segmentation, figure to data, state preprocessed data teledata, information processing board
Image intensifying processing, then carries out Registration of Measuring Data, by coordinate transform and unit conversion, the teledata received, at information
Data, state preprocessed data are transformed into unified expression-form between reason plate, carry out data fusion using Kalman filtering algorithm,
Obtain fused system standardization status information.
6. a kind of high speed big data quantity information processing system according to claim 1, it is characterised in that: external system and height
The rate that data double-way transmits between fast big data quantity information processing system is 12500M/min, in high speed big data quantity system
SpaceWire bus data transfer rate is 200Mbps.
7. a kind of high speed big data quantity information processing system according to claim 1, it is characterised in that: the multicore
DSP module is provided with the kilomega network port for supporting 10/100/1000Mbps data transmission bauds, realizes the high speed with remote terminal
Data transmission.
8. a kind of high speed big data quantity information processing system according to claim 1, it is characterised in that: the multicore
DSP circuit block memory capacity: SDRAM--4Gbit；Bandwidth > 200MB/s；Solid-state memory is had using NAND FLASH
512Mb capacity, E2PROM:1M.
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