CN205787883U - A kind of built-in IO of microcontroller SOC maps test device - Google Patents

Abstract

The utility model discloses a kind of built-in IO of microcontroller SOC and map test device, including external testing logic module, microcontroller core, ip module IP1, ip module IP2, close beta control module and I/O control module.The beneficial effects of the utility model are: 1, the integrated IP within microcontroller SOC can be tested by this programme efficiently.Losing efficacy occurs in microcontroller SOC when, it is also possible in test mode the IP being internally integrated is carried out failure analysis.2, this programme can improve the testing efficiency of microcontroller SOC, it is only necessary to increases few resource to realize built-in IO and maps test logic, with little need for the manufacturing cost increasing microcontroller SOC.

Description

A kind of built-in IO of microcontroller SOC maps test device

Technical field

This utility model relates to a kind of host computer system, and specifically a kind of built-in IO of microcontroller SOC maps test device.

Background technology

In microcontroller SOC, often in addition to microcontroller core (mcu core), also include some IP kernels.IP The ip module of the chip design that core refers to be provided by one party (intellectual property core, referred to as IP).Inside microcontroller SOC, microcontroller core (mcu core) is connected by metal wire with some function IP kernels.? In integrated circuit (Integrated Circuit is called for short IC) industry, IC testing cost accounts for the most important of IC total production cost A part, the ratio shared in circuit and system total cost of testing expense constantly rises.In IC produces design, how to drop The testing cost of low IC becomes an important topic now.

Utility model content

The purpose of this utility model is to provide a kind of built-in IO of microcontroller SOC to map test device, above-mentioned to solve The problem proposed in background technology.

For achieving the above object, the following technical scheme of this utility model offer:

A kind of built-in IO of microcontroller SOC maps test device, including external testing logic module, microcontroller core, Ip module IP1, ip module IP2, close beta control module and I/O control module, described external testing logic Module includes serial communication interface and external testing control module, and I/O control module connects external testing control module respectively, knows Knowing property blocks IP1, ip module IP2, microcontroller core and close beta control module, described close beta controls Module is also connected with serial communication interface.

As preferred version of the present utility model: described close beta control module include test vector serial number register and Close beta control module.

Compared with prior art, the beneficial effects of the utility model are: 1, this programme can be efficiently to microcontroller SOC Internal integrated IP tests.Losing efficacy occurs in microcontroller SOC when, it is also possible in test mode to being internally integrated IP carry out failure analysis.2, this programme can improve the testing efficiency of microcontroller SOC, it is only necessary to increases few resource Realize built-in IO and map test logic, with little need for the manufacturing cost increasing microcontroller SOC.

Accompanying drawing explanation

Fig. 1 is overall structure block diagram of the present utility model；

Fig. 2 is the schematic diagram of I/O control module.

Detailed description of the invention

Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole Embodiment.Based on the embodiment in this utility model, those of ordinary skill in the art are not under making creative work premise The every other embodiment obtained, broadly falls into the scope of this utility model protection.

Referring to Fig. 1-2, a kind of built-in IO of microcontroller SOC maps test device, including external testing logic module, micro- Controller kernel, ip module IP1, ip module IP2, close beta control module and I/O control module, described External testing logic module includes serial communication interface and external testing control module, and I/O control module connects external testing respectively Control module, ip module IP1, ip module IP2, microcontroller core and close beta control module, described Close beta control module is also connected with serial communication interface.

Close beta control module includes test vector serial number register and close beta control module.

Operation principle of the present utility model is: provided herein is a kind of IO for microcontroller SOC map testing scheme with Device.This scheme is for the test of microcontroller SOC.When testing microcontroller SOC, the test outside microcontroller SOC is patrolled Collecting and passed through with chip internal testing control module by serial communication interface, request chip enters test pattern.Microcontroller After device SOC enters test pattern, under the IO within microcontroller SOC maps the effect of test logic, IP to be tested is drawn Foot maps to the external pin of microcontroller SOC.Test logic outside microcontroller SOC by test and excitation by microcontroller The external pin input of SOC, it is possible to drive the integrated IP within microcontroller SOC in test mode.Meanwhile, microcontroller The integrated IP within SOC response under test and excitation can also be monitored by microcontroller SOC external pin.This programme can Efficiently the integrated IP within microcontroller SOC is tested.Losing efficacy occurs in microcontroller SOC when, it is also possible to In test mode the IP being internally integrated is carried out failure analysis.This programme can improve the testing efficiency of microcontroller SOC, only Need to increase few resource and map test logic to realize built-in IO, with little need for increasing being manufactured into of microcontroller SOC This.

The utility model proposes a kind of towards low-power consumption Managed Solution in the MCU chip of keying class application, at MCU chip In resting state, after being waken up up by the key scan logic working in low frequency, it is possible to respond ensuing sleep request at once, and It is not required to etc. the key scan clock cycle of at least 2 low frequencies.MCU kernel is thereby made to reenter not in time Dormancy state, thus enable the chip to be suitable for the application scenario stricter to power consumption requirements.

External testing logic:

External testing logic can be controlled with the close beta in microcontroller core by internal serial communication interface Module communicates.Some test instructions can be transmitted to microcontroller SOC by serial communication interface.External testing Logic is also responsible for some the corresponding test and excitations produced for driving the IP within microcontroller SOC, and surveying IP Response under examination incentive action is monitored, to judge whether microcontroller SOC exists inefficacy.

Microcontroller core (mcu_core):

Microcontroller core is the core cell of whole microcontroller SOC.

IP1/IP2

The ip module (IP kernel) of the chip design provided by one party.It is usually microcontroller core (mcu_ Core) function peripheral unit.

Close beta control module (test_ctrl):

Close beta control module is being the unit inside microcontroller soc being controlled whole test logic.Internal Testing control module is responsible for controlling logic with external testing and is communicated.It is laggard that close beta controls to receive external testing instruction Enter test pattern, and the test volume sequence number receiving outside transmission is sent to close beta control module (test_ctrl), preserves In the test vector serial number register of internal testing control module (test_ctrl).Close beta control module is to test Vector sequence number decodes, and obtains each IO and maps direction control signal (dir_p1, dir_p2, dir_p3 ...), and by this A little IO map direction control signal and are input into I/O control module (gpio_ctrl).

I/O control module (gpio_ctrl):

The input that gpio_ctrl module is responsible for the gpio function of microcontroller SOC and microcontroller SOC peripheral hardware is defeated Go out the multiplexing on chip pin.When test pattern, the test I/O mapping logic work of gpio_ctrl inside modules, it is responsible for Pin to be tested (P1`, P2`, P3` ...) by IP1 Yu IP2 maps to the chip pin of microcontroller SOC accordingly (P1, P2, P3 ...) above.

The principle of this programme is as shown in Figure 1.Microcontroller core, IP1 and IP2 two is included inside microcontroller SOC The same situation that can be applicable to comprise more IP inside microcontroller SOC of function IP(this programme).External testing logic is passed through Serial communication interface communicates with the testing control module (test_ctrl) within microcontroller SOC.Request micro controller SOC Enter test pattern.When, after microcontroller SOC internal entrance test pattern, close beta control module exports control signal The state of test_mode is high effectively.After microcontroller SOC internal entrance test pattern, external testing controls logic and continues logical Cross serial communication interface and test vector sequence number is sent to close beta control module (test_ctrl), be stored in the survey of inside In the test vector serial number register of examination control module (test_ctrl).Translate according to test vector sequence number at test_ctrl Code, obtains each IO and maps direction control signal (dir_p1, dir_p2, dir_p3 ...), and these IO map direction control Signal processed is input into I/O control module (gpio_ctrl).When microcontroller SOC normal mode of operation, gpio_ctrl module is born The gpio function of duty management microcontroller SOC and the input and output of microcontroller SOC peripheral hardware multiplexing on chip pin.? In this programme, gpio_ctrl module in addition to the functions discussed above, also addition of test I/O mapping logic.Test I/O mapping logic Opening and closing controlled by test pattern control signal (test_mode).By test I/O mapping logic by IP1 and IP2 Pin to be tested (P1`, P2`, P3` ...) map to chip pin (P1, P2, the P3 of microcontroller SOC accordingly ...) above.Mapping relations are mapped direction control signal by IO and are controlled.

The design principle of I/O control module (gpio_ctrl) is as shown in Figure 2.As close beta control module (test_ Ctrl) when input to control signal test_mode of I/O control module (gpio_ctrl) is high effective status, microcontroller SOC Being in normal mode of operation, mux1 selector selects p1_oen to select as the control signal of output buffering buf1, mux2 selector Selecting the p1_o input signal as output buffer buf1, gate controlled switch g1 disconnects.Now, pin P1 exports as universal input (gpio) function uses.Control when close beta control module (test_ctrl) input to I/O control module (gpio_ctrl) When signal test_mode processed is low level state, mux1 selector selects IO to map direction control signal (dir_p1) as defeated Go out the control signal of buffer buf1.The direction that corresponding IO maps is mapped direction control signal by IO and is controlled.As IO maps When direction control signal (dir_p1) is low level, gate controlled switch g1 turns on, and gate controlled switch g2 closes, and P1 is as input port, P1` As delivery outlet, external testing excitation can be inputted by P1 mouth, is directly driven IP by P1`.As IO maps direction control signal (dir_p1) when being high level, gate controlled switch g2 turn on, gate controlled switch g1 close, P1 as delivery outlet, P1` as input port, External testing logic can monitor the response of internal IP by P1 mouth.Other corresponding IO maps control planning, as above-mentioned identical. By this control mechanism, the test logic outside microcontroller SOC is defeated by the external pin of microcontroller SOC by test and excitation Enter, it is possible to drive the integrated IP within microcontroller SOC in test mode.Meanwhile, the integrated IP within microcontroller SOC Response under test and excitation can also be monitored by microcontroller SOC external pin, and external testing logic is rung by difference The correctness answered just can interpolate that microcontroller SOC is outside and whether internal IP lost efficacy.

Claims (2)

1. the built-in IO of microcontroller SOC maps a test device, including external testing logic module, microcontroller core, knows Know property blocks IP1, ip module IP2, close beta control module and I/O control module, it is characterised in that outside described Portion's test logic module includes serial communication interface and external testing control module, and I/O control module connects external testing control respectively Molding block, ip module IP1, ip module IP2, microcontroller core and close beta control module, described interior Portion's testing control module is also connected with serial communication interface.

A kind of built-in IO of microcontroller SOC the most according to claim 1 maps test device, it is characterised in that in described Portion's testing control module includes test vector serial number register and close beta control module.