CN111717059B

CN111717059B - DC charging pile controller and control method thereof

Info

Publication number: CN111717059B
Application number: CN202010643873.XA
Authority: CN
Inventors: 包文泉
Original assignee: Hangzhou Cangxin Power Technology Co ltd
Current assignee: Hangzhou Cangxin Power Technology Co ltd
Priority date: 2020-07-07
Filing date: 2020-07-07
Publication date: 2024-06-25
Anticipated expiration: 2040-07-07
Also published as: CN111717059A

Abstract

The invention discloses a direct current charging pile controller and a control method thereof, wherein the controller comprises a main control chip, an FPGA chip, an internal digital logic module, an Ethernet interface, a charging gun A control circuit, a charging gun B control circuit, a charging gun C control circuit, a charging gun D control circuit, a touch display screen communication interface circuit, an IC card communication interface circuit and a power supply circuit; the control method of the controller comprises the following step S1: initializing; step S2: entering a main control program; step S3: executing the interrupt subroutine, and returning to the step S2 after the execution is completed; the controller fully plays the advantages of FPGA logic control and multiple interfaces, reduces the use of peripheral interfaces of the singlechip, further lightens the processing load of the singlechip program, realizes four-gun parallel charging, and improves the integration level of the controller.

Description

DC charging pile controller and control method thereof

Technical Field

The invention relates to the technical field of direct current charging piles, in particular to a direct current charging pile controller and a control method thereof.

Background

The direct current charging technology adopts a high-voltage and high-current charging mode; in order to ensure the safety of charging operation, relevant control flow and guarantee measures are specified in the existing national standard; such as connection detection, charging gun electronic locks, insulation monitoring measures, residual voltage relief, charging control and the like; in actual research and development design, the main controller not only needs to realize the related control requirements specified in national standards, but also needs to realize functions such as ammeter control communication, charging module control communication, ethernet communication, fan control, auxiliary power supply output control and the like in order to meet the requirements of actual application; most of the existing direct current charging pile main control boards adopt embedded processors (single chip microcomputer) as main, because the control peripherals have higher requirements on the performance of the processors and interface resources, a plurality of processors are needed to cooperate in a mode of realizing multi-gun parallel charging for a common 32-bit single chip microcomputer, so that a control circuit is complex and the integration level is low; in addition, the processing logic in the main control program of the processor is relatively complex, and unknown errors may be caused, so that the main controller is halted in the charging process.

Disclosure of Invention

Aiming at the problems in the prior art, the direct current charging pile controller and the control method thereof provided by the invention are composed of the FPGA, the singlechip and the peripheral circuit, so that the advantages of the FPGA logic control and multiple interfaces are fully exerted, the use of the singlechip peripheral interfaces is reduced, the processing load of the singlechip program is further reduced, the four-gun parallel charging is realized, the integration level of the controller is improved, and the problems that the existing controller is complex in circuit, low in integration level and easy to cause dead halt due to complex processing logic are solved.

In order to achieve the purpose of the invention, the invention adopts the following technical scheme:

The direct current charging pile controller comprises a main control chip, an FPGA chip, an Ethernet interface, a charging gun A control circuit, a charging gun B control circuit, a charging gun C control circuit, a charging gun D control circuit, a touch display screen communication interface circuit, an IC card communication interface circuit and a power supply circuit; the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit, the charging gun D control circuit, the touch display screen communication interface circuit and the IC card communication interface circuit are respectively and electrically connected with the FPGA chip; the FPGA chip is electrically connected with the main control chip through interrupt 0, interrupt 1, interrupt 2 and interrupt 3 signal lines and a communication bus; the Ethernet interface is electrically connected with the main control chip; the power supply circuit supplies power to each chip and each circuit;

Further, the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit and the charging gun D control circuit comprise an output control circuit, an ammeter communication interface circuit, an insulation monitoring module communication circuit, a charging module communication interface circuit, a charging communication interface circuit and a CC1 detection circuit; the output control circuit is provided with nine groups of control channels, a first group of control operation indicator lamps, a second group of control fault indicator lamps, a third group of control cooling fans, a fourth group of control auxiliary power supply switching and output, a sixth group of control charging gun output, a seventh group of control discharge loop switching, and an eighth group of control charging gun electronic locks and unlocks; .

The I/O port of the FPGA chip is electrically connected with the EXTI, EXTI, EXTI and EXTI interrupt signal input port and the FSMC interface of the main control chip through interrupt 0, interrupt 1, interrupt 2, interrupt 3 signal lines and a communication bus; the Ethernet interface comprises an Ethernet PHY chip and an Ethernet connector; the RMII interface of the main control chip is electrically connected with the Ethernet PHY chip, and the Ethernet PHY chip is electrically connected with the Ethernet connector; the power supply circuit comprises an AC-DC module, a DC-DC isolation module A, a voltage conversion chip A and a voltage conversion chip B, DC-DC isolation module B; the AC-DC module is connected with AC220V, and the output end of the AC-DC module is connected with the input end of the DC-DC isolation module A, DC-DC isolation module B; the output end of the DC-DC isolation module A is connected with the input ends of the voltage conversion chip A and the voltage conversion chip B; the output end of the DC-DC isolation module A, the output end of the voltage conversion chip B and the output end of the DC-DC isolation module B are grounded together;

the output control circuit comprises a relay, a driving chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, the other end of the isolation chip is connected with one end of the driving chip, the other end of the driving chip is connected with a coil end of the relay, and nine groups of relay output control channels are formed in the connection mode;

The ammeter communication interface circuit, the touch display screen communication interface circuit and the IC card communication interface circuit comprise an RS232 interface chip and an isolation chip, an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS232 interface chip;

The insulation monitoring module communication circuit comprises an RS485 interface chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS485 interface chip;

The charging module communication interface circuit and the charging communication interface circuit both comprise a CAN interface chip and an isolation chip, the I/O port of the FPGA core is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the CAN interface chip;

The CC1 detection circuit comprises a V/F conversion chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the V/F conversion chip;

Further, the digital logic in the FPGA chip comprises a charging gun A signal processing module, a charging gun B signal processing module, a charging gun C signal processing module, a charging gun D signal processing module, an IC card signal processing module and a touch screen signal processing module; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module, the charging gun D signal processing module, the IC card signal processing module and the touch screen signal processing module are connected with an address signal wire, a data signal wire, a writing control signal wire, a reading control signal wire and a CLK clock signal wire; the address signal line, the data signal line, the write control signal line, the read control signal line and the CLK clock signal line form a communication bus and are connected with an FSMC interface of the main control chip; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module and the charging gun D signal processing module respectively output an interrupt 0 signal, an interrupt 1 signal, an interrupt 2 signal and an interrupt 3 signal which are connected with the interrupt signal input ends of EXTI, EXTI1, EXTI2 and EXTI of the main control chip;

The internal digital logic of the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module and the charging gun D signal processing module comprises a frequency counter module, a CAN bus interface A module, a CAN bus interface B module, a UART interface A module, a UART interface B module and an output control module; the frequency counter module acquires an output signal of the CC1 detection circuit, and a transmission FIFO module is arranged in the frequency counter module; the CAN bus interface A module is in circuit connection communication with the communication interface of the charging module, and a transmission FIFO module and a reception FIFO module are arranged in the CAN bus interface A module; the CAN bus interface B module is communicated with the charging communication interface circuit, and a transmission FIFO module and a reception FIFO module are arranged in the CAN bus interface B module; the UART interface A module is in circuit connection communication with the ammeter communication interface, and a transmission FIFO module and a reception FIFO module are arranged in the UART interface A module; the UART interface B module is communicated with the insulation monitoring module communication circuit, and a transmission FIFO module and a reception FIFO module are arranged in the UART interface B module; the output control module is in control connection with the output control circuit, and a state register is arranged in the output control module;

The touch screen signal processing module is a UART interface C module with a transmission FIFO module and a reception FIFO module, and the UART interface C module is in circuit connection communication with the touch display screen communication interface; the IC card signal processing module is a UART interface D module with a transmission FIFO module and a reception FIFO module, and the UART interface D module is in circuit connection communication with the IC card interface;

the address signal line and the read control signal line are connected with a read data enabling end of a sending FIFO module of the frequency counter module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module and the IC card signal processing module after logical AND operation;

The address signal line and the write control signal line are connected with a write data enabling end of a receiving FIFO module of the touch screen signal processing module and the IC card signal processing module and a write data enabling end of a status register of the output control module after performing logic AND operation;

The data signal line is connected with the data output end of the sending FIFO module of the frequency counter module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the IC card signal processing module and the data input end of the status register of the control module;

the CLK clock signal line is connected with the data reading clock end of the sending FIFO module of the frequency counter module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the IC card signal processing module and the data writing clock end of the state register of the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the receiving FIFO module of the IC card signal processing module and the data writing clock end of the state register of the control module;

further, the full-read flag bit output of the transmission FIFO module of the frequency counter module forms an interrupt signal.

A control method using the direct current charging pile controller comprises the following steps,

Step S1: initializing EXTI0, EXTI1, EXTI, EXTI3 interrupt and ethernet interfaces and FSMC interfaces;

step S2: entering a main control program, and circularly executing a touch screen control step S21, an IC card control step S22, a charging control step S23 and an Ethernet communication step S24;

step S3: when EXTI0, EXTI1, EXTI2 and EXTI3 interrupt signals trigger, executing the interrupt 0/1/2/3 subroutine, and returning to the step S2 after the execution is completed;

In the step S3, when an interrupt signal triggers, the main control chip executes an FSMC read instruction on the frequency counter module of the corresponding charging gun signal processing module through the FSMC interface, acquires CC1 status data, and returns to the step S2; when the CC1 voltage state is 4V, starting to execute the steps of locking the electronic lock of the charging gun and outputting the auxiliary power supply in the step S23 of controlling the charging, after the step of outputting the auxiliary power supply is completed, sending a handshake message to the charging automobile, after the handshake message is sent, successfully receiving a return message from the charging automobile, starting to execute the steps of insulation monitoring and voltage discharging, after the step of voltage discharging is completed, sending a message confirmation to the charging automobile, confirming the return message of the charging automobile, after the confirmation is completed, executing the step of closing the charging, and starting to output electric energy to the charging automobile; when in charging, according to message data of a charging automobile, the main control chip is communicated with the charging module to execute a current regulation step and read ammeter data in real time; when the charging automobile returns to the return message to finish charging, sequentially executing the steps of stopping power failure, releasing voltage, cutting off auxiliary power supply output and unlocking the electronic lock; the touch screen control step S21 comprises the steps of executing the operation instruction data input by a reading operator to the touch screen and writing the charge state information data into the touch screen; inputting operation instruction data comprises starting charging and ending charging; the charge state information includes a charge preparation, charging, and charge end state; the IC card control step S22 comprises the steps of reading and writing operation, fee deduction and balance judgment of the IC card information; the ethernet communication step S24 includes sending ammeter data and charging status information, and receiving charging start-stop instruction data from the internet.

Preferably, when the touch screen control step S21, the IC card control step S22, and the charging control step S23 are executed, the main control chip and the external communication are all completed by performing a read/write operation on the FSMC interface.

Preferably, in the charging control step S23, a charging state variable is set, and the charging state variable is changed in real time according to a message of a charging car, IC card information, an internet charging start-stop instruction, and an input operation of a touch screen; the charging control step S23 executes a closed power-on and power-off stopping step according to the charging state variable; the Ethernet communication step S24 updates the sent charging state information in real time according to the charging state variable; the touch screen control step S21 updates the written charge state information data in real time according to the charge state variables.

Compared with the prior art, the invention has the following beneficial effects:

The invention provides a new solution scheme for the direct current charging pile, which consists of an FPGA, a singlechip and a peripheral circuit, wherein each group of charging gun signal processing modules arranged in the FPGA controls one charging gun to charge, different module data are read and written through address signals matched with read control signals and write control signals, the control and communication of corresponding peripherals are completed, the four charging guns of the integrated direct current charging pile are combined for charging operation, the advantages of FPGA logic control resources and multiple interfaces are fully exerted, the use of the interfaces of the singlechip peripherals is reduced, the processing load of the singlechip is further reduced, and the integration level of the controller and the operation efficiency of a main control program are improved.

Drawings

FIG. 1 is a block diagram of a DC charging pile controller according to the present invention;

FIG. 2 is a block diagram of the charging gun A/B/C/D control circuit of the DC charging pile controller;

FIG. 3 is a circuit connection diagram of a main control chip, an FPGA chip and an Ethernet interface of the DC charging pile controller;

FIG. 4 is a diagram showing the connection of a power supply circuit of a DC charging pile controller according to the present invention;

FIG. 5 is a circuit diagram of the charging gun A/B/C/D control circuit of the DC charging pile controller according to the present invention;

FIG. 6 is a circuit diagram of the touch screen and IC card interface circuit of a DC charging stake controller according to the present invention;

FIG. 7 is a diagram showing the connection structure of digital logic modules in an FPGA chip of the DC charging pile controller;

FIG. 8 is a digital logic connection block diagram of the charging gun A/B/C/D signal processing module of FIG. 7;

FIG. 9 is a diagram of the digital logic connection of the IC card signal processing module and the touch screen signal processing module of FIG. 7;

FIG. 10 is a general execution of steps of a control method of a DC charging pile controller according to the present invention;

Fig. 11 is a control flow block diagram of steps S2, S3 in fig. 10;

Detailed Description

The drawings in the embodiments of the present invention will be combined; the technical scheme in the embodiment of the invention is clearly and completely described:

As shown in fig. 1, in one embodiment of the present invention, a dc charging pile controller includes a main control chip 1, an FPGA chip 2, an ethernet interface 3, a charging gun a control circuit 4, a charging gun B control circuit 5, a charging gun C control circuit 6, a charging gun D control circuit 7, a touch display communication interface circuit 8, an IC card communication interface circuit 9, and a power supply circuit 10; the charging gun A control circuit 4, the charging gun B control circuit 5, the charging gun C control circuit 6, the charging gun D control circuit 7, the touch display screen communication interface circuit 8 and the IC card communication interface circuit 9 are respectively and electrically connected with the FPGA chip 2; the FPGA chip 2 is electrically connected with the main control chip 1 through interrupt 0, interrupt 1, interrupt 2 and interrupt 3 signal lines and a communication bus; the Ethernet interface 3 is electrically connected with the main control chip 1; the power supply circuit 10 supplies power to each chip and each circuit;

As shown in fig. 2, the charging gun a control circuit 4, the charging gun B control circuit 5, the charging gun C control circuit 6 and the charging gun D control circuit 7 comprise an output control circuit 401, an ammeter communication interface circuit 402, an insulation monitoring module communication circuit 403, a charging module communication interface circuit 404, a charging communication interface circuit 405 and a CC1 detection circuit 406; the output control circuit 401 is provided with nine groups of control channels, a first group of control operation indicator lamps, a second group of control fault indicator lamps, a third group of control cooling fans, a fourth group of control auxiliary power supply switching and output, a sixth group of control charging gun output, a seventh group of control discharge loop switching, and an eighth group of control charging gun electronic locks and unlocks; .

As shown in fig. 3-6, in the specific circuit connection diagrams of the present invention, the connection of related chips, power signals and data transmission signals mainly shown in the diagrams is omitted for the auxiliary circuits around the chips, and specific reference may be made to the disclosed chip manual; in a specific embodiment of the present invention, the I/O port of the FPGA chip 2 is electrically connected to the FSMC interface of the main control chip 1 and the EXTI, EXTI1, EXTI2, EXTI interrupt signal input ports, and bus communication is implemented by using the FSMC interface; the ethernet interface 3 includes an ethernet PHY chip 31 and an ethernet connector 32; the RMII interface of the main control chip 1 is electrically connected with the Ethernet PHY chip 31, and the Ethernet PHY chip 31 is electrically connected with the Ethernet connector 32; the power supply circuit 10 comprises an AC-DC module 101, a DC-DC isolation module A102, a voltage conversion chip A103, a voltage conversion chip B104 and a DC-DC isolation module B105; the AC-DC module 101 is connected to AC220V, and the output end of the AC-DC module is connected with the input ends of the DC-DC isolation module A102 and the DC-DC isolation module B105; the output end of the DC-DC isolation module A102 is connected with the input ends of the voltage conversion chip A103 and the voltage conversion chip B104; the output end of the DC-DC isolation module A102, the output end of the voltage conversion chip A103, the output end of the voltage conversion chip B104 and the output end of the DC-DC isolation module B105 are grounded together;

The output control circuit 401 includes a relay (ADL 105), a driving chip (ULN 2803), and an isolation chip (AduM N), where an I/O port of the FPGA chip 2 is connected to one end of the isolation chip, the other end of the isolation chip is connected to one end of the driving chip, and the other end of the driving chip is connected to a coil end of the relay, and nine groups of relay output control channels are formed by the above connection manner, and note that only one group of channels of the circuit connection is shown in fig. 5;

the ammeter communication interface circuit 402, the touch display screen communication interface circuit 8 and the IC card communication interface circuit 9 comprise an RS232 interface chip (MAX 232) and an isolation chip (AduM 1201), an I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS232 interface chip;

the insulation monitoring module communication circuit 403 comprises an RS485 interface chip (MAX 485) and an isolation chip (AduM 1201), wherein an I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS485 interface chip;

The charging module communication interface circuit 404 and the charging communication interface circuit 405 both comprise a CAN interface chip (TJA 1050) and an isolation chip (AduM 1201), the I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the CAN interface chip; the charging communication interface circuit realizes the communication between the controller and the charging automobile, and the charging module communication interface circuit controller realizes the communication with the charging module;

The CC1 detection circuit 406 comprises a V/F conversion chip (AD 654 JR) and an isolation chip (Adu 1100,1100), wherein an I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the V/F conversion chip;

As shown in fig. 7, the digital logic in the FPGA chip 2 includes a charging gun a signal processing module 201, a charging gun B signal processing module 202, a charging gun C signal processing module 203, a charging gun D signal processing module 204, an IC card signal processing module 205, and a touch screen signal processing module 206; the charging gun A signal processing module 201, the charging gun B signal processing module 202, the charging gun C signal processing module 203, the charging gun D signal processing module 204, the IC card signal processing module 205 and the touch screen signal processing module 206 are connected with an address signal wire, a data signal wire, a writing control signal wire, a reading control signal wire and a CLK clock signal wire; the address signal line, the data signal line, the write control signal line, the read control signal line and the CLK clock signal line form a communication bus 207 and are connected with the FSMC interface of the main control chip 1; the charging gun A signal processing module 201, the charging gun B signal processing module 202, the charging gun C signal processing module 203 and the charging gun D signal processing module 204 respectively output an interrupt 0 signal, an interrupt 1 signal, an interrupt 2 signal and an interrupt 3 signal which are connected with the interrupt signal input ends EXTI, EXTI1, EXTI and EXTI of the main control chip 1; each group of charging gun signal processing modules controls one charging gun to charge, when the charging guns are connected, the corresponding charging gun signal processing modules output interrupt signals, and the main control chip 1 receives the interrupt signals to make corresponding charging operation;

As shown in fig. 8, the internal digital logic of the charging gun a signal processing module 201, the charging gun B signal processing module 202, the charging gun C signal processing module 203, and the charging gun D signal processing module 204 includes a frequency counter module 2010, a CAN bus interface a module 2011, a CAN bus interface B module 2012, a UART interface a module 2013, a UART interface B module 2014, and an output control module 2015; the frequency counter module 2010 collects the output signal of the CC1 detection circuit 406, and a transmission FIFO module (a first-in first-out data buffer, which is the same as the prior art, is provided with a write data enabling end, a write data clock end, a data input end, a full write flag, a null write flag, a read data enabling end, a read data clock end, a full read flag, a null read flag, etc.) is arranged in the frequency counter module 2010; the CAN bus interface A module 2011 is communicated with the charging module communication interface circuit 404 in a connection way, and a transmission FIFO module and a reception FIFO module are arranged in the CAN bus interface A module 2011; the CAN bus interface B module 2012 is in communication connection with the charging communication interface circuit 405, and a transmission FIFO module and a reception FIFO module are arranged in the CAN bus interface B module 2012; the UART interface A module 2013 is connected with the ammeter communication interface circuit 402 for communication, and a transmission FIFO module and a reception FIFO module are arranged in the UART interface A module 2013; the UART interface B module 2014 is in communication connection with the insulation monitoring module communication circuit 403, and a transmission FIFO module and a reception FIFO module are arranged in the UART interface B module 2014; the output control module 2015 is in control connection with the output control circuit 401, the output control module 2015 is provided with a status register, and the logic expression of the output control module 2015 is changed by writing the internal data of the status register, so that the output level of the output control circuit 401 is changed;

As shown in fig. 9, the touch screen signal processing module 205 is a UART interface C module with a transmit FIFO module and a receive FIFO module, and the UART interface C module is in communication with the touch screen communication interface circuit 8; the IC card signal processing module 206 is a UART interface D module with a transmission FIFO module and a reception FIFO module, and the UART interface D module is connected and communicated with the IC card communication interface circuit 9;

The address signal line and the read control signal line are logically and operated and then are respectively connected with the frequency counter module 2010, the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205 and the read data enabling end of the transmission FIFO module of the IC card signal processing module 206, and it should be noted that the address signal line is a multi-bit address bus signal, and a one-bit address corresponds to the read data enabling end of the transmission FIFO module;

The address signal line and the write control signal line are logically and operated and then respectively connected with a write data enabling end of a receiving FIFO module of the UART interface B module 2014, the UART interface a module 2013, the touch screen signal processing module 205, the IC card signal processing module 206 and a write data enabling end of a status register of the output control module 2015;

The data signal line is connected with the frequency counter module 2010, the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205, the data output end of the transmitting FIFO module of the IC card signal processing module 206, and the data input end of the status register of the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205, the data input end of the receiving FIFO module of the IC card signal processing module 206, and the control module 2015;

The CLK clock signal line is connected to the frequency counter module 2010, the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205, the read data clock end of the transmitting FIFO module of the IC card signal processing module 206, and the write data clock end of the status register of the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205, the write data clock end of the receiving FIFO module of the IC card signal processing module 206, and the control module 2015;

The read full flag output of the transmit FIFO of the frequency counter module 2010 forms an interrupt signal, i.e., interrupt 0 signal, interrupt 1 signal, interrupt 2 signal, interrupt 3 signal (one interrupt signal is output by the frequency counter module of each charging gun signal processing module).

When the charging gun is connected, the frequency counter module 2010 counts the output signal of the CC1 detection circuit 406, and when the transmission FIFO module is fully written, an interrupt signal is triggered to be transmitted to the main control chip 1.

When the controller reads data from the external interface, the bus interface 207 reads the control signal effectively, and simultaneously outputs the corresponding address signal bit to select the corresponding transmission FIFO module to read the internal data to the data signal line, and the internal data is received by the main control chip 1; when the controller writes data to the external interface, the bus interface 207 writes control signals effectively, and outputs corresponding address signal bits to select corresponding receiving FIFO modules or status registers, store the data on the data signal lines, and send the data out by the external interface.

As shown in fig. 10, a control method of a direct current charging pile controller includes,

As shown in fig. 11, specifically, when an interrupt signal triggers, the main control chip 1 executes an FSMC read instruction on the frequency counter module 2010 of the corresponding charging gun signal processing module through the FSMC interface, acquires CC1 status data, and returns to step S2; when the CC1 voltage state is 4V, starting to execute the steps of locking the electronic lock of the charging gun and outputting the auxiliary power supply in the step S23 of controlling the charging, after the step of outputting the auxiliary power supply is completed, sending a handshake message to the charging automobile, after the handshake message is sent, successfully receiving a return message from the charging automobile, starting to execute the steps of insulation monitoring and voltage discharging, after the step of voltage discharging, sending a message confirmation to the charging automobile, confirming the return message of the charging automobile, after the confirmation is completed, executing the step of closing the charging automobile, starting to output electric energy to the charging automobile, and when the charging is completed, executing the step of current regulation according to the message data of the charging automobile by the main control chip 1 and the charging module in a communication way, and reading the electric meter data in real time; when the charging automobile returns to the return message to finish charging, sequentially executing the steps of stopping power failure, releasing voltage, cutting off auxiliary power supply output and unlocking the electronic lock;

specifically, when the touch screen control step S21, the IC card control step S22, and the charging control step S23 are executed, the main control chip 1 and the external communication are completed by performing read/write operation on the FSMC interface, so that the main control chip 1 is prevented from directly going to operate and control the corresponding peripheral, the peripheral configuration program is reduced, and the operation efficiency of the main control program is improved.

Specifically, the step S21 of controlling the touch screen includes executing the operation instruction data input to the touch screen by the reading operator and writing the charge state information data into the touch screen; inputting operation instruction data comprises starting charging and ending charging; the charge state information includes a charge preparation, charging, and charge end state;

Specifically, the IC card control step S22 includes reading and writing operations, fee deduction, and balance judgment of IC card information;

Specifically, the ethernet communication step S24 includes sending ammeter data and charging status information, and receiving charging start-stop instruction data from the internet.

Specifically, in the charging control step S23, a charging state variable is set, and the charging state variable is changed in real time according to a message of a charging car, IC card information, an internet charging start-stop instruction, and an input operation of a touch screen; the charging control step S23 executes a closed power-on and power-off stopping step according to the charging state variable; the Ethernet communication step S24 updates the sent charging state information in real time according to the charging state variable; the touch screen control step S21 updates the written charge state information data in real time according to the charge state variables. The charging state variables at least comprise charging start-stop flag bits, current charging voltage, current data information, IC card balance information, auxiliary source state and charging fault information.

The charging control step S23 is specifically executed, and FSMC read instructions and FSMC write instructions are operated for different address intervals according to different interrupt signals, so that charging control of different charging guns is realized; in specific implementation, a total of 26 bits of [25:0] address of the FSMC interface may be connected to the address signal line of the bus interface 207, where the address interval of [5:0] is allocated to the charging gun a signal processing module 201 and corresponds to the 6 modules included therein, the same address interval of [11:6] is allocated to the charging gun B signal processing module 202, the address interval of [17:12] is allocated to the charging gun C signal processing module 203, and the address interval of [23:18] is allocated to the charging gun D signal processing module 205; when the touch screen control step S21 and the IC card control step S22 are executed, the rest [25:24] is respectively distributed to the touch screen signal processing module 205 and the IC card signal processing module 206; the address signals are matched with the read control signals and the write control signals to realize the read and write of different module data, and the control and the communication of the corresponding peripheral equipment are completed.

Claims

1. A DC charging stake controller, its characterized in that: the intelligent charging device comprises a main control chip, an FPGA chip, an Ethernet interface, a charging gun A control circuit, a charging gun B control circuit, a charging gun C control circuit, a charging gun D control circuit, a touch display screen communication interface circuit, an IC card communication interface circuit and a power supply circuit; the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit, the charging gun D control circuit, the touch display screen communication interface circuit and the IC card communication interface circuit are respectively and electrically connected with the FPGA chip; the FPGA chip is electrically connected with the main control chip through interrupt 0, interrupt 1, interrupt 2 and interrupt 3 signal lines and a communication bus; the Ethernet interface is electrically connected with the main control chip; the power supply circuit supplies power to each chip and each circuit; the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit and the charging gun D control circuit comprise an output control circuit, an ammeter communication interface circuit, an insulation monitoring module communication circuit, a charging module communication interface circuit, a charging communication interface circuit and a CC1 detection circuit; the output control circuit is provided with nine groups of control channels, a first group of control operation indicator lamps, a second group of control fault indicator lamps, a third group of control cooling fans, a fourth group of control auxiliary power supply switching and output, a sixth group of control charging gun output, a seventh group of control discharge loop switching, and an eighth group of control charging gun electronic locks and unlocks;

The CC1 detection circuit comprises a V/F conversion chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the V/F conversion chip; the FPGA chip is internally provided with digital logic and comprises a charging gun A signal processing module, a charging gun B signal processing module, a charging gun C signal processing module, a charging gun D signal processing module, an IC card signal processing module and a touch screen signal processing module; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module, the charging gun D signal processing module, the IC card signal processing module and the touch screen signal processing module are connected with an address signal wire, a data signal wire, a writing control signal wire, a reading control signal wire and a CLK clock signal wire; the address signal line, the data signal line, the write control signal line, the read control signal line and the CLK clock signal line form a communication bus and are connected with an FSMC interface of the main control chip; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module and the charging gun D signal processing module respectively output an interrupt 0 signal, an interrupt 1 signal, an interrupt 2 signal and an interrupt 3 signal which are connected with the interrupt signal input ends of EXTI, EXTI1, EXTI2 and EXTI of the main control chip;

The CLK clock signal line is connected with the data reading clock end of the sending FIFO module of the frequency counter module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the IC card signal processing module, the data writing clock end of the state register of the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the data writing clock end of the receiving FIFO module of the IC card signal processing module and the data writing clock end of the state register of the control module.

2. A dc charging stake controller as claimed in claim 1, wherein: and the full reading zone bit output of the transmission FIFO module of the frequency counter module forms an interrupt signal.

3. The control method of the direct current charging pile controller according to claim 1, wherein: the method comprises the following steps of,

step S3: when EXTI, EXTI1, EXTI, EXTI3 interrupt signals trigger, the interrupt 0/1/2/3 subroutine is executed, and after execution is completed, the process returns to step S2.

4. A control method of a dc charging pile controller according to claim 3, characterized by: in the step S3, when an interrupt signal triggers, the main control chip executes an FSMC read instruction on the frequency counter module of the corresponding charging gun signal processing module through the FSMC interface, acquires CC1 status data, and returns to the step S2; when the CC1 voltage state is 4V, starting to execute the steps of locking the electronic lock of the charging gun and outputting the auxiliary power supply in the step S23 of controlling the charging, after the step of outputting the auxiliary power supply is completed, sending a handshake message to the charging automobile, after the handshake message is sent, successfully receiving a return message from the charging automobile, starting to execute the steps of insulation monitoring and voltage discharging, after the step of voltage discharging is completed, sending a message confirmation to the charging automobile, confirming the return message of the charging automobile, after the confirmation is completed, executing the step of closing the charging, and starting to output electric energy to the charging automobile; when in charging, according to message data of a charging automobile, the main control chip is communicated with the charging module to execute a current regulation step and read ammeter data in real time; when the charging automobile returns to the return message to finish charging, sequentially executing the steps of stopping power failure, releasing voltage, cutting off auxiliary power supply output and unlocking the electronic lock; the touch screen control step S21 comprises the steps of executing the operation instruction data input by a reading operator to the touch screen and writing the charge state information data into the touch screen; inputting operation instruction data comprises starting charging and ending charging; the charge state information includes a charge preparation, charging, and charge end state; the IC card control step S22 comprises the steps of reading and writing operation, fee deduction and balance judgment of the IC card information; the ethernet communication step S24 includes sending ammeter data and charging status information, and receiving charging start-stop instruction data from the internet.

5. The control method of the direct current charging pile controller according to claim 4, wherein: when the touch screen control step S21, the IC card control step S22 and the charging control step S23 are executed, the communication between the main control chip and the outside is completed by performing read/write operation on the FSMC interface.

6. The control method of the direct current charging pile controller according to claim 4, wherein: the charging control step S23 is provided with a charging state variable, wherein the charging state variable is changed in real time according to a message of a charging automobile, IC card information, an Internet charging start-stop instruction and input operation of a touch screen; the charging control step S23 executes a closed power-on and power-off stopping step according to the charging state variable; the Ethernet communication step S24 updates the sent charging state information in real time according to the charging state variable; the touch screen control step S21 updates the written charge state information data in real time according to the charge state variables.