CN205752162U - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN205752162U
CN205752162U CN201620597055.XU CN201620597055U CN205752162U CN 205752162 U CN205752162 U CN 205752162U CN 201620597055 U CN201620597055 U CN 201620597055U CN 205752162 U CN205752162 U CN 205752162U
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fet
gan
semiconductor packages
pedestal
ldmos
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P·T·勒
A·尤恩戈
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本实用新型提供一种半导体封装，其包括具有源极连接器的导电基座(基座)。漏极连接器和栅极连接器与所述基座电耦接。耗尽型氮化镓场效应晶体管(GaN FET)和增强型横向扩散金属氧化物半导体场效应晶体管(LDMOS FET)也与所述基座耦接。所述栅极连接器和所述LDMOS FET的栅极触点均包括在第一电节点中，所述源极连接器和所述LDMOS FET的源极触点均包括在第二电节点中，并且所述漏极连接器和所述GaN FET的漏极触点均包括在第三电节点中。所述GaN FET和LDMOS FET一起形成作为增强型放大器工作的共源共栅结构。所述半导体封装不包括位于所述GaN FET与所述基座之间或位于所述LDMOS FET与所述基座之间的***器。

Description

半导体封装
技术领域
本实用新型的各方面整体涉及半导体共源共栅装置。
背景技术
共源共栅结构(cascode)是具有放大器和电流缓冲器的两级放大器。用半导体材料形成的常规共源共栅结构常常包括两个晶体管，诸如双极性结型晶体管(BJT)和/或场效应晶体管(FET)。一个晶体管通常作为共源极或共发射极来工作，另一个晶体管通常作为共栅极或共基极来工作。
实用新型内容
半导体封装的实施可包括：具有源极连接器的导电基座(基座：base)；与基座电耦接的漏极连接器；与基座电耦接的栅极连接器；与基座耦接的氮化镓场效应晶体管(GaNFET)；以及与基座耦接并且与GaN FET电耦接的横向扩散金属氧化物半导体场效应晶体管(LDMOS FET)，该GaN FET和该LDMOS FET一起形成共源共栅结构。
半导体封装的实施可包括以下各项中的一项、全部或任何一项：
栅极连接器和LDMOS FET的栅极触点均可包括在第一电节点中，源极连接器和LDMOS FET的源极触点均可包括在第二电节点中，并且漏极连接器和GaN FET的漏极触点均可包括在第三电节点中。
GaN FET可为平面GaN FET，其在GaN FET的第一侧面上具有源极触点、栅极触点和漏极触点。
半导体封装可不具有位于GaN FET与基座之间的***器。
半导体封装可不具有位于LDMOS FET与基座之间的***器。
GaN FET可包括耗尽型GaN FET。
LDMOS FET可包括增强型LDMOS FET。
GaN FET可包括高电子迁移率晶体管(HEMT)。
共源共栅结构可作为增强型放大器工作。
半导体封装的实施可包括：共源共栅结构，其包括：与横向扩散金属氧化物半导体场效应晶体管(LDMOS FET)电耦接的氮化镓场效应晶体管(GaN FET)；其中LDMOS FET的源极和GaN FET的栅极均与半导体封装的源极电耦接；其中LDMOS FET的栅极与半导体封装的栅极电耦接；并且其中GaN FET的漏极与半导体封装的漏极电耦接。
半导体封装的实施可包括以下各项中的一项、全部或任何一项：
密封剂包封GaN FET和LDMOS FET，并且通过密封剂暴露半导体封装的栅极、源极和漏极。
半导体封装可不包括耦接在GaN FET与半导体封装的基座之间的***器。
半导体封装可不包括耦接在LDMOS FET与半导体封装的基座之间的***器。
GaN FET可包括耗尽型GaN FET。
LDMOS FET可包括增强型LDMOS FET。
GaN FET可包括高电子迁移率晶体管(HEMT)。
共源共栅结构可作为增强型放大器工作。
LDMOS FET可包括含有LDMOS FET的源极的第一侧面以及含有LDMOS FET的栅极与LDMOS FET的漏极的第二侧面。
GaN FET可包括与半导体封装的基座耦接的第一侧面以及包含GaN FET的栅极、GaN FET的漏极和GaN FET的源极的第二侧面。
半导体封装的实施可包括：耗尽型氮化镓高电子迁移率晶体管(GaN HEMT)，其具有与导电基座(基座)物理耦接的第一侧面和包括源极触点、漏极触点和栅极触点的第二侧面，该栅极触点通过电耦接器与基座电耦接；横向扩散金属氧化物半导体场效应晶体管(LDMOS FET)，其具有包括源极触点与基座物理耦接和电耦接的的第一侧面以及包括栅极触点和漏极触点的第二侧面；其中GaN HEMT和LDMOS FET电耦接在一起以形成增强型共源共栅结构；其中基座包括源极连接器，并且其中半导体封装还包括栅极连接器和漏极连接器，该栅极连接器与LDMOS FET的栅极触点电耦接并且该漏极连接器与GaN HEMT的漏极触点电耦接；其中密封剂包封GaN HEMT和LDMOS FET，并且至少部分地包封源极连接器、栅极连接器和漏极连接器；以及其中通过密封剂中的开口暴露的栅极连接器的栅极触点、源极连接器的源极触点和漏极连接器的漏极触点。
对于本领域的普通技术人员而言，通过具体实施方式和附图以及通过权利要求，上述以及其他方面、特征和优点将显而易见。
附图说明
将在下文中结合附图描述各实施方式，其中类似的标号表示类似的元件，并且：
图1是使用具有引线的封装来封装共源共栅结构的实施的顶部部分穿透视图；
图2是沿平面A-A截取的图1的封装的剖视图；
图3是使用没有引线的封装来封装共源共栅结构的实施的顶部部分穿透视图；
图4是沿平面B-B截取的图3的封装的剖视图；以及
图5是示出图1的共源共栅结构的若干元件的电路图。
具体实施方式
本公开、其各方面以及实施不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的符合预期共源共栅结构半导体封装及相关方法的许多额外部件、组装工序和/或方法元素将显而易见地与本公开的特定实施一起使用。因此，例如，尽管本发明公开了特定实施，但此类实施和实施部件可包括符合预期操作和方法的针对此类共源共栅结构半导体封装的本领域已知的任何形状、尺寸、样式、类型、型号、版本、量度、浓度、材料、数量、方法元素、步骤等和相关方法，以及实施部件和方法。
如本文所用，“电节点”和“节点”各自被定义为电路中不存在电位变化的区域。
如本文所用，“***器”被定义为用于将两个导电元件彼此电绝缘隔离的电绝缘体。
现在参见图1，在实施中，半导体封装(封装)2包括共源共栅结构16，其作为增强型放大器18来工作。封装2包括栅极20、源极22和漏极24。导电基座(基座)26包括源极连接器28，其是源极引线30并且包括源极触点32。在所示的实施中，基座26是金属基板34，并且可以看到，当封装完全形成时，基座延伸穿过封装的前部(源极连接器28位于该处)，并且延伸穿过封装的背部(其中具有开口38的延伸器位于该处)。在各种实施中，开口和/或延伸器可用于将电压源耦接到封装。因此，封装包括从封装的侧边延伸出的四条引线36：三条引线位于封装的前部，该封装前部包括源极连接器、栅极连接器44和漏极连接器50，封装还包括从背部延伸出的引线36。从背部延伸出的引线和源极连接器均与基板34形成整体。栅极连接器44和漏极连接器50未与基板34形成整体，并且不是直接耦接到基板，而是通过电耦接器和其他元件与基板间接电耦接，如本文所公开，另外还通过相同元件以及通过密封剂40与基板间接物理耦接。
因此，封装2包括栅极连接器44，其包括栅极引线46，该栅极引线46延伸穿过密封剂中的开口42并且具有栅极触点48。封装2还包括漏极连接器50，其包括漏极引线52，该漏极引线52延伸穿过密封剂中的另一个开口42并且具有漏极触点54。另外，如先前所描述，封装2包括源极连接器28，其包括源极引线30，该源极引线30延伸穿过密封剂中的另一个开口42并且具有源极触点32。封装2背部与基座和源极连接器形成整体的延伸器本身是延伸穿过密封剂中另一个开口42的引线36，并且由于该延伸器与基座直接电耦接，所以其还可充当封装2的源极。在实施中，位于背部的延伸器还可在需要时充当接地，其中电耦接器在需要时通过开口38将基座耦接到接地。图2是沿平面A-A截取的图1的封装2的横截面，其示出在实施中，基座实际上暴露在封装2的底部6上。在其他实施中，基板可包封在封装的底部处，但在实施中，使基座暴露有利于增加从封装提取热量。如图所示，封装2的顶部4可包封基座以及本文所描述的封装2的其他部件。
仍参见图1至2，在各种实施中，氮化镓场效应晶体管(GaN FET)56耦接到基座26。在实施中，GaN FET是平面GaN FET 58，其具有直接耦接到基座的第一侧面66和包括GaNFET的栅极70、源极74和漏极82的第二侧面68(在所示的实施中与第一侧面66相对)。在各种实施中，GaN FET是高电子迁移率晶体管(HEMT)60。另外，在各种实施中，GaN FET是耗尽型GaN FET 62。在图1所示的实施中，GaN FET同时是HEMT和耗尽型GaN FET，并且因此是耗尽型氮化镓高电子迁移率晶体管(GaN HEMT)64。
GaN FET可使用在硅(Si)衬底或碳化硅(SiC)衬底上生长的氮化镓半导体来形成。作为非限制性示例，这可使用各种常规方法来进行，包括金属有机化学气相沉积(MOCVD)、分子束外延(MBE)等等。
多种技术可用于形成不同区域、互连等等以形成场效应晶体管。在各种实施中，GaN FET的形成不使用掺杂，而是形成一个或多个电子沟道，其中在具有不同带隙的材料之间具有异质结。在使用掺杂的其他实施中，可利用各种掺杂技术，诸如作为非限制性示例：气相外延；生长作为梨晶添加的掺杂剂；扩散；离子注入等等，并且这些技术中的任一项技术还可使用光刻技术来限定所需的掺杂区域。互连件、钝化层、散热片等(诸如金属垫、金属线、电触点、绝缘层等)可使用各种常规沉积技术来形成，诸如作为非限制性示例：镀敷、电镀、无电镀、化学溶液沉积(CSD)、化学浴沉积(CBD)、旋涂、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、金属有机气相外延(MOVPE)、等离子体增强型CVD(PECVD)、原子层沉积(ALD)、物理气相沉积(PVD)、热蒸发、电子束蒸发、分子束外延(MBE)、溅射、脉冲激光沉积、离子束沉积、阴极电弧沉积(电弧PVD)、电流体动力沉积(电喷雾沉积)和任何其他沉积方法。这些沉积技术可包括光刻技术和/或可包括诸如通过物理和/或化学蚀刻技术的材料移除。
可根据需要通过此类蚀刻技术对层进行薄化，并且还可根据需要通过材料移除技术形成通孔等等。可在GaN FET中包括氮化铝间隔物，并且这些间隔物可增大电子迁移率，但可针对屏障使用其他材料，诸如作为非限制性示例：氮化铝铟(InAlN)、栅极金属绝缘体(诸如氮化物、通过原子层沉积(ALD)而沉积的氧化铝等等)等。在各种实施中，GaN FET的一个或多个电子沟道可由氮化镓形成，但在其他实施中，该电子沟道可包括铟以形成氮化镓铟(InGaN)电子沟道。GaN FET的一个或多个缓冲区可由GaN形成和/或可包括低氮化镓铝(AlGaN)。还可在GaN FET的各种区域的制作中使用退火循环。
一旦制成GaN FET，在适用时将其从GaN FET阵列分离，便可将其与基座耦接，诸如作为非限制性示例，通过使用粘合剂和/或借助于使用取放工具将其粘附到基座上。在各种实施中，GaN FET可在其下侧具有电触点，该电触点可与基座电耦接。在其他实施中，GaNFET在其下侧可没有电触点。在各种实施中，当GaN FET在其下侧没有电触点时，则不需要使用导电粘合剂(或例如，焊料)，但可根据需要使用导电粘合剂或焊料。还可使用高热导率粘合剂，而无论其是否导电。如可从图1和图2看到，没有***器位于GaN FET与基座之间，因为在这个实施中，这些元件之间不需要电绝缘。在GaN FET与基座之间不包括***器可产生减小的封装尺寸、较少的处理步骤和/或改进的传热性能。
参见图1并且如本文所描述，GaN FET 56包括源极74、漏极82和栅极70。GaN FET为耗尽型FET，使得当不存在栅极偏压时，电流从漏极流动到源极，并且当施加栅极偏压时，电流不从漏极流动到源极。在一些实施中，所施加的栅极偏压是负栅极偏压，或者说在操作期间，将栅极带到比源极低的电位。源极包括具有源极触点80的衬垫76和从源极触点朝漏极延伸并且与源极电连通的多条源极线78。漏极82包括具有漏极触点88的衬垫84和从漏极触点朝源极延伸并且与漏极电连通的多条漏极线86。源极线和漏极线设置成交替图案，如图1中可见，以形成线格阵列。漏极线和源极线的这种交替图案可用于平面GaN FET。由于源极电流和漏极电流均在管芯的同一侧上，因此以这种交替图案放置线可有助于获得较低电阻(这可减少热量)、可有助于将热量在GaN FET的整个顶侧上分散开，和/或可增加源极与漏极之间的结处的表面区域或体积以实现较高电子迁移率/吞吐量。
GaN FET的漏极82通过电耦接器122与封装2的漏极24电耦接。电耦接器122可为焊线、夹子、以焊接或使用诸如导电粘合剂等其他方式附接的薄金属元件等等。GaN FET的栅极70具有栅极触点72，在所示的实施中，其为金属垫，并且栅极触点72使用电耦接器120与基座26电耦接，在所示的实施中，该电耦接器120类似于电耦接器122。
仍参见图1和图2，封装2包括横向扩散金属氧化物半导体场效应晶体管(LDMOSFET)90。LDMOS FET具有第一侧面94，其包括具有源极触点98的源极96，该源极触点98是衬垫100。LDMOS FET的第二侧面(在所示的实施中，位于与LDMOS FET的第一侧面相对侧面上)包括具有栅极触点106的栅极104，该栅极触点106是衬垫108，以及具有漏极触点112的漏极110，该漏极触点112是衬垫114。LDMOS FET 90是增强型LDMOS FET 92，使得在存在零栅极偏压时一般处于“断开”模式，其中电流不从漏极流动到源极，并且当存在栅极偏压电流时，电流可因此从漏极流动到源极。
电耦接器116将封装2的栅极20与LDMOS FET的栅极104电耦接。另一个电耦接器118将LDMOS FET的漏极110与GaN FET 56的源极74电耦接。电耦接器116和118可类似于先前描述的其他电耦接器120和122，并且可类似地附接。
LDMOS FET 90可使用上文相对于GaN FET制造所描述的任何制造技术来形成。在实施中，LDMOS FET可使用硅衬底和各种离子注入和退火循环来制造，以针对各种区域实现恰当的掺杂分布。上文相对于GaN FET描述的用于添加金属层或触点或者限定金属层或触点的任何方法还可用于LDMOS FET。一旦制成LDMOS FET和/或将其从LDMOS FET阵列分离，便可将其放置在基座上(作为非限制性示例，诸如使用取放工具)，并且可使用本文所描述的任何方法将其附接到基座上。然而，就LDMOS FET而言，由于源极96在LDMOS FET的面向基座的侧面(或者说是第一侧面(底侧)94)上，因此将使用导电材料(诸如导电粘合剂、导电焊料等)将衬垫100附接或耦接到基座。在其他实施中，LDMOS FET可形成为使得源极96在第二侧面(顶侧)102上，并且电耦接器(类似于本文所描述的其他电耦接器)可用于将LDMOS FET的源极96与基座26电耦接。如从图1和图2可见，在LDMOS FET与基座之间也不存在***器。由于没有理由要将LDMOS FET与基座电绝缘，因此不需要***器-而是第一侧面(底侧)94与基座直接耦接-并且这可减小装置尺寸，减少处理步骤和/或改进热性能。
在将GaN FET和LDMOS FET放置在基座上并且将电耦接器116、118、120、122耦接在恰当地方之后，密封剂40可用于包封半导体装置的各种元件。在包封之前，装置的各种部分(包括基座26、栅极连接器44和漏极连接器50)可实际上耦接在一起或由单片材料(诸如引线框)形成，并且在包封之后，可使用分离工艺将封装与引线框的部分分开并且同时将引线框的部分彼此割断，或者说将这些元件直接耦接在一起的那些部分割断。封装2在包封工艺完成并且已经执行所有分离步骤后完全形成，从而形成图1至2所示的结构。在实施中，可使用单个引线框形成多个封装2。在此类实施中，取放和包封工艺可用于形成未分离封装阵列，并且可接着使用分离工艺以形成多个分离封装2。
可从图1和图2看到，与封装2及其各种元件形成多个电节点(节点)。第一电节点(节点)8包括封装2的栅极20、LDMOS FET 90的栅极104和电耦接器116。第二电节点(节点)10包括封装2的源极22(以及相应地整个基座26)、LDMOS FET 90的源极96、GAN FET 56的栅极70和将GAN FET 56耦接到基座26的电耦接器120。第三电节点(节点)12包括封装2的漏极24、GaN FET 56的漏极82和电耦接器122。第四电节点(节点)14包括LDMOS FET 90的漏极110、GaN FET 56的源极74和电耦接器118。
在操作中，当在LDMOS FET的栅极104处没有栅极偏压时(即，当在封装2的栅极20处没有栅极偏压时)，LDMOS FET处于“断开”模式，使得电流无法从LDMOS FET的漏极流动到源极。因此，没有流向GaN FET的源极的电流，并且因此，没有流向GaN FET漏极的电流以及相应地流向封装漏极24的电流。因此，在这种状态下，封装2处于“断开”状态。
当在封装2的栅极20处存在栅极偏压时，在LDMOS FET的栅极104处存在栅极偏压。LDMOS FET因此处于“接通”状态。在这种状态下，电流进入封装2的漏极24并且流动到GaN漏极衬垫，接着穿过GaN装置到达GaN FET源极74。电流接着从GaN FET源极74穿过电耦接器118流动到LDMOS FET漏极110，接着到达LDMOS FET的源极96，并且到达封装2的源极22。因此，虽然GaN FET是耗尽型FET，但在所示的配置中，通过将其与LDMOS FET耦接，形成作为增强型放大器工作的共源共栅结构。虽然附图中未具体描绘，但本领域的普通技术人员将理解，可使用其他部件来形成放大器(包括电阻器和其他电部件)以实现所需增益。
图5示出描绘封装2中的GaN FET 56和LDMOS FET 90的各种元件的电路图178。这些元件中的一些元件在封装2的内部，并且诸如栅极20、源极22和漏极24之类的其他元件延伸到封装2的外部，如先前所描述。还描绘了节点8、10、12和14。
现在参见图3至4，在各种实施中，半导体封装(封装)124在结构上类似于封装2，不同之处在于其为无引线封装。例如，封装124的GaN FET 56和LDMOS FET 90与图1至2和图5所示的以及先前相对于封装2所描述的那些相同。因此，图5的电路图178同样适用于图3至4的封装124，并且先前相对于封装2描述的任何制造技术还可用于形成封装124。
封装124具有由密封剂162的表面形成的顶部126和由密封剂162形成的底部128，其中通过所述密封剂暴露导电基座(基座)152。封装124的第一侧面130包括密封剂的开口164，在该处暴露栅极连接器166的栅极触点168和漏极连接器170的漏极触点172。在封装124的第二侧面132、第三侧面134和第四侧面136里的密封剂162中也存在开口164，在该处暴露源极连接器154的源极触点156。封装124因此具有栅极146、源极148和漏极150。栅极146通过电耦接器174与LDMOS FET的栅极104耦接，从而形成第一电节点(节点)138。第二电节点(节点)140包括封装源极148、LDMOS FET源极96、GaN FET栅极70和电耦接器120，该电耦接器120将基座152与GaN FET栅极70耦接。GaN FET漏极82通过电耦接器176与漏极150耦接，从而形成第三电节点(节点)142。第四电节点(节点)144包括LDMOS FET的漏极、GaN FET的源极和将这两者耦接在一起的电耦接器118。因此，电路图178可用相同格式来绘制，用封装124的具有相同名称的元件的标号替换封装2的元件的标号，以产生封装124的电路图。
如图4中可见，在实施中，基座152由基板158形成，其中在基板158的第一侧面160中具有多个凹处。这些凹处可在诸如引线框中使用选择性蚀刻、光刻等等来形成，并且可进一步有助于减小封装尺寸。
因为本文所描述的封装不包括***器并且使用基座作为GaN FET和LDMOS FET的共源极，所以这些封装可减少组装步骤和组装复杂性；可增大装置的热性能；可允许装置以较高频率操作；可增强功率处理能力；可减小外在寄生电容、电感和电阻；全部前述内容；以及前述内容的任何组合。用作共源极的基座可为管芯标记或凸缘，和/或可为接地。在各种实施中，本文所描述的封装可被设计为以600V或左右进行工作。本文中的共源共栅结构不是使用垂直沟槽FET技术形成，因此制作和组装可更容易、更灵活和/或更经济。本文所描述的封装可用于功率管理应用、DC-DC应用、工业应用、汽车应用、无线应用、医学应用、蜂窝电话应用、***接收器应用、电压转换应用、雷达应用、微波和/或射频(RF)功率放大应用等等。
虽然本文中所描述的共源共栅结构被描述为用作放大器，但在实施中，其可被修改为用作调制器，诸如用于振幅调制。该共源共栅结构还可与电压梯组合以产生高压晶体管。
在各种半导体封装实施中，半导体封装还包括密封剂，该密封剂包封GaN FET和LDMOS FET，并且通过密封剂暴露半导体封装的栅极、源极和漏极。
在各种实施中，GaN FET是耗尽型GaN FET。
在各种实施中，LDMOS FET是增强型LDMOS FET。
在各种实施中，GaN FET是高电子迁移率晶体管(HEMT)。
在各种实施中，共源共栅结构作为增强型放大器工作。
在各种实施中，LDMOS FET包括含有LDMOS FET的源极的第一侧面以及含有LDMOSFET的栅极和LDMOS FET的漏极的第二侧面。
在各种实施中，GaN FET包括与半导体封装的基座耦接的第一侧面以及含有GaNFET的栅极、GaN FET的漏极和GaN FET的源极的第二侧面。
在以上描述提到共源共栅半导体封装和相关方法以及实施部件、子部件、方法和子方法的特定实施的地方，应当易于显而易见的是，可在不脱离其精神的情况下做出多种修改，并且这些实施、实施部件、子部件、方法和子方法可应用于其他共源共栅半导体封装和相关方法。

Claims (11)

1.一种半导体封装，其特征在于包括：
导电基座，所述基座包括源极连接器；
与所述基座电耦接的漏极连接器；
与所述基座电耦接的栅极连接器；
与所述基座耦接的氮化镓场效应晶体管GaN FET；以及
与所述基座耦接并且与所述GaN FET电耦接的横向扩散金属氧化物半导体场效应晶体管LDMOS FET，所述GaN FET和所述LDMOS FET一起形成共源共栅结构。
2.根据权利要求1所述的半导体封装，其特征在于所述栅极连接器和所述LDMOS FET的栅极触点均包括在第一电节点中，所述源极连接器和所述LDMOS FET的源极触点均包括在第二电节点中，并且所述漏极连接器和所述GaN FET的漏极触点均包括在第三电节点中。
3.根据权利要求1所述的半导体封装，其特征在于所述GaN FET是平面GaN FET，包括：位于所述GaN FET的第一侧面上的源极触点、栅极触点和漏极触点。
4.根据权利要求1所述的半导体封装，其特征在于所述半导体封装不包括位于所述GaNFET与所述基座之间的***器。
5.根据权利要求1所述的半导体封装，其特征在于所述半导体封装不包括位于所述LDMOS FET与所述基座之间的***器。
6.根据权利要求1所述的半导体封装，其特征在于所述GaN FET是耗尽型GaN FET，并且所述LDMOS FET是增强型LDMOS FET。
7.根据权利要求1所述的半导体封装，其特征在于所述GaN FET是高电子迁移率晶体管HEMT。
8.根据权利要求1所述的半导体封装，其特征在于所述共源共栅结构作为增强型放大器工作。
9.一种半导体封装，其特征在于包括：
共源共栅结构，其包括：
与横向扩散金属氧化物半导体场效应晶体管LDMOS FET电耦接的氮化镓场效应晶体管GaN FET；
其中所述LDMOS FET的源极和所述GaN FET的栅极均与所述半导体封装的源极电耦接；
其中所述LDMOS FET的栅极与所述半导体封装的栅极电耦接；并且
其中所述GaN FET的漏极与所述半导体封装的漏极电耦接。
10.根据权利要求9所述的半导体封装，其特征在于所述半导体封装不包括耦接在所述GaN FET与所述半导体封装的基座之间的***器，并且不包括耦接在所述LDMOS FET与所述半导体封装的基座之间的***器。
11.一种半导体封装，其特征在于包括：
耗尽型氮化镓高电子迁移率晶体管GaN HEMT，所述GaN HEMT包括与导电基座物理耦接的第一侧面和包括源极触点、漏极触点和栅极触点的第二侧面，所述栅极触点通过电耦接器与所述基座电耦接；
横向扩散金属氧化物半导体场效应晶体管LDMOS FET，所述LDMOS FET包括第一侧面和第二侧面，所述第一侧面包括与所述基座物理耦接和电耦接的源极触点，所述第二侧面包括栅极触点和漏极触点；
其中所述GaN HEMT和所述LDMOS FET电耦接在一起以形成增强型共源共栅结构；
其中所述基座包括源极连接器，并且其中所述半导体封装还包括栅极连接器和漏极连接器，所述栅极连接器与所述LDMOS FET的所述栅极触点电耦接，并且所述漏极连接器与所述GaN HEMT的所述漏极触点电耦接；
其中密封剂包封所述GaN HEMT和所述LDMOS FET，并且至少部分地包封所述源极连接器、所述栅极连接器和所述漏极连接器；并且
其中通过所述密封剂中的开口暴露所述栅极连接器的栅极触点、所述源极连接器的源极触点和所述漏极连接器的漏极触点。
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