CN205665611U

CN205665611U - Loading point supplies electric chip's power supply system

Info

Publication number: CN205665611U
Application number: CN201620411055.6U
Authority: CN
Inventors: 张更
Original assignee: OPHYLINK COMMUNICATION TECHNOLOGY Ltd
Current assignee: OPHYLINK COMMUNICATION TECHNOLOGY Ltd
Priority date: 2016-05-09
Filing date: 2016-05-09
Publication date: 2016-10-26
Anticipated expiration: 2026-05-09

Abstract

The utility model discloses a loading point supplies electric chip's power supply system, its characterized in that: including PCB circuit board and clock phase generator able to programme, install a n SOC chip on the PCB circuit board, every SOC chip disposes corresponding load respectively and supplies electric chip, and every load confession electric chip equallys divide and bie is connected with the power bus and the clock phase generator able to programme of PCB circuit board. The utility model discloses an add adjustable clock phase generator, make each loading point power adopt the synchro switch clock to work is in the phase place of difference, and many powers of at utmost reduction rail reduces the EMI radiation to the interference of middle power bus's production, has improved system power supply's stability.

Description

A kind of electric power system of POL power supply chip

Technical field

This utility model relates to the in-line power technical field of big power consuming device, specifically refers to a kind of POL power supply chip Electric power system.

Background technology

Along with the lifting of chip integration, the lifting that technique carries, the application of single-chip SOC is increasingly wider, and monolithic PCB collection The chip number become also gets more and more, and a piece of PCB needs provide multiple low-voltage, high-current supply rail.

Existing POL power supply technique, it is achieved method is independent POL DC/DC conversion, and multi-disc POL is for battery core Not having synchronization policy between sheet, this scheme realizes simple, and cost is relatively low, is essentially all the most in the market and uses this The mode of kind is powered.But utilize independent, scattered POL power supply technique, do not carry out same between each POL Step, so can cause producing bigger interference in middle centre line, causes EMI electromagnetic radiation, the most also gives electric supply system Bring instability and uncertainty.

Utility model content

The purpose of this utility model is that providing a kind of provides synchronization policy to POL power supply chip, reduces many power rails Interference to the generation of intermediate power bus, reduces EMI radiation, improves the electric power system of the stability of power-supply system.

This utility model is achieved through the following technical solutions: the electric power system of a kind of POL power supply chip, including PCB electricity Road plate and programmable clock phase generator, described PCB is provided with the SOC no less than two, each SOC core Sheet is each configured with corresponding load supplying chip, each load supplying chip respectively with the power bus of PCB with And programmable clock phase generator connects.

Load supplying chip, be usually used in pcb board card distributed, polyfunctional design in the middle of, it can be one very Small power supply IC, it is also possible to be the power module of micropower can be isolation or do not isolates.But common load Power supply chip application be mostly IC class be main, or be similar to the micropower modular power source of IC, be generally also and do not require isolation The most not seeking to stable pressure, the feature of load supplying chip is that voltage is typically the least, as 1.5V, 2V, 3.3V etc., loads the least, It is usually about 1W or below 1W.

The operation principle of the technical program is, the multiple SOC of integrated installation in PCB, and each SOC is passed through The load supplying chip of configuration is connected with the power bus in PCB, and the power bus in PCB is each SOC Chip provides electric power, and the power supply of corresponding SOC is controlled by load supplying chip.

Each load supplying chip is all connected at the programmable clock phase generator outside PCB with external, can Mbus phase generator provides control signal for all of load supplying chip, makes all of load supplying chip use system The homology clock of one, the program in programmable clock phase generator can be adjusted, when making able to programme by user according to demand Clock phase generator provides the clock phase relation fixed for each load supplying chip, so that each load supplying chip work The clock made is different, does not works in same a period of time.Such as, receive able to programme when one of them load supplying chip Clock phase generator provide clock signal, when arriving this clock position, this load supplying chip make corresponding SOC with Power bus is connected, and other load supplying chip then because not in the clock position of oneself, does not the most make corresponding SOC Connecting with power bus, i.e. within a clock cycle, only one of which SOC is connected with power bus, thus avoids When multiple load supplying chips operate simultaneously, power bus is produced interference, reduces EMI radiation, improve system power supply Stability.

For preferably realizing this utility model, further, described PCB is provided with 5 SOC.

For preferably realizing this utility model, further, described load supplying chip is linear voltage regulator.

For preferably realizing this utility model, further, described SOC is mainly by microprocessor, Analog IP core, number Word IP kernel and memorizer are constituted.

For preferably realizing this utility model, further, described PCB is single-sided circuit board.

For preferably realizing this utility model, further, the model of described programmable clock phase generator is VersaClock 6.The output that the programmable clock generator that model is VersaClock 6 can provide general is right, can be independent Be configured to LVDS, LVPECL, HCSL or double LVCMOS, and can each output on independent produce 1 MHz to 350 MHz's Any frequency, the most here as programmable clock phase generator is preferred.

This utility model compared with prior art, has the following advantages and beneficial effect:

This utility model is by setting up programmable clock phase generator, when making each POL power supply use synchro switch Clock, and be operated in different phase places, at utmost reduce the interference to the generation of intermediate power bus of many power rails, reduce EMI radiation, improves the stability of system power supply.

Accompanying drawing explanation

The detailed description with reference to the following drawings, non-limiting example made by reading, other spies of the present utility model Levy, purpose and advantage will be changed to substantially:

Fig. 1 is structural schematic block diagram of the present utility model.

Detailed description of the invention

Of the present utility model embodiment is described below in detail, and the example of described embodiment is shown in the drawings, the most ad initio Represent same or similar element to same or similar label eventually or there is the element of same or like function.Below by ginseng It is exemplary for examining the embodiment that accompanying drawing describes, and is only used for explaining this utility model, and it is not intended that to of the present utility model Limit.

In description of the present utility model, it is to be understood that term " " center ", " longitudinally ", " laterally ", " on ", D score, Orientation or the position relationship of the instruction such as "front", "rear", "left", "right", " vertically ", " level ", " top ", " end ", " interior ", " outward " are Based on orientation shown in the drawings or position relationship, it is for only for ease of description this utility model and simplifies description rather than instruction Hint indication device or element must have specific orientation, with specific azimuth configuration and operation, be not understood that For to restriction of the present utility model.

In description of the present utility model, it should be noted that unless otherwise clearly defined and limited, term " peace Dress ", should be interpreted broadly " being connected ", " connection ", for example, it may be fix connection, it is also possible to be to removably connect, or integratedly Connect；Can be to be mechanically connected, it is also possible to be electrical connection；Can also be to be joined directly together, it is also possible to be indirect by intermediary It is connected, can be the connection of two element internals.For the ordinary skill in the art, can be with in concrete condition understanding State term concrete meaning in this utility model.

Embodiment 1:

The primary structure of the present embodiment, as it is shown in figure 1, include PCB and programmable clock phase generator, described Being provided with n SOC in PCB, each SOC is each configured with corresponding load supplying chip, each load Power supply chip is connected with power bus and the programmable clock phase generator of PCB respectively.

Detailed description of the invention is, is configured programmable clock phase generator, makes the load of n SOC configuration Power supply chip all has the fixed phase relationship of corresponding clock, when the load supplying chip of one of them SOC receives, arrives During this clock phase that programmable clock phase generator provides, this load supplying chip makes corresponding SOC total with power supply Line is connected, and other load supplying chip then because not in the clock position of oneself, does not the most make corresponding SOC and power supply Bus is connected, and i.e. within a clock cycle, only one of which SOC is connected with power bus, thus avoids multiple negative When load power supply chip operates simultaneously, power bus is produced interference, reduces EMI radiation, improve the stability of system power supply.

Embodiment 2:

The present embodiment, on the basis of above-described embodiment, further defines the number installing SOC in PCB Amount, described PCB is provided with 5 SOC.Respectively SOC 1, SOC 2, SOC 3, SOC 4, SOC 5, in the specific implementation, is configured the phase relation of five clocks by programmable clock phase generator, each The load supplying chip of SOC maps the phase relation of a clock.When PCB circuit bus is energized, according to clock phase Relation, makes SOC complete work successively.Other parts of the present embodiment are same as the previously described embodiments, repeat no more.

Embodiment 3:

The present embodiment, on the basis of above-described embodiment, further defines load supplying chip, SOC, PBC Circuit board and the concrete structure of programmable clock phase generator and model, described load supplying chip is linear voltage regulator； Described SOC is mainly made up of microprocessor, Analog IP core, numeral IP kernel and memorizer；Described PCB is one side electricity Road plate；The model of described programmable clock phase generator is VersaClock 6.Other parts of the present embodiment and embodiment 1 Identical, repeat no more.

It is understood that according to the electric power system of one embodiment of this utility model, such as programmable clock phase place is produced Operation principle and the work process of the raw parts such as device and POL power supply are all prior aries, and for those skilled in the art institute Know, be the most no longer described in detail.

Embodiment the most of the present utility model, it will be understood by those skilled in the art that: Under without departing from principle of the present utility model and objectives, these embodiments can be carried out multiple change, revise, replace and modification, Scope of the present utility model is limited by claim and equivalent thereof.

Claims

1. the electric power system of a POL power supply chip, it is characterised in that: include that PCB and programmable clock phase place are produced Raw device, described PCB is provided with the SOC no less than two, and each SOC is each configured with loading accordingly Power supply chip, each load supplying chip respectively with power bus and the programmable clock phase generator of PCB Connect.

The electric power system of a kind of POL power supply chip the most according to claim 1, it is characterised in that: described PCB circuit 5 SOC are installed on plate.

The electric power system of a kind of POL power supply chip the most according to claim 1 and 2, it is characterised in that: described load Power supply chip is linear voltage regulator.

The electric power system of a kind of POL power supply chip the most according to claim 1 and 2, it is characterised in that: described SOC core Sheet is mainly made up of microprocessor, Analog IP core, numeral IP kernel and memorizer.

The electric power system of a kind of POL power supply chip the most according to claim 1 and 2, it is characterised in that: described PCB electricity Road plate is single-sided circuit board.

The electric power system of a kind of POL power supply chip the most according to claim 1 and 2, it is characterised in that: described compile The model of journey clock phase generator is VersaClock 6.