CN205561751U - Multilayer PCB board dielectric layer thickness detection device based on capacitance measurement - Google Patents
Multilayer PCB board dielectric layer thickness detection device based on capacitance measurement Download PDFInfo
- Publication number
- CN205561751U CN205561751U CN201620412786.2U CN201620412786U CN205561751U CN 205561751 U CN205561751 U CN 205561751U CN 201620412786 U CN201620412786 U CN 201620412786U CN 205561751 U CN205561751 U CN 205561751U
- Authority
- CN
- China
- Prior art keywords
- layer
- pcb board
- copper billet
- detection device
- layer pcb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Abstract
The utility model discloses a multilayer PCB board dielectric layer thickness detection device based on capacitance measurement, the device is including setting up the several copper billet that on each layer of multilayer PCB board each other does not switch on, the geomery is the same, and set up and be in several test pad on the multilayer PCB board first layer, several test pad respectively with the copper billet of each layer of multilayer PCB board is corresponding, each layer copper billet is connected with corresponding test pad through lead wire and/or metallization guide hole. The method uses the capacitance measurement appearance to measure the capacitance value between each layer copper billet to whether each layer of judgement PCB board dielectric layer thickness within a definite time that can be quick, simple, directly perceived and accurate through contrast design theory capacitance value meets the demands, has avoided the complexity and the destructiveness of section analysis.
Description
Technical field
This utility model relates to a kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement detection device.
Background technology
Development along with PCB industry enters the information age, and signal transmission frequencies is the highest, and speed is very fast, the strictest particularly with the requirement of impedance plate to the performance requirement of PCB.The factor of the impedance affecting PCB trace mainly has cabling of the width of copper cash, the thickness of copper cash, the dielectric constant of medium, the thickness of medium, the thickness of pad, the path of ground wire, cabling periphery etc., and must strictly control during between PCB layer, the thickness of dielectric layer is often PCB manufacturing process.Judge that between PCB layer, the method for thickness of dielectric layers is mainly by slice analysis at present, and measure thickness by metallurgical microscope.But the method will certainly hurt PCB unit and cause PCB unit to be scrapped, and even monoblock pcb board is scrapped.
Utility model content
For overcoming the deficiencies in the prior art, the purpose of this utility model is to provide a kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement to detect device, can quickly judge whether thickness of dielectric layers meets requirement, and PCB will not be caused damage.
This utility model the technical scheme is that for solving its technical problem
A kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement detection device, including be arranged on each layer of described multi-layer PCB board be not turned on mutually, several copper billets that geomery is identical, and it being arranged on the several testing weld pads on described multi-layer PCB board ground floor, the copper billet of described several testing weld pads layer each with described multi-layer PCB board respectively is corresponding；Each layer copper billet is connected with corresponding testing weld pad by lead-in wire and/or metallized vias.
Further, the copper billet of ground floor is connected with corresponding testing weld pad by lead-in wire；The copper billet of remaining number of plies connects each via the lead-in wire being arranged on same layer the metallized vias corresponding with the place number of plies, and described metallized vias connects the testing weld pad of the corresponding number of plies by being arranged on the lead-in wire of ground floor.
Further, described metallized vias runs through described multi-layer PCB board.
Further, described copper billet be shaped as rectangle.
Further, the size of described copper billet is 4mm × 25mm.
Further, a diameter of 0.6mm of described metallized vias.
The beneficial effects of the utility model are: according to the principle of parallel plate capacitor, capacitance measuring tester is used to measure the capacitance between each layer copper billet, and can judge whether the thickness of dielectric layers of each interlayer of pcb board meets requirement quickly, simply, intuitively and accurately by contrast design theory capacitance, it is to avoid the complexity of slice analysis and destructiveness.
Accompanying drawing explanation
Fig. 1 is the structural representation of detection device of the present utility model.
Fig. 2 is each layer copper billet and the circuit design diagram (as a example by four laminates) of detection device of the present utility model.
In figure, label represents respectively: 1-PCB plate；2-ground floor copper billet；3-second layer copper billet；4-third layer copper billet；The 4th layer of copper billet of 5-；6-ground floor testing weld pad；7-second layer testing weld pad；8-third layer testing weld pad；The 4th layer of testing weld pad of 9-；10-second layer metal guide hole；11-third layer metallized vias；The 4th layer of metallized vias of 12-.
Detailed description of the invention
Below in conjunction with accompanying drawing and example, the utility model is described in further detail.
With reference to Fig. 1, Fig. 2, a kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement of the present utility model detection device, including be arranged on the described each layer of multi-layer PCB board 1 be not turned on mutually, several copper billets (2,3,4,5) that geomery is identical, and the several testing weld pads (6,7,8,9) being arranged on described multi-layer PCB board 1 ground floor, described several testing weld pads (6,7,8,9) are corresponding with the copper billet (2,3,4,5) of the described each layer of multi-layer PCB board 1 respectively；Each layer copper billet (2,3,4,5) is connected with corresponding testing weld pad (6,7,8,9) by lead-in wire and/or metallized vias (10,11,12).
Pcb board 1 as shown in Figure 2 has four layers, and ground floor copper billet 2 is connected with corresponding ground floor testing weld pad 6 by lead-in wire；Second and third, four layers of copper billet (3,4,5) connect the metallized vias (10,11,12) corresponding with the place number of plies each via the lead-in wire being arranged on same layer is corresponding, metallized vias (10,11,12) is respectively by arranging the testing weld pad (7,8,9) of the lead-in wire corresponding number of plies of connection on the first layer.
In the present embodiment, described metallized vias (10,11,12) runs through described multi-layer PCB board 1.
In the present embodiment, described copper billet (2,3,4,5) be preferably shaped to rectangle.
In the present embodiment, described copper billet (2,3,4,5) is preferably dimensioned to be 4mm × 25mm, a diameter of 0.6mm of described metallized vias (10,11,12), on the premise of guaranteeing that interlayer copper billet (2,3,4,5) capacitance can be detected smoothly, reduce the area of copper billet (2,3,4,5) busy line layer as far as possible.
This utility model additionally provides the detection method of application said apparatus, described method includes: capacitance measuring tester connects two testing weld pads that the corresponding number of plies is adjacent, detect the capacitance between the copper billet of the adjacent number of plies, the actual capacitance value measured contrasts with engineering design value, if actual value is less with design load deviation, then explanation is normal, otherwise it is assumed that the medium thickness between this two-layer is abnormal；Thus the multiple thickness of dielectric layers in pcb board are detected.
Ground floor testing weld pad 6, second layer testing weld pad 7 is connected by capacitance measuring tester during as tested, measure the capacitance between ground floor copper billet 2 and second layer copper billet 3, the actual capacitance value measured contrasts with engineering design value, if actual value is less than design load deviation, then explanation is normal；If actual value is relatively bigger than design load, then the thickness of dielectric layers between explanation pcb board 1 ground floor copper billet 2 and second layer copper billet 3 exists abnormal.The like, the capacitance between the second layer and third layer, third layer and the 4th layer can be measured, thus the thickness of dielectric layers between judging every layer is the most normal.
The foregoing is only preferred implementation of the present utility model, as long as realizing within the technical scheme of this utility model purpose broadly falls into protection domain of the present utility model with essentially identical means.
Claims (6)
1. multi-layer PCB board thickness of dielectric layers based on a capacity measurement detection device, it is characterized in that: include being arranged on each layer of described multi-layer PCB board be not turned on mutually, several copper billets that geomery is identical, and it being arranged on the several testing weld pads on described multi-layer PCB board ground floor, the copper billet of described several testing weld pads layer each with described multi-layer PCB board respectively is corresponding；Each layer copper billet is connected with corresponding testing weld pad by lead-in wire and/or metallized vias.
A kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement the most according to claim 1 detection device, it is characterised in that: the copper billet of ground floor is connected with corresponding testing weld pad by lead-in wire；The copper billet of remaining number of plies connects each via the lead-in wire being arranged on same layer the metallized vias corresponding with the place number of plies, and described metallized vias connects the testing weld pad of the corresponding number of plies by being arranged on the lead-in wire of ground floor.
A kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement the most according to claim 2 detection device, it is characterised in that: described metallized vias runs through described multi-layer PCB board.
A kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement the most according to claim 1 detection device, it is characterised in that: described copper billet be shaped as rectangle.
A kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement the most according to claim 4 detection device, it is characterised in that: the size of described copper billet is 4mm × 25mm.
A kind of multi-layer PCB board thickness of dielectric layers based on capacity measurement the most according to claim 1 detection device, it is characterised in that: a diameter of 0.6mm of described metallized vias.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620412786.2U CN205561751U (en) | 2016-05-06 | 2016-05-06 | Multilayer PCB board dielectric layer thickness detection device based on capacitance measurement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620412786.2U CN205561751U (en) | 2016-05-06 | 2016-05-06 | Multilayer PCB board dielectric layer thickness detection device based on capacitance measurement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205561751U true CN205561751U (en) | 2016-09-07 |
Family
ID=56803690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620412786.2U Active CN205561751U (en) | 2016-05-06 | 2016-05-06 | Multilayer PCB board dielectric layer thickness detection device based on capacitance measurement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205561751U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105823406A (en) * | 2016-05-06 | 2016-08-03 | 鹤山市中富兴业电路有限公司 | Multi-layer PCB dielectric layer thickness detection apparatus and detection method based on capacitance measurement |
| CN110220449A (en) * | 2019-06-28 | 2019-09-10 | 广东品能实业股份有限公司 | A kind of wiring board and conductive layer thickness detection method, detection device |
| CN117471182A (en) * | 2023-12-21 | 2024-01-30 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | System, method and storage medium for testing dielectric property of circuit board |
-
2016
- 2016-05-06 CN CN201620412786.2U patent/CN205561751U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105823406A (en) * | 2016-05-06 | 2016-08-03 | 鹤山市中富兴业电路有限公司 | Multi-layer PCB dielectric layer thickness detection apparatus and detection method based on capacitance measurement |
| CN110220449A (en) * | 2019-06-28 | 2019-09-10 | 广东品能实业股份有限公司 | A kind of wiring board and conductive layer thickness detection method, detection device |
| CN117471182A (en) * | 2023-12-21 | 2024-01-30 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | System, method and storage medium for testing dielectric property of circuit board |
| CN117471182B (en) * | 2023-12-21 | 2024-04-02 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | System, method and storage medium for testing dielectric property of circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9263410B2 (en) | Chip detecting system and detecting method | |
| CN105823406A (en) | Multi-layer PCB dielectric layer thickness detection apparatus and detection method based on capacitance measurement | |
| CN205561751U (en) | Multilayer PCB board dielectric layer thickness detection device based on capacitance measurement | |
| CN104582331B (en) | The internal layer off normal detection method of multilayer circuit board | |
| JP5185342B2 (en) | Method for inspecting printed circuit boards with built-in passive elements | |
| US20140333329A1 (en) | Method and apparatus for measuring thickness of layer in printed circuit board | |
| CN203423847U (en) | Multilayer circuit board allowing registration detection | |
| CN106550556A (en) | Aligning degree of multi-layer circuit board detecting system and its detection method | |
| CN205898964U (en) | Conducting hole pick -up plate and semi -manufactured goods printed circuit board | |
| KR20070111330A (en) | Board examination device and board examination method | |
| CN108398112A (en) | Circuit board copper plating detecting system and detection method | |
| US20040130334A1 (en) | Timing markers used in the measurement and testing of a printed circuit board's controlled impedance | |
| Kwon et al. | Detection of solder joint degradation using RF impedance analysis | |
| CN104764395A (en) | Printed-circuit board cutting depth testing method and circuit board | |
| CN204514300U (en) | The equipment of automatic detection resist thickness | |
| CN106024739A (en) | Metallic pad device and test system and method using same | |
| JP6520127B2 (en) | Substrate inspection apparatus, substrate inspection method, and substrate inspection jig | |
| KR101474620B1 (en) | Substrate Inspection Apparatus and Substrate Inspection Method | |
| CN104297673A (en) | Circuit board fault detector | |
| US20080088318A1 (en) | Method to test transparent-to-test capacitors | |
| JP2014020815A (en) | Substrate inspection device and substrate inspection method | |
| US8704545B2 (en) | Determination of properties of an electrical device | |
| JP2011069777A (en) | Method and device for inspecting substrate | |
| CN115877173A (en) | Blind hole detection structure and blind hole detection method | |
| KR101462954B1 (en) | Fixture of auto test equipment for testing electronic circuit card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |