CN103515340B - 电源模块封装和用于制造电源模块封装的方法 - Google Patents

电源模块封装和用于制造电源模块封装的方法 Download PDF

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Publication number
CN103515340B
CN103515340B CN201210593909.3A CN201210593909A CN103515340B CN 103515340 B CN103515340 B CN 103515340B CN 201210593909 A CN201210593909 A CN 201210593909A CN 103515340 B CN103515340 B CN 103515340B
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substrate
fastening unit
external connection
insulant
circuit layer
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CN103515340A (zh
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俞度在
尹善禹
蔡埈锡
金洸洙
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

本发明在此公开了一种电源模块封装,该电源模块封装包括:外部连接端子;基板,在该基板中,沿厚度方向以预定深度埋设有紧固单元,该紧固单元允许外部连接端子的一个端部被入式紧固于所述紧固单元上;和安装在基板的一个表面上的半导体芯片。

Description

电源模块封装和用于制造电源模块封装的方法
相关申请的交叉引用
本申请要求2012年6月29日提交的标题为“电源模块封装和用于制造电源模块封装的方法(Power Module Package and Method for Manufacturingthe Same)”的韩国专利申请10-2012-0070667的优先权,该申请在此通过全部引用合并于本申请。
技术领域
本发明涉及电源模块封装和用于制造电源模块封装的方法。
背景技术
近年来,随着针对电源的电子工业的发展,电子产品日益变小并且密度越来越大。因此,除了减小电子元件尺寸的方法之外,在确定的空间内尽可能多地安装元件和导线的方法也是设计电源模块封装时的关键性问题。
同时,在美国专利5920119中公开了一种相关技术的电源模块封装结构。
发明内容
本发明致力于提供一种电源模块封装和用于制造电源模块封装的方法,以能够去除或便于用于将外部连接端子紧固单元连接至基板的封装过程,并且能够防止外部连接端子与基板之间产生焊接裂纹,由此实现高可靠性。
根据本发明的第一优选实施方式,提供一种电源模块封装,其包括:外部连接端子;基板,在该基板中,沿厚度方向以预定深度埋设有紧固单元,该紧固单元允许所述外部连接端子的一个端部***式紧固于所述紧固单元上;和半导体芯片,该半导体芯片安装在所述基板的一个表面上。
所述基板可包括:绝缘材料;电路层,该电路层形成在所述绝缘材料的一个表面上并且包括芯片安装盘和外部连接盘;和金属层,该金属层形成在所述绝缘材料的另一表面上,并且,所述紧固单元可以由导电性材料制成并且所述紧固单元的一部分可以接触所述外部连接盘。
所述基板可包括:绝缘材料;电路层,该电路层形成在所述绝缘材料的一个表面上并且包括芯片安装盘和外部连接盘;和金属层,该金属层形成在所述绝缘材料的另一表面上,并且,所述紧固单元可以由非导电性材料制成,并且所述电源模块封装还可包括将所述外部连接端子电连接至所述外部连接盘的引线框。
所述紧固单元还可包括槽,在所述紧固单元内形成的所述外部连接端子***到所述槽中,并且可以在所述槽和***于所述槽内的所述外部连接端子中分别形成有悬挂凹槽和与所述悬挂凹槽相对应的悬挂突起。
所述电源模块封装还可包括:壳体,该壳体形成在所述基板上,以覆盖所述基板的一个表面以及半导体芯片,并且使所述外部连接端子的另一端部暴露在外。
所述电源模块封装还可包括:密封构件,该密封构件形成在所述壳体内,以覆盖所述基板的所述一个表面和所述半导体芯片。
根据本发明的第二优选实施方式,提供一种用于制造电源模块封装的方法,该方法包括如下步骤:制备基板,在该基板中沿厚度方向以预定深度埋设紧固单元,该紧固单元具有形成于其中的用于***式紧固外部连接端子的槽;将半导体芯片安装在所述基板上;并且将所述外部连接端子的一个端部***式紧固在所述紧固单元的所述槽内。
在此情形中,制备基板并在该基板中沿厚度方向以预定深度埋设紧固单元的步骤可以包括:准备绝缘材料;在所述绝缘材料的一个表面上形成预定深度的沟;在所述绝缘材料的一个表面上布置电路层,该电路层上与所述沟相对应的部分被去除;在所述绝缘材料的另一表面上布置金属层;并且将所述紧固单元***到所述沟内,并且使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体。
所述方法还可包括:在使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体之后,通过使所述电路层形成图案而形成芯片安装盘和外部连接盘,其中,将所述半导体芯片安装在所述芯片安装盘上。
所述紧固单元可以由导电性材料制成,并且所述外部连接盘可以形成为接触所述紧固单元。
所述紧固单元可以由非导电性材料制成,并且所述方法还可包括:在形成所述芯片安装盘和所述外部连接盘之后,形成用于将所述外部连接端子电连接至所述外部连接盘的引线框。
可以通过加热和共烧来进行使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体的步骤。
可以通过利用激光钻来进行形成所述沟的步骤。
制备基板并在该基板中沿厚度方向以预定深度埋设紧固单元的步骤可包括:准备绝缘材料;在所述绝缘材料的一个表面上形成预定深度的沟;在所述绝缘材料的一个表面上,布置电路层,该电路层上与所述沟相对应的部分被去除;在所述绝缘材料的另一表面上布置金属层;并且使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体。
所述方法还可包括:在使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体之后,通过使所述电路层形成图案而形成芯片安装盘和外部连接盘,其中,将所述半导体芯片安装在所述芯片安装盘上。
所述紧固单元可由导电性材料制成,并且所述外部连接盘可以形成为接触所述紧固单元。
所述紧固单元可由非导电性材料制成,并且所述方法还可包括:在形成所述芯片安装盘和所述外部连接盘之后,形成用于将所述外部连接端子电连接至所述外部连接盘的引线框。
可以通过加热和共烧来进行使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体的步骤。
所述方法还可包括:在将所述外部连接端子的一个端部***式紧固在所述紧固单元的所述槽内之后,在所述基板上形成壳体,以覆盖所述基板的一个表面以及所述半导体芯片并且使所述外部连接端子的另一端部暴露在外。
所述方法还可包括:在形成所述壳体之后,通过将模塑材料注射到所述壳体内来形成覆盖所述基板的所述一个表面以及所述半导体芯片的模塑构件。
附图说明
从结合附图的以下详细描述中,将更为清楚地理解本发明的上述以及其他目的、特征和优点,其中:
图1为示出根据本发明的第一优选实施方式的电源模块封装的结构的截面图;
图2为示出根据本发明的第二优选实施方式的电源模块封装的结构的截面图;
图3至图9为顺次地示出用于制造根据本发明的第一优选实施方式的电源模块封装的第一种方法的过程的截面图;
图10至图13为顺次地示出用于制造根据本发明的第二优选实施方式的电源模块封装的方法的过程的截面图;
图14至图16为顺次地示出用于制造根据本发明的第一优选实施方式的电源模块封装的第二种方法中的基板制造过程的截面图。
具体实施方式
从以下结合附图对优选实施方式进行的详细描述中,将更为清楚地理解本发明的目的、特征和优点。在所有附图中,使用相同的附图标记标示相同或相似的组成部件,并且省略其冗余描述。此外,在以下描述中,术语“第一”、“第二”、“一侧”、“另一侧”等用于将某一组成部件与其他组成部件区分开,而这样的组成部件的构造不应解释为受术语所限。此外,在本发明的描述中,当确认现有技术的详细描述会模糊本发明的主旨时,将省略其描述。
在下文中,将参照附图详细地描述本发明的优选实施方式。
电源模块封装
<第一优选实施方式>
图1为示出了根据本发明的第一优选实施方式的电源模块封装的结构的截面图。
参照图1,根据所述优选实施方式的电源模块封装100包括:外部连接端子130a和130b;基板110,在该基板110中沿厚度方向以预定的深度埋设有紧固单元,该紧固单元中***式紧固有外部连接端子130a和130b的端部;和半导体芯片120a和120b,该半导体芯片120a和120b安装在基板110的一个表面上。
在本实施方式中,基板110可以包括绝缘材料111、形成在绝缘材料111的一个表面上的电路层113以及形成在绝缘材料111的另一表面上的金属层115。
在此情形中,可以使用陶瓷作为绝缘材料111,但是绝缘材料111并不特别限定于此。
在本实施方式中,基板110具有一个表面和另一表面。在此情形中,参照图1,所述一个表面意味着其上安装有半导体芯片120a和120b的表面,即,其上形成有包括芯片安装盘113a和外部连接盘113b的电路层113的表面,并且所述另一表面可意味着与之相反的表面,即,其上形成有金属层115的表面。
在本实施方式中,如上所述,包括绝缘材料111、电路层113和金属层115的直接敷铜(DBC)基板是作为基板110的示例,但是基板110并不特别限定于此并且可以包括:例如,具有阳极氧化层的金属基板;印刷电路板(PCB);陶瓷基板;包括金属板、绝缘层和电路图案的基板;等等。
外部连接端子130a和130b是电连接至外部驱动IC以驱动安装在基板110上的半导体芯片120a和120b的组成部件。在本实施方式中,如图1所示,外部连接端子130a和130b形成为针型端子,但是本发明并不特别限定于此。
此处,半导体芯片120a和120b可以是功率元件。功率元件可包括可控硅整流器(SCR)、功率晶体管、绝缘栅双极型晶体管(IGBT)、MOS晶体管、功率整流器、功率调节器、逆变器、转换器或者通过组合这些元件而构造的高功率半导体芯片或二极管。
在本实施方式中,可以在半导体芯片120a和120b与芯片安装盘113a之间形成接合层(bonding layer)123,并且接合层123可以由具有相对较高的导热性的焊料或导电性环氧树脂构成以便有效地散热,但是并不特别限定于此。
在本实施方式中,半导体芯片120a和120b与基板110以及外部连接端子130a和130b可以通过使用导线121彼此电连接,但是并不特别限定于此。
此处,导线连接过程可以作为现有技术中所熟知的球形焊、楔形焊和针脚焊进行,但是并不特别限定于此。
此处,导线121可以由铝(Al)、金(Au)、铜等制成,但是本发明并不特别限定于此。通常使用由铝(Al)制成的导线,该导线施加高额定电压至作为功率元件的半导体芯片120a和120b。这是因为,为了承受高电压而使用粗导线,此处使用铝而不是金(Au)或铜(Cu)在降低成本方面更加有效。
在本实施方式中,允许外部连接端子130a和130b从中***式紧固的紧固单元140沿厚度方向以预定的深度埋设在基板110内。
此处,可在紧固单元140内沿长度方向形成允许外部连接端子130a和130b从中***的槽141。
虽然图中并未示出,但是为了提高外部连接端子130a和130b与紧固单元140之间的紧固力,可以在紧固单元140的槽141内形成悬挂凹槽(或悬挂突起)并且可以在被***槽141内的外部连接端子中形成悬挂突起(或悬挂凹槽)。
在本实施方式中,紧固单元140可以由导电性材料制成,但是并不特别限定于此。
然而,当紧固单元140由导电性材料制成时,只是被***式紧固在紧固单元140内的外部连接端子130a和130b以及与由导电性材料制成的紧固单元140相接触的外部连接盘113b可以彼此电连接,而不需要通过另外的结构。
如图1所示,根据优选实施方式的电源模块封装100还可包括壳体160,该壳体160形成为覆盖基板110的一个表面以及半导体芯片120a和120b并且使外部连接端子130a和130b的另一端部暴露在外。
在此情形中,壳体160可以包括允许模塑材料从中穿过以注入到壳体160内的开口区域160a。
根据优选实施方式的电源模块封装100还可包括密封构件150,该密封构件150形成为在壳体160内覆盖基板110的一个表面、半导体芯片120a和120b以及电连接半导体芯片120a和120b的导线121。
在此情形中,作为密封构件150,可以使用硅胶或环氧树脂模塑料(EMC),但是密封构件150并不特别限定于此。
此外,虽然未示出,但是根据本实施方式的电源模块封装100还可包括接合在基板110的另一表面(即金属层115的露出部分)上的散热器。
散热器可以包括用于使半导体芯片120a和120b散发的热量消散到空气中的多个散热片。
此外,散热器通常由铜(Cu)或锡(Sn)制成或者涂敷有铜(Cu)或锡(Sn)以便获得优异的散热性能并且容易与散热基体接合。然而,本发明并不特别限定于此。
在本实施方式中,由于用于将外部连接端子130a和130b***式紧固的紧固单元140形成为埋设在基板110内,所以与用于连接外部连接端子的构件是通过焊料焊接接合于基板的现有技术相比,可防止在接合交界处产生裂纹的可能性,因此能够提高产品的可靠性。
<第二优选实施方式>
图2为示出根据本发明的第二实施方式的电源模块封装的结构的截面图。
在第二实施方式中,将省略与上述第一实施方式的相同组成部件的描述,并且对于与第一实施方式中相同的组成部件将使用相同的附图标记。
参照图2,与第一实施方式一样,根据本实施方式的电源模块封装200包括:外部连接端子130a和130b;基板110,***式紧固有外部连接端子130a和130b的端部的紧固单元240沿厚度方向以预定的深度埋设在该基板110中;和安装在基板110的一个表面上的半导体芯片120a和120b。
此处,电源模块封装200还可包括用于将外部连接端子130a和130b电连接至外部连接盘113b的引线框(lead frame)210。
在本实施方式中,与根据第一优选实施方式的紧固单元140不同的是,以预定深度埋设在基板110内的紧固单元240可以由非导电性材料制成。
结果,由于***式紧固在紧固单元240内的外部连接端子130a和130b与外部连接盘113b没有彼此电连接,于是另外接合了用于电连接的引线框210。
在此情形中,引线框210和外部连接盘113b可以通过利用焊料或导电性环氧树脂彼此接合,但是本发明并不特别限定于此。
可以在引线框210中形成孔210a,该孔210a具有可供外部连接端子130a和130b贯穿的尺寸,并且可以通过贯穿引线框210的孔210a而将外部连接端子130a和130b的端部***式紧固到紧固单元240内。
在此情形中,可以在外部连接端子130a和130b与引线框210彼此接触的部位(即引线框210的孔210a处)额外形成焊料或导电性环氧树脂,由此也可以增加接合力。
同时,虽然图中未示出,但是当紧固单元240由非导电性材料制成时,电源模块封装200可以包括结合构件,该结合构件采用螺纹连接而不是引线框210的方式结合到紧固单元240内,并且该结合构件接触外部连接端子130a和130b被***其中的槽以及外部连接盘113b,以此作为另一优选实施方式。
在此情形中,可以在紧固单元240的除了埋设在基板110内的部分之外的从基板110突出的其它部分的外周面上形成螺钉螺纹(或螺旋槽)。
结合构件由导电性材料制成,并且可以包括:主体段,该主体段包括具有用于***外部连接端子130a和130b的槽的筒状第一主体部和与第一主体部连接的同时结合至紧固单元240的中空筒状第二主体部;以及连接段,该连接段的一个端部与主体段的外壁形成为一体并且另一端部接触外部连接盘113b。
在此情形中,可以在第二主体部的内壁上形成与紧固单元240的从110突出的部分的外周面上形成的螺钉螺纹(或螺纹槽)相对应的螺纹槽(或螺钉螺纹)。
可以在第一主体部内形成的槽中形成悬挂凹槽(或悬挂突起)并且可以在插在槽内的外部连接端子130a和130b中形成悬挂突起(或悬挂凹槽)。
用于制造电源模块封装的方法
<第一优选实施方式>
图3至图9为顺次地示出用于制造根据本发明的第一优选实施方式的电源模块封装的第一种方法的过程的截面图。图14至图16为顺次地示出在用于制造根据本发明的第一优选实施方式的电源模块封装的第二种方法中的基板制造过程的截面图。
首先,参照图3,制备在其一个表面形成有沟111a的绝缘材料111。
在本实施方式中,绝缘材料111可以由陶瓷制成,但是并不特别限定于此。
在本实施方式中,沟111a可以通过利用激光钻形成,但是并不特别限定于此。
沟111a可以形成为从绝缘材料111的表面沿厚度方向直至预定深度,并且紧固单元140的一部分(即底部)可在随后的过程中***到如此形成的沟111a内。
接下来,参照图4,将绝缘材料111、电路层113、金属层115和紧固单元140结合成整体。
下面将详细描述该步骤。
首先,将去除了与沟111a对应的部分的电路层113放置在绝缘材料111的一个表面上,该绝缘材料111的一个表面上形成有沟111a,并且将金属层115放置在绝缘材料111的另一表面上,之后将紧固单元140***到电路层113的去除部分以及沟111a内,之后进行加热和共烧(cofired)。
同时,如图14至图16所示,该步骤可以按照如下顺序进行:制备在其一个表面上形成有沟111a的绝缘材料111,制备在与沟111a对应的部分处形成有紧固单元140的电路层113,之后将电路层113放置在绝缘材料111的一个表面上以使得紧固单元140***到沟111a内并且将金属层115放置在绝缘材料111的另一表面上,之后进行加热和共烧。
结果,可以使绝缘材料111、电路层113、金属层115和紧固单元140成为整体。
在本实施方式中,电路层113和金属层115可以由铜(Cu)制成,但是并不特别限定于此。
在本实施方式中,紧固单元140可以由导电性材料制成,但是并不特别限定于此。
像这样,***式紧固有外部连接端子130a和130b的紧固单元140沿厚度方向以预定深度被埋设在基板110内,使得与现有技术中通过焊料接合的紧固单元接合方法相比,可以在比较精确的位置形成紧固单元140。
像这样,由于对于每个模块,在比较一致的位置形成紧固单元140,所以外部连接端子的***过程还可以平滑地进行。
接下来,参照图5,加工(patterned)电路层113以形成芯片安装盘113a和外部连接盘113b。
在此情形中,外部连接盘113b可以形成为接触紧固单元140,结果,***式紧固在由导电性材料制成的紧固单元140内的外部连接端子130a和130b与外部连接盘113b可以电连接,而不需要通过另外的结构。
接下来,参照图6,将半导体芯片120a和120b接合至芯片安装盘113a。
在此情形中,可以通过利用焊料或导电性环氧树脂将半导体芯片120a和120b与芯片安装盘113a彼此接合,但是并不特别限定于此。
像这样,将半导体芯片120a和120b接合至芯片安装盘113a,之后通过利用导线121的导线连接过程可以将半导体芯片120a和120b与电路图案113彼此电连接。
在此情形中,可以和现有技术中熟知的球形焊、楔形焊和针脚式焊一样进行导线连接过程,但是并不特别限定于此。
导线121可以由铝(Al)、金(Au)、铜(Cu)等制成,但是本发明并不特别限定于此。通常使用由铝(Al)制成的导线,以施加高额定电压至作为功率元件的半导体芯片120a和120b中。这是因为,为了承受高电压而使用粗电线,此处使用铝而不是金(Au)或铜(Cu)在降低成本方面更加有效。
接下来,参照图7,将外部连接端子130a和130b的端部***式紧固到紧固单元140的槽141内。
此处,为了提高外部连接端子130a和130b与紧固单元140之间的紧固力,可以在紧固单元140的槽141内形成悬挂凹槽(或悬挂突起)(未示出),并且可以在外部连接端子130a和130b的***部分上形成与所述悬挂凹槽(或悬挂突起)(未示出)相对应的悬挂突起(或悬挂凹槽)(未示出),但是本发明并不特别限定于此。
接下来,参照图8,形成壳体160,该壳体160与半导体芯片120a和120b安装(mount)在一起,覆盖基板110的一个表面以及***式紧固有外部连接端子130a和130b的基板110上的半导体120a和120b,并且使外部连接端子130a和130b的另一端部暴露在外。
在此情形中,壳体160可以包括允许模塑材料穿过其中并注入到壳体160内的开口区域160a。
接下来,参照图9,使模塑材料通过开口区域160a填充到壳体160内以形成覆盖基板110的一个表面以及半导体芯片120a和120b的密封构件150。
此处,硅胶、环氧树脂模塑料(EMC)等可以用作模塑材料,但是本发明并不特别限定于此。
<第二优选实施方式>
图10至图12为顺次地示出用于制造根据本发明的第二优选实施方式的电源模块封装的方法的过程的截面图。
在本实施方式中,将省略与上述第一实施方式的相同组成部件的描述,并且对于与第一实施方式的相同组成部件将使用相同的附图标记。
在优选的实施方式中,使绝缘材料、电路层、金属层和紧固单元成为整体的步骤与第一优选实施方式中的相同,因而将省略其描述。
在本实施方式中,紧固单元240可以由非导电性材料制成。
参照图10,将半导体芯片120a和120b安装在基板110的芯片安装盘113a上并且将引线框210接合至外部连接盘113b。
在此情形中,可以通过利用焊料或导电性环氧树脂将半导体芯片120a和120b、芯片安装盘113a、引线框210以及外部连接盘115b接合,但是并不特别限定于此。
本实施方式中使用的引线框210可以在其中央处形成有孔210a,如图10所示。
孔210a是外部连接端子130a和130b在随后的过程中所贯穿的部分,孔210a的位置与紧固单元240的槽241的位置对应,并且孔210a的直径可以与紧固单元240的槽241的直径以及外部连接端子130a和130b的直径相同,但是并不特别限定于此。
接下来,参照图11,使每个外部连接端子130a和130b的一个端部贯穿引线框210的孔210a,以***式紧固到紧固单元240的槽241内。
在此情形中,为了提高紧固力,可以在紧固单元240的槽241内形成悬挂凹槽(或悬挂突起)(未示出),并且在***于槽241内的外部连接端子130a和130b中形成与所述悬挂凹槽(或悬挂突起)(未示出)对应的悬挂突起(或悬挂凹槽)(未示出)。
接下来,虽然图中未示出,但是为了提高外部连接端子130a及130b和与之接触的引线框210之间的紧固力,可以通过利用焊料或导电性环氧树脂将引线框210的孔210a与贯穿孔210a的外部连接端子130a和130b彼此接合。
同时,虽然图中未示出,但是当紧固单元240由非导电性材料制成时,电源模块封装200可以通过利用具有连接部的结合构件将外部连接端子130a和130b与基板110机械连接并且电连接,所述结合构件的连接部采用螺纹连接而不是引线框210的方式结合到紧固单元240内并且接触外部连接端子130a和130b被***其中的槽以及外部连接盘113b,以此作为另一优选实施方式。
详细地,制备紧固单元240,该紧固单元240在除了埋设于基板110内之外的其它部分的外周面上形成有螺钉螺纹(或螺纹槽),并且形成基板110,该基板110与所制备的紧固单元240结合成一体。
接下来,制备结合构件,该结合构件由导电性材料制成,并且包括:主体段,该主体段包括具有用于***外部连接端子130a和130b的槽的筒状第一主体部和与第一主体部连接的同时结合至紧固单元240的中空筒状第二主体部;和连接段,该连接段的一个端部与主体段的外壁形成为一体并且另一端部接触外部连接盘113b。
在此情形中,可以在第二主体部的内壁上形成与紧固单元240的从基板110突出的部分的外周面上所形成的螺钉螺纹(或螺纹槽)相对应的螺纹槽(或螺钉螺纹)。
可以在第一主体部中所形成的槽内形成悬挂凹槽(或悬挂突起)并且可以在插于槽内的外部连接端子130a和130b中形成与所述悬挂凹槽(或悬挂突起)(未示出)相对应的悬挂突起(或悬挂凹槽)(未示出)。
接下来,将结合构件用螺纹连接方式紧固于紧固单元240,并且将外部连接端子130a和130b***式紧固到结合构件的槽内。
在上述方式中,外部连接端子130a和130b与基板110相连,使得无需另外的接合过程,从而节约了工艺成本,并且由于结合构件仅采用螺纹连接方式紧固于紧固单元且外部连接端子装配在结合构件的槽内,所以可以使过程简化。
接下来,参照图12至图13,在基板110上形成壳体160,并且将模塑材料注入壳体160的开口区域160a内,以形成覆盖基板110的一个表面以及半导体芯片120a和120b的模塑构件150。
根据本发明的优选实施方式,由于用于将外部连接端子紧固于基板上的单元的接合过程不再需要,因而能够减少过程的数量,使过程简化。
此外,由于在基板内安装了用于***外部连接端子的紧固单元,在制造各个产品时紧固单元的位置相对一致,因此能够容易地紧固外部连接端子。
另外,由于在基板内安装了用于***外部连接端子的紧固单元,所以与通过焊料接合安装在基板上的相关技术的紧固单元相比,没有可能在基板与紧固单元的交界处产生裂纹。
虽然为了说明的目的已经公开了本发明的实施方式,但是应该理解的是本发明并不限定于此,并且本领域技术人员可理解的是,可以在不脱离发明的范围和精神的情况下做出各种修改、添加和替换。
因此,任何以及所有修改、变型或等同配置都应该被视为落入本发明的保护范围内,并且将通过随附的权利要求书公开本发明的具体保护范围。

Claims (15)

1.一种电源模块封装,该电源模块封装包括:
外部连接端子;
基板,在该基板中沿厚度方向以预定深度埋设有紧固单元,该紧固单元允许所述外部连接端子的一个端部***式紧固于所述紧固单元上;和
半导体芯片,该半导体芯片安装在所述基板的一个表面上,并且
其中,所述紧固单元由非导电性材料制成,并且所述电源模块封装还包括将所述外部连接端子电连接至所述基板的引线框。
2.根据权利要求1所述的电源模块封装,其特征在于,所述基板包括:
绝缘材料;
电路层,该电路层形成在所述绝缘材料的一个表面上并且所述电路层包括芯片安装盘和外部连接盘;和
金属层,该金属层形成在所述绝缘材料的另一个表面上。
3.根据权利要求1所述的电源模块封装,其特征在于,所述紧固单元还包括槽,在所述紧固单元内形成的所述外部连接端子***到所述槽中,并且
在所述槽和***于所述槽内的所述外部连接端子中分别形成有悬挂凹槽和与所述悬挂凹槽相对应的悬挂突起。
4.根据权利要求1所述的电源模块封装,其特征在于,所述电源模块封装还包括壳体,该壳体形成在所述基板上,以覆盖所述基板的一个表面和所述半导体芯片,并且使所述外部连接端子的另一个端部暴露在外。
5.根据权利要求4所述的电源模块封装,其特征在于,所述电源模块封装还包括密封构件,该密封构件形成在所述壳体内,以覆盖所述基板的所述一个表面和所述半导体芯片。
6.一种用于制造电源模块封装的方法,该方法包括:
制备基板并在该基板中沿厚度方向以预定深度埋设紧固单元,该紧固单元具有形成于其中的用于***式紧固外部连接端子的槽;
将半导体芯片安装在所述基板上;以及
将所述外部连接端子的一个端部***式紧固在所述紧固单元的所述槽内,并且
形成用于将所述外部连接端子电连接至所述基板的引线框,其中所述紧固单元由导电性材料制成。
7.根据权利要求6所述的方法,其特征在于,所述制备基板并在该基板中沿厚度方向以预定深度埋设紧固单元的步骤包括:
准备绝缘材料;
在所述绝缘材料的一个表面上形成预定深度的沟;
在所述绝缘材料的一个表面上,布置电路层,该电路层上与所述沟相对应的部分被去除;
在所述绝缘材料的另一个表面上布置金属层;以及
将所述紧固单元***到所述沟内,并且使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体。
8.根据权利要求7所述的方法,其特征在于,所述方法还包括:
在使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体之后,通过使所述电路层形成图案而形成芯片安装盘和外部连接盘,
其中,将所述半导体芯片安装在所述芯片安装盘上。
9.根据权利要求7所述的方法,其特征在于,通过加热和共烧来进行使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体的步骤。
10.根据权利要求7所述的方法,其特征在于,通过利用激光钻来进行形成所述沟的步骤。
11.根据权利要求6所述的方法,其特征在于,所述制备基板并在该基板中沿厚度方向以预定深度埋设紧固单元的步骤包括:
准备绝缘材料;
在所述绝缘材料的一个表面上形成预定深度的沟;
在所述绝缘材料的一个表面上,布置电路层,该电路层上与所述沟相对应的部分被去除;
在所述绝缘材料的另一个表面上布置金属层;并且
使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体。
12.根据权利要求11所述的方法,其特征在于,所述方法还包括:
在使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体之后,通过使所述电路层形成图案而形成芯片安装盘和外部连接盘,
其中,将所述半导体芯片安装在所述芯片安装盘上。
13.根据权利要求11所述的方法,其特征在于,通过加热和共烧来进行使所述绝缘材料、所述电路层、所述金属层和所述紧固单元成为整体的步骤。
14.根据权利要求6所述的方法,其特征在于,所述方法还包括:
在将所述外部连接端子的一个端部***式紧固在所述紧固单元的所述槽内之后,在所述基板上形成壳体,以覆盖所述基板的一个表面以及所述半导体芯片并且使所述外部连接端子的另一个端部暴露在外。
15.根据权利要求14所述的方法,其特征在于,所述方法还包括:
在形成所述壳体之后,通过将模塑材料注射到所述壳体内来形成覆盖所述基板的所述一个表面以及所述半导体芯片的模塑构件。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515364A (zh) * 2012-06-29 2014-01-15 三星电机株式会社 电源模块封装和用于制造电源模块封装的方法
JP2015026820A (ja) * 2013-06-18 2015-02-05 株式会社デンソー 電子装置
KR102143890B1 (ko) * 2013-10-15 2020-08-12 온세미컨덕터코리아 주식회사 파워 모듈 패키지 및 이의 제조 방법
JP5910653B2 (ja) * 2014-03-18 2016-04-27 トヨタ自動車株式会社 放熱板付きリードフレーム、放熱板付きリードフレームの製造方法、半導体装置、および半導体装置の製造方法
KR101562661B1 (ko) * 2014-03-18 2015-10-22 삼성전기주식회사 전력모듈 패키지
US9620877B2 (en) 2014-06-17 2017-04-11 Semiconductor Components Industries, Llc Flexible press fit pins for semiconductor packages and related methods
TWI544868B (zh) * 2014-07-11 2016-08-01 台達電子工業股份有限公司 散熱模組及其結合方法
DE112015001002B4 (de) * 2014-10-14 2023-08-10 Fuji Electric Co., Ltd. Halbleitervorrichtung
US9431311B1 (en) 2015-02-19 2016-08-30 Semiconductor Components Industries, Llc Semiconductor package with elastic coupler and related methods
CN105118816A (zh) * 2015-08-25 2015-12-02 无锡新洁能股份有限公司 功率端子以及利用所述功率端子的功率模块
WO2018138961A1 (ja) * 2017-01-27 2018-08-02 京セラ株式会社 セラミック回路基板、パワーモジュールおよび発光装置
CN108447827B (zh) * 2018-03-17 2020-04-17 临沂金霖电子有限公司 一种电力转换电路的封装模块
US11569141B2 (en) * 2018-08-08 2023-01-31 Mitsubishi Electric Corporation Semiconductor device including a groove within a resin insulating part positioned between and covering parts of a first electrode and a second electrode
CN110676233B (zh) * 2019-09-10 2021-09-24 深圳第三代半导体研究院 一种压接式功率开关模块及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592021A (en) * 1995-04-26 1997-01-07 Martin Marietta Corporation Clamp for securing a power device to a heatsink
US6421244B1 (en) * 1999-12-28 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Power module

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2596607A1 (fr) * 1986-03-28 1987-10-02 Bull Sa Procede de montage d'un circuit integre sur une carte de circuits imprimes, boitier de circuit integre en resultant et ruban porteur de circuits integres pour la mise en oeuvre du procede
JP3168901B2 (ja) 1996-02-22 2001-05-21 株式会社日立製作所 パワー半導体モジュール
JPH11330283A (ja) * 1998-05-15 1999-11-30 Toshiba Corp 半導体モジュール及び大型半導体モジュール
CN1460293A (zh) * 2001-04-09 2003-12-03 株式会社住友金属电设备 散热型bga封装及其制造方法
US7180169B2 (en) * 2003-08-28 2007-02-20 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for manufacturing the same
JP2005217093A (ja) 2004-01-29 2005-08-11 Kyocera Corp 光半導体素子収納用パッケージ
US7663232B2 (en) * 2006-03-07 2010-02-16 Micron Technology, Inc. Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
KR101203466B1 (ko) 2006-04-20 2012-11-21 페어차일드코리아반도체 주식회사 전력 시스템 모듈 및 그 제조 방법
JP4634498B2 (ja) 2008-11-28 2011-02-16 三菱電機株式会社 電力用半導体モジュール
JP4766162B2 (ja) 2009-08-06 2011-09-07 オムロン株式会社 パワーモジュール
KR101216896B1 (ko) 2011-02-11 2012-12-28 서울특별시도시철도공사 파워 모듈

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592021A (en) * 1995-04-26 1997-01-07 Martin Marietta Corporation Clamp for securing a power device to a heatsink
US6421244B1 (en) * 1999-12-28 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Power module

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