CN205353187U

CN205353187U - Transient voltage recorder based on FPGA

Info

Publication number: CN205353187U
Application number: CN201520855972.9U
Authority: CN
Inventors: 姜龙; 徐德超; 谢荣斌; 薛静; 张霖; 杨超; 刘波; 张丽娟; 李诗勇; 施艳; 李冶; 吴湘黔
Original assignee: Guiyang Power Supply Bureau Guizhou Power Grid Co ltd
Current assignee: Guiyang Power Supply Bureau Guizhou Power Grid Co ltd
Priority date: 2015-10-30
Filing date: 2015-10-30
Publication date: 2016-06-29
Anticipated expiration: 2025-10-30

Abstract

The utility model discloses a transient voltage recorder based on FPGA, include: analog to digital conversion circuit, FPGA chip circuit, DSP data signal treatment circuit, memory circuit and clock, power and restorer circuit, the utility model discloses because adoption FPGA hardware compresses in real time, the peak value calculates, trigger the judgement, adopts the assembly line framework, can accomplish a large amount of data operation in a clock cycle to very big improvement DSP's efficiency, make and should adorn multichannel synchronous sampling speed and can reach 20M, satisfied the record demand to the various transient that fast, change at a slow speed.

Description

Transient voltage recording device based on FPGA

Technical field

This utility model relates to waveform recording field, particularly to a kind of transient voltage recording device based on FPGA.

Background technology

Electrical network is in operation it may happen that various fault, and some meetings cause power failure and cause equipment damage.The process of electric network fault is usually associated with the disturbance of system voltage.Or even thunderbolt, switching overvoltage, power-frequency overvoltage, pollution flashover, equipment fault etc., can cause grid disturbances power grid accident.Before record power grid accident, the disturbance situation of line voltage, has important value for accident inversion and analysis.Want complete documentation grid disturbances, both required high sampling rate, with the needs of satisfied record thunder and lightning waveform etc.；The memory time rectificated again, record long-term accident process to meet.When adopting higher sample rate, in order to save memory space, it will usually adopt some compressions to process.In conventional transient voltage record, DSP is generally adopted to directly read the data of high-speed a/d and make Real Time Compression, storage and trigger judgement etc., CPU is in the process of continuous peek, compression, process, take the CPU plenty of time, cause that CPU is not free and do other work, thus having to reduce sample rate.Along with developing rapidly of on-site programmable gate array FPGA, FPGA is adopted to realize data compression, be treated as a kind of new means.Owing to there being the memorizer of a number of trigger, comparator, larger capacity inside FPGA, for realizing data acquisition, compression, judgement provide possibility.

Utility model content

In view of this, the purpose of this utility model is to provide a kind of transient voltage recording device based on FPGA, process circuit by increasing FPGA, it is possible to realize the high speed acquisition of transient process that is electrical network is various quickly, that change at a slow speed, solve the sample rate reduction problem that existing apparatus causes because CPU takies.

The purpose of this utility model is achieved through the following technical solutions:

It is somebody's turn to do the transient voltage recording device based on FPGA, including:

Analog to digital conversion circuit, including analog signal conditioner circuit, A/D conversion chip and peripheral circuit thereof, for analogue signal is nursed one's health and analog digital conversion, and output digit signals is to FPGA chip circuit；

FPGA chip circuit, including fpga chip and peripheral circuit thereof, the data after fpga chip processes are read out by DSP digital signal processing circuit；

DSP digital signal processing circuit, including dsp chip and peripheral circuit thereof, reads the data after fpga chip processes and transmits to memory circuitry；

Memory circuitry, including FLASH memory and dynamic memory, is used for storing data；

Clock, power supply and positor circuit.

Further, described fpga chip includes Real Time Compression module and peak computation module.

Further, described fpga chip also includes triggering judge module.

Further, described fpga chip also includes low rate acquisition module.

The beneficial effects of the utility model are:

This utility model carries out Real Time Compression, peak computational, triggering judgement owing to adopting FPGA hardware, adopt pipelined architecture, substantial amounts of data operation can be completed within a clock cycle, thus greatly improving the efficiency of DSP, make this dress multi-channel synchronal sampling speed up to 20M, meet the record demand to the various transient processes changed quickly, at a slow speed.

Other advantages of the present utility model, target and feature will be illustrated to a certain extent in the following description, and to a certain extent, will be apparent to those skilled in the art based on to investigating hereafter, or can be instructed from practice of the present utility model.Target of the present utility model and other advantages can be realized by description below and obtain.

Accompanying drawing explanation

In order to make the purpose of this utility model, technical scheme and advantage clearly, below in conjunction with accompanying drawing, this utility model is described in further detail, wherein:

Fig. 1 is that structure of the present utility model connects block diagram；

Fig. 2 is hardware connection figure of the present utility model.

Detailed description of the invention

Hereinafter with reference to accompanying drawing, preferred embodiment of the present utility model is described in detail.Should be appreciated that preferred embodiment is only for illustrating this utility model, rather than in order to limit protection domain of the present utility model.

As shown in Figure 1 and Figure 2, this utility model based on the transient voltage recording device of FPGA, including:

(1) analog to digital conversion circuit 1: include analog signal conditioner circuit, A/D conversion chip and peripheral circuit thereof, for analogue signal is nursed one's health and analog digital conversion, and output digit signals is to FPGA chip circuit；

(2) FPGA chip circuit 2: include fpga chip and peripheral circuit thereof, described fpga chip includes Real Time Compression module, peak computation module, triggering judge module and low rate acquisition module, and the data after fpga chip processes are read out by DSP digital signal processing circuit；

(3) DSP digital signal processing circuit 3: include dsp chip and peripheral circuit thereof, reads the data after fpga chip processes and transmits to memory circuitry；

(4) memory circuitry 4: include FLASH memory and dynamic memory, are used for storing data；

(5) clock, power supply and positor circuit 5: produce input A/D chip and the 20M global clock of fpga chip, power supply and reset signal.

In the present embodiment, the operation principle of this device is as follows:

Analog voltage signal enters adc circuit, it is amplified, after the rising edge of clock signal carries out A/D conversion, enter FPGA, at the trailing edge of clock signal, FPGA to simultaneously complete 4 work: (1) FPGA is compressed according to compression comparison data, the data write half-full backward DSP of FIFO, FIFO after compression sends half-full signal, after DSP receives half-full signal, read the data in FIFO, be stored in dynamic memory；(2) data of this reading and previous data are compared by FPGA, obtain positive peak and negative peak, the every 20ms of DSP reads a minor peaks, and compare in previous peak value, if reaching to start threshold value, then according to length set in advance, data in dynamic memory are stored in FLASH memory.(3) data of this reading and higher limit set in advance, lower limit are compared by FPGA, if reaching entry condition, then sending triggering signal to DSP, DSP starts record, by pre-set record length, the data in dynamic memory is stored in FLASH memory.(4) low rate collection, data are carried out snap shot compression according to pre-set frequency by FPGA, are stored in FIFO, wait that DSP reads.

The key problem in technology of the present invention is to have employed pipelined architecture in FPGA programs data are carried out Real Time Compression, adopt parallel computing mode, the process of mass data computing demonstrates FPGA data and processes the superiority with computing, the collection of data, compression, storage, peak computational can be completed in a sampling clock cycle and trigger judgement.

What finally illustrate is, above example is only in order to illustrate the technical solution of the utility model and unrestricted, although this utility model being described in detail with reference to preferred embodiment, it will be understood by those within the art that, the technical solution of the utility model can be modified or equivalent replacement, without deviating from objective and the scope of the technical program, it all should be encompassed in the middle of right of the present utility model.

Claims

1. based on the transient voltage recording device of FPGA, it is characterised in that: described device includes:

Analog to digital conversion circuit, including analog signal conditioner circuit, A/D conversion chip, for analogue signal is nursed one's health and analog digital conversion, and output digit signals is to FPGA chip circuit；

FPGA chip circuit, including fpga chip, the data after fpga chip processes are read out by DSP digital signal processing circuit；

DSP digital signal processing circuit, including dsp chip, reads the data after fpga chip processes and transmits to memory circuitry；

Clock, power supply and positor circuit.

2. the transient voltage recording device based on FPGA according to claim 1, it is characterised in that: described fpga chip includes Real Time Compression module and peak computation module.

3. the transient voltage recording device based on FPGA according to claim 1 and 2, it is characterised in that: described fpga chip also includes triggering judge module.

4. the transient voltage recording device based on FPGA according to claim 3, it is characterised in that: described fpga chip also includes low rate acquisition module.