CN203414947U

CN203414947U - FPGA (Field Programmable Gate Array)-based multi-channel high-speed voltage and resistance isolating acquisition card

Info

Publication number: CN203414947U
Application number: CN201320378801.2U
Authority: CN
Inventors: 吴锦来
Original assignee: DONGGUAN FRIENDS INSTRUMENT Co Ltd
Current assignee: DONGGUAN FRIENDS INSTRUMENT Co Ltd
Priority date: 2013-06-27
Filing date: 2013-06-27
Publication date: 2014-01-29
Anticipated expiration: 2023-06-27

Abstract

The utility model relates to the technology of a data acquisition card, in particular to an FPGA (Field Programmable Gate Array)-based multi-channel high-speed voltage and resistance isolating acquisition card. The acquisition card comprises a plurality of data acquisition channels, data and power isolating units corresponding to the data acquisition channels, an FPGA chip and a communication interface, wherein the communication interface is used for externally connecting an upper computer; the data acquisition channels are connected with a data acquisition end of the FPGA chip through the data and power isolating units; an output end of the FGPA chip is connected with the communication interface. The acquisition card has a synchronous execution capacity by using the FPGA, so that the FPGA chip can synchronize the data acquired by the data acquisition channels, i.e., the voltage data or resistance data can be synchronously acquired by the data acqusition channels; thus, the comparability of the acqusition result is guaranteed, the error of the acquired data is reduced and the data acqusition efficiency is improved.

Description

A kind of hyperchannel isolation high speed voltage and electrical resistance collection card based on FPGA

Technical field

The utility model relates to data acquisition card technique, relate in particular to a kind of based on FPGA(field programmable gate array, English name: hyperchannel Field-Programmable Gate Array) isolation high speed voltage and electrical resistance collection card.

Background technology

Data collecting card, refers to from the analog-and digital-unit under tests such as sensor and other Devices to test and gathers non electrical quantity or electric quantity signal, then delivers to the board of analyzing and processing in host computer.At present, the data acquisition modes of data collecting card, great majority are by the switching of relay, to connect one by one data acquisition channel, to gather the data of all bus data acquisition passage.The image data object of this data collecting card is single, conventionally only possesses the function that gathers voltage data, and, when the data of acquisition channel are different, asynchronous, can affect the comparability of collection result, image data error is larger, and image data efficiency is lower.

Utility model content

The purpose of this utility model is to provide a kind of for the deficiencies in the prior art and guarantees collection result comparability, reduces image data error, improves hyperchannel isolation high speed voltage and the electrical resistance collection card based on FPGA of image data efficiency.

The purpose of this utility model realizes by following technical measures: a kind of hyperchannel isolation high speed voltage and electrical resistance collection card based on FPGA, comprise several data acquisition channels, also comprise the data corresponding with each data acquisition channel and isolated from power unit, fpga chip, for the communication interface of external host computer; Described data acquisition channel is connected with the data acquisition end of described fpga chip by described data and isolated from power unit, makes described data acquisition channel by data and isolated from power unit, send the data that collect to fpga chip; The output terminal of described fpga chip is connected with described communication interface, makes the data that described fpga chip obtains computing send outside host computer to by communication interface.

Preferably, described fpga chip is provided with for storing the RAM(random access memory of the data that computing obtains, English name: random access memory) unit, this ram cell is connected with described communication interface.

Preferably, described data and isolated from power unit adopt integrated circuit (IC) chip, and the model of this integrated circuit (IC) chip is ADUM5401.

Preferably, described data acquisition channel adopts integrated circuit (IC) chip, and the model of this integrated circuit (IC) chip is AD7793.

The utility model beneficial effect is:

The utility model has utilized FPGA to have the ability of synchronous execution, the data that fpga chip can be gathered several data acquisition channels are carried out synchronization, be that a plurality of data acquisition channels can synchronous acquisition voltage data or resistance data, thus guaranteed collection result comparability, reduce image data error, improve the efficiency of image data.

Accompanying drawing explanation

Fig. 1 is frame principle figure of the present utility model.

Fig. 2 is the circuit theory diagrams of data acquisition channel of the present utility model and data and isolated from power unit.

Embodiment

Below in conjunction with accompanying drawing, the utility model is further described.

Please refer to Fig. 1 and Fig. 2, the hyperchannel of the utility model based on FPGA isolation high speed voltage and electrical resistance collection card, comprise several data acquisition channels 1, data corresponding with each data acquisition channel 1 and isolated from power unit 2, fpga chip 3, for the communication interface 4 of external host computer.Data acquisition channel 1 is connected with the data acquisition end of fpga chip 3 by data and isolated from power unit 2, makes data acquisition channel 1 by data and isolated from power unit 2, send the data that collect to fpga chip 3; The output terminal of fpga chip 3 is connected with communication interface 4, makes the data that fpga chip 3 obtains computing send outside host computer to by communication interface 4.

Specifically, fpga chip 3 is provided with for storing the ram cell of the data that computing obtains, and this ram cell is connected with communication interface 4, makes outside host computer read the data that the computing in ram cell obtains by communication interface 4.

Wherein, data and isolated from power unit 2 adopt integrated circuit (IC) chip, the model of this integrated circuit (IC) chip is ADUM5401, as shown in Fig. 2 (drawing one of them data acquisition channel 1 and data and the isolated from power unit 2 corresponding with it), integrated circuit (IC) chip and peripheral circuit thereof that each data and isolated from power unit 2 are ADUM5401 by model form.Like this, data and isolated from power unit 2 can will isolate between all data acquisition channels 1 completely, and the isolation that single-chip carries out contributes to the miniaturization of product and improves global reliability.

Wherein, data acquisition channel 1 adopts integrated circuit (IC) chip, the model of this integrated circuit (IC) chip is AD7793, as shown in Figure 2, be that integrated circuit (IC) chip and the peripheral circuit thereof that each data acquisition channel 1 is AD7793 by model forms, because the AD that the integrated circuit (IC) chip that model is AD7793 can be carried out magnitude of voltage gathers, and recycles its inner constant current source and carries out the measurement to measured object resistance value.

Principle of work of the present utility model is as follows: by all data acquisition channels 1 synchronous acquisition, and by the analog quantity digital quantity of image data (be about to simulating signal and be converted to digital signal), then, each data acquisition channel 1 is sent to fpga chip 3 by the data corresponding with it and isolated from power unit 2 by the signal of digital quantity, signal by 3 pairs of these digital quantities of fpga chip carries out computing, obtain correct magnitude of voltage or resistance value, again this magnitude of voltage or resistance value are stored in ram cell, wait for reading of communication interface 4.

Therefore, the utility model has utilized FPGA to have the ability of synchronous execution, the data that fpga chip 3 can be gathered several data acquisition channels 1 are carried out synchronization, be that a plurality of data acquisition channels 1 can synchronous acquisition voltage data or resistance data, thus guaranteed collection result comparability, reduce image data error, improve the efficiency of image data.For example: can be set to 16 data acquisition channels 1, with these 16 data acquisition channels 1 16 data and isolated from power unit 2 one to one, 16 data acquisition channels 1 can moment synchronous acquisition voltage data or resistance data, make the data result comparability of collection high, and unit interval image data efficiency improves, error is little, can test the Instantaneous Situation value of hyperchannel out-put supply supply.Certainly, the utility model image data object can switch arbitrarily collection between voltage, resistance.

Finally should be noted that; above embodiment is only in order to illustrate the technical solution of the utility model; but not restriction to the utility model protection domain; although the utility model has been done to explain with reference to preferred embodiment; those of ordinary skill in the art is to be understood that; can modify or be equal to replacement the technical solution of the utility model, and not depart from essence and the scope of technical solutions of the utility model.

Claims

1. the hyperchannel based on FPGA is isolated high speed voltage and electrical resistance collection card, comprise several data acquisition channels, it is characterized in that: also comprise the data corresponding with each data acquisition channel and isolated from power unit, fpga chip, for the communication interface of external host computer; Described data acquisition channel is connected with the data acquisition end of described fpga chip by described data and isolated from power unit, makes described data acquisition channel by data and isolated from power unit, send the data that collect to fpga chip; The output terminal of described fpga chip is connected with described communication interface, makes the data that described fpga chip obtains computing send outside host computer to by communication interface.

2. hyperchannel based on FPGA isolation high speed voltage according to claim 1 and electrical resistance collection card, is characterized in that: described fpga chip is provided with for storing the ram cell of the data that computing obtains, and this ram cell is connected with described communication interface.

3. hyperchannel isolation high speed voltage and the electrical resistance collection card based on FPGA according to claim 1, is characterized in that: described data and isolated from power unit adopt integrated circuit (IC) chip, and the model of this integrated circuit (IC) chip is ADUM5401.

4. hyperchannel isolation high speed voltage and the electrical resistance collection card based on FPGA according to claim 1, is characterized in that: described data acquisition channel adopts integrated circuit (IC) chip, and the model of this integrated circuit (IC) chip is AD7793.