CN205263807U - Double - circuit FC circuit structure of PCIe interface - Google Patents
Double - circuit FC circuit structure of PCIe interface Download PDFInfo
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- CN205263807U CN205263807U CN201521037490.9U CN201521037490U CN205263807U CN 205263807 U CN205263807 U CN 205263807U CN 201521037490 U CN201521037490 U CN 201521037490U CN 205263807 U CN205263807 U CN 205263807U
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Abstract
The utility model relates to a double - circuit FC circuit structure of PCIe interface. This circuit contains treater, intersection switch module, general processing unit, host interface and ASM protocol processor, the treater and the switch module that intersects are connected through two -way PLB0, PLB1 bus and general processing unit through two -way data DMA path connection, the switch module that intersects, alternately the switch module is through two -way PLB0 bus and host interface and the connection of ASM protocol processor, and the host interface is connected with the ASM protocol processor through two -way bus and control interface. The utility model discloses can realize the analysis and the processing of two way FC -AE -ASM agreement data simultaneously, for under the applied situation of multi -processor, the machine of buildding carries FC network application environment and provides safeguard.
Description
Technical field
The utility model belongs to computer hardware technology, relates to a kind of two-way FC circuit structure of PCIE interface.
Background technology
FC network has high bandwidth, low delay and the feature such as highly reliable, is highly suitable for the reality to transfer of dataIn the avionics system that Shi Xing, reliability have higher requirements, use.
In the particular surroundings of aerospace applications, in the face of high functional density, the performance densimeter data of multiprocessorProcessing demands, data throughput between multiprocessor and FC network affects processing to a certain extentOverall performance.
Utility model content
The utility model is to solve the above-mentioned technical problem existing in background technology, and provides a kind of efficient oneThe two-way FC circuit structure of kind of PCIE interface, can solve subsidiary high-performance processor, General Porcess Unit,The FC-AE-ASM protocol treatment circuit design of two-way PCIe HPI, two-way ASM protocol processes interfaceProblem, provide safeguard for building the airborne FC network platform.
Technical solution of the present utility model is: the utility model is a kind of two-way FC electricity of PCIE interfaceLine structure, its special character is: this circuit comprise processor, cross switch module, General Porcess Unit,HPI and ASM protocol processor; Processor and cross switch module connect by bi-directional data DMA passageConnect, cross switch module is connected with General Porcess Unit by two-way PLB0, PLB1 bus; Intersection is openedClose module and be connected with HPI and ASM protocol processor by two-way PLB0 bus, HPI is logicalCrossing two-way bus is connected with ASM protocol processor with control interface.
Above-mentioned General Porcess Unit comprises the command memory, the chip external memory control that are connected in PLB1 busDevice interface processed, is connected to data storage, bridger in PLB0 bus, and is connected to OPB busOn fixed, the real-time clock of house dog, timer, serial line interface and universal input/output interface; Described OPBBetween bus and PLB0 bus, connect by bridger.
Above-mentioned PLB0, PLB1 bus adopt 128 bit data width; OPB bus adopts 64 or 32Bit data width.
Above-mentioned HPI comprises the PCIe link, a PCIeIP and the DMA that connect successivelyAnd the 2nd PCIe link, the 2nd PCIeIP and the 2nd DMA that connect successively, a described DMA and theTwo DMA are connected with ASM protocol processor respectively.
The serial line interface of an above-mentioned PCIe link and the 2nd PCIe link all adopts 4 line interfaces backward compatible1 line interface.
An above-mentioned PCIeIP and the 2nd PCIeIP all adopt the PCIeIP with PCIe agreement 1.3 compatibilitiesCore.
An above-mentioned DMA and the 2nd DMA all adopt DMA passage.
Above-mentioned ASM protocol processes interface comprises: successively connect a FC-AE-ASM protocol process module,The one SerDes and a FC link and the 2nd FC-AE-ASM protocol processor module, the 2nd SerDesWith the 2nd FC link, a described DMA is connected with a FC-AE-ASM protocol process module, and describedTwo DMA are connected with the 2nd FC-AE-ASM protocol processor module.
Above-mentioned processor type is PowerPC460 or PowerPC470.
Above-mentioned processor and General Porcess Unit adopt CoreConnect bus interconnected.
The utility model is in order to solve under multiprocessor applied environment, the processor with PCIe interface and FC netThe mutual problem of data efficient between network, to improve the performance of airborne circumstance FC network data processing, proposesA two-way FC circuit structure for PCIe interface, inside circuit comprises flush bonding processor, general procedure listUnit, multi-host interface, many ASM protocol processes interface can be realized two-way FC-AE-ASM protocol data simultaneouslyParsing and processing, under the application scenarios of multiprocessor, building airborne FC network application environment providesEnsure.
Brief description of the drawings:
Fig. 1 is circuit structure diagram of the present utility model.
Detailed description of the invention:
Referring to Fig. 1, the two-way FC circuit of a kind of PCIe interface that the utility model provides, chip internal bagContaining processor 1, cross switch module 2, General Porcess Unit 3, HPI 4, and ASM agreement placeReason device 5.
Wherein, processor 1 is connected by bi-directional data DMA passage with cross switch module 2, cross bar switchModule 2 is connected by two-way PLB0, PLB1 bus and General Porcess Unit 3; Cross switch module 2By two-way PLB0 bus and HPI 4, and ASM protocol processor 5 connects, HPI 4Be connected with ASM protocol processor 5 with control interface by two-way bus.
When processor 1 write operation, processor 1 is sent out write command to cross switch module 2 by DMA passage, hands overFork switch module 2, according to the decoding of write address, uses two-way PLB0 and PLB1 interface, realizes generalIn processing unit 3, configuration is write in the initialization of ancillary equipment, HPI 4, ASM protocol processor 5 interfaces;When processor 1 read operation, processor 1 is sent out and is read instruction to cross switch module 2 by DMA passage, intersectsSwitch module 2, according to the decoding of reading address, uses two-way PLB0 and PLB1 interface, obtains general procedureThe status information of ancillary equipment, HPI 4, ASM protocol processor 5 interfaces in unit 3; ProcessingAfter the configuration operation of device 1 completes, HPI 4 and ASM protocol processor 5 are by two-way data/address busRealize the mutual of high band wide data between PCIe interface, PCIe interface and ASM protocol processor.
Processor 1 sends out write command by DMA passage or cross switch module 2, cross bar switch mould are arrived in read operationPiece 2, according to the decoding of write address, uses two-way PLB0 and PLB1 interface, realizes General Porcess UnitIn 3, configuration or status information are write in the initialization of ancillary equipment, HPI 4, ASM protocol processor 5 interfaces,After configuration operation completes, HPI 4 and ASM protocol processor 5 are realized by two-way data/address busHigh band wide data between PCIe interface, PCIe interface and ASM protocol processor mutual. This practicality is newThe two-way FC circuit structure of the PCIe interface that type provides, can solve subsidiary high-performance processor, general placeThe FC-AE-ASM protocol processes of reason unit, two-way PCIe HPI, two-way ASM protocol processes interfaceThe problem of circuit design, provides safeguard for building the airborne FC network platform.
The type of processor 1 can be PowerPC460, PowerPC470 and similar processor; This processingDevice running frequency can be selected; Selection mode is that the outer pin wire jumper of sheet is selected and software configuration is selected.
General Porcess Unit 3 comprises, is connected to command memory 301, chip external memory in PLB1 busControl unit interface 302, is connected to data storage 307, bridger 308 in PLB0 bus, Yi JilianBe connected on that house dog in OPB bus is fixed 303, real-time clock 304, timer 305, serial line interface 306,With universal input/output interface 309.
When powering on for the treatment of device, enters from the memory of chip exterior wherein said chip external memory interface 302Row start-up routine loads, and after processor starts, the instruction that needs are carried out is left finger in by PLB1 busMake in memory 301, data to be processed need are left in data storage 307 by PLB0 bus.The processor peripheral of low speed, as house dog 303, real-time clock 304, timer 305, serial line interface306, and universal input/output interface 309 is articulated in OPB bus, between OPB bus and PLB0 busUse bridger 308 to connect, realize the data interaction of PLB0 and OPB.
With processing unit 3, can also comprise other similar functions modules, as: ethernet communication/debugging interface,IIC interface, SPI interface etc. Various device in General Porcess Unit 3, can according to communication data withAnd the requirement of transmission delay etc., can be articulated in PLB bus or OPB bus.
Processor and General Porcess Unit 3: adopt CoreConnect bus interconnected. PLB0, PLB1 are totalLine adopts 128 bit data width; OPB bus adopts 64 or 32 bit data width; PLB0 bus withBetween OPB bus, adopt bus bridge to realize.
HPI 4 adopts a PCIe link 401, a PCIeIP402, a DMA403, realThe data of existing first via PCIe HPI are to the bidirectional high-efficiency transmission of ASM protocol processor 5; Adopt theTwo PCIe links 404, the 2nd PCIeIP405, the 2nd DMA406, realize the second road PCIe HPIData to the bidirectional high-efficiency transmission of ASM protocol processor 5; The priority of DMA adopts fifo queueMode manage.
The serial line interface of the one PCIe link 401, the 2nd PCIe link 404 is 4 lines, backward compatible 1Line.
ASM protocol processes interface 5 adopts a FC-AE-ASM protocol process module 501 and secondFC-AE-ASM protocol processor module 504, realizes FC-AE-ASM protocol analysis and processing; Adopt firstThe analog circuit of SerDes502, the 2nd SerDes505 is realized high speed serial parallel exchange circuit, adopts numeral electricity8B/10B codec functions is realized on road, and simulation adopts self defined interface with digital interface; The one FC link 503,Wire rate 1.0625Gbps, the 2.125Gbps of the 2nd FC link 504, can select.
Claims (10)
1. a two-way FC circuit structure for PCIe interface, is characterized in that: this circuit comprises processor, cross switch module, General Porcess Unit, HPI and ASM protocol processor; Described processor is connected by bi-directional data DMA passage with cross switch module, and described cross switch module is connected with General Porcess Unit by two-way PLB0, PLB1 bus; Cross switch module is connected with HPI and ASM protocol processor by two-way PLB0 bus, and HPI is connected with ASM protocol processor with control interface by two-way bus.
2. the two-way FC circuit structure of PCIe interface according to claim 1, it is characterized in that: described General Porcess Unit comprises the command memory, the chip external memory control unit interface that are connected in PLB1 bus, be connected to data storage, bridger in PLB0 bus, and be connected to that house dog in OPB bus is fixed, real-time clock, timer, serial line interface and universal input/output interface; Between described OPB bus and PLB0 bus, connect by bridger.
3. the two-way FC circuit structure of PCIe interface according to claim 2, is characterized in that: described PLB0, PLB1 bus adopt 128 bit data width; OPB bus adopts 64 or 32 bit data width.
4. the two-way FC circuit structure of PCIe interface according to claim 2, it is characterized in that: described HPI comprises a PCIe link, a PCIeIP and the DMA and the 2nd PCIe link being connected successively, the 2nd PCIeIP and the 2nd DMA that connect successively, and a described DMA is connected with ASM protocol processor respectively with the 2nd DMA.
5. the two-way FC circuit structure of PCIe interface according to claim 4, is characterized in that: the serial line interface of a described PCIe link and the 2nd PCIe link all adopts backward compatible 1 line interface of 4 line interfaces.
6. the two-way FC circuit structure of PCIe interface according to claim 4, is characterized in that: a described PCIeIP and the 2nd PCIeIP all adopt the PCIeIP core with PCIe agreement 1.3 compatibilities.
7. the two-way FC circuit structure of PCIe interface according to claim 4, is characterized in that: a described DMA and the 2nd DMA all adopt DMA passage.
8. the two-way FC circuit structure of PCIe interface according to claim 4, it is characterized in that: described ASM protocol processes interface comprises: a FC-AE-ASM protocol process module, a SerDes and the FC link and the 2nd FC-AE-ASM protocol processor module, the 2nd SerDes and the 2nd FC link that connect successively, a described DMA is connected with a FC-AE-ASM protocol process module, and described the 2nd DMA is connected with the 2nd FC-AE-ASM protocol processor module.
9. according to the two-way FC circuit structure of the PCIe interface described in the arbitrary claim of claim 1 to 8, it is characterized in that, described processor type is PowerPC460 or PowerPC470.
10. the two-way FC circuit structure of PCIe interface according to claim 9, is characterized in that: described processor and General Porcess Unit adopt CoreConnect bus interconnected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521037490.9U CN205263807U (en) | 2015-12-11 | 2015-12-11 | Double - circuit FC circuit structure of PCIe interface |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521037490.9U CN205263807U (en) | 2015-12-11 | 2015-12-11 | Double - circuit FC circuit structure of PCIe interface |
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| CN205263807U true CN205263807U (en) | 2016-05-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108614800A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AE-ASM protocol processing chip circuit structures |
| CN109839886A (en) * | 2017-11-27 | 2019-06-04 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of multibus reconfigurable processor chip circuit |
| CN110012369A (en) * | 2019-04-12 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of FC sonet card |
-
2015
- 2015-12-11 CN CN201521037490.9U patent/CN205263807U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108614800A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AE-ASM protocol processing chip circuit structures |
| CN109839886A (en) * | 2017-11-27 | 2019-06-04 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of multibus reconfigurable processor chip circuit |
| CN110012369A (en) * | 2019-04-12 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of FC sonet card |
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| C14 | Grant of patent or utility model | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20221013 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No. 15, Jinye Second Road, Xi'an, Shaanxi 710065 Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |
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| TR01 | Transfer of patent right |