CN110287141A - A kind of FPGA reconstructing method and system based on multiple interfaces - Google Patents
A kind of FPGA reconstructing method and system based on multiple interfaces Download PDFInfo
- Publication number
- CN110287141A CN110287141A CN201910564666.2A CN201910564666A CN110287141A CN 110287141 A CN110287141 A CN 110287141A CN 201910564666 A CN201910564666 A CN 201910564666A CN 110287141 A CN110287141 A CN 110287141A
- Authority
- CN
- China
- Prior art keywords
- data
- dynamic
- transceiver module
- module
- static
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a kind of FPGA reconstructing method and system based on multiple interfaces, this method comprises: FPGA is divided into static zones and dynamic area, static zones and dynamic area can carry out static reconfiguration, and dynamic area can also carry out dynamic restructuring；Static zones include: PCIE core, kilomega network transceiver module and can bus transceiver module；PCIE core, kilomega network transceiver module and can bus transceiver module receive input data respectively；The dynamic configuration file through PCIE core and kilomega network transceiver module is extracted respectively, is configured to dynamic area；The global static configuration data through PCIE core, kilomega network transceiver module and can bus transceiver module is extracted respectively, FLASH is written, and static zones obtain global static configuration data one by one；General data through PCIE core, kilomega network transceiver module and can bus transceiver module passes to dynamic area.The present invention solves the problems, such as that loading method is single in existing reconstruct mode, greatly increases the flexibility of system reconfiguration.
Description
Technical field
The present invention relates to electronic technology fields, and in particular to a kind of FPGA reconstructing method and system based on multiple interfaces.
Background technique
Due to the demand that digital logic system function complicates, the chip of monolithic system is just towards ultra-large, high density
Direction develop.But each functional module in system is not all to work at the moment, but according to the entirety of exterior
It is required that being activated or working in turn or cyclically.Also, with the expansion of Digital Logic scale, under identical velocity conditions,
The average service rate in regular hour section, functional module will decline.Therefore, system design should pursue big rule from tradition
Mould, highdensity direction turn to how to improve resource utilization, are realized in more massive logical design with limited resource
Come.And Reconfigurable Computing Technology can be improved the utilization rate of hardware and provide the programmability of software, the development for becoming following becomes
Gesture.Computer by local bus configure FPGA be known as locally reconstructing, pass through remote interface access FPGA and complete configuration be known as
Remote reconstruction.It repeats to configure and be divided into static reconfiguration and dynamic restructuring according to whether online.Static reconfiguration refers to goal systems
Logic function (including circuit function and circuit logic) static overload, can only configure before operation.Dynamic restructuring refers to target system
The logic function (including circuit function and circuit logic) of system can configure in real time in the process of running.Current static reconfiguration mode
Program downloading generally is carried out using the dedicated pin of specific download device connection FPGA, dynamic restructuring mode is connected with specific download device
FPGA is loaded using local PCIE bus, and such loading method is single, not flexible, therefore is found and a kind of can be based on a variety of connect
The FPGA reconstructing method and system of mouth are particularly important.
Summary of the invention
The purpose of the present invention is to provide a kind of FPGA reconstructing method and system based on multiplex roles is existing heavy for solving
The single problem of loading method in structure mode.
A kind of FPGA reconstructing method based on multiplex roles of the invention, including FPGA is divided into static zones and dynamic area,
Static zones and dynamic area can carry out static reconfiguration, and dynamic area can also carry out dynamic restructuring；Static zones include: PCIE core,
Kilomega network transceiver module and can bus transceiver module；PCIE core and switch carry out data interaction, judge the transmission of PCIE core
Dynamic configuration file is passed to dlm (dynamic loading module) by the type of data, other data pass to dma controller；PCIE core, thousand
Million net transceiver modules and can bus transceiver module receive input data respectively, and the input data includes dynamic configuration file, complete
Office's static configuration data and general data；The dynamic configuration file through switch and kilomega network transceiver module is extracted respectively, and is matched
Set dynamic area；The global static configuration through dma controller, kilomega network transceiver module and can bus transceiver module is extracted respectively
Data, are written FLASH, and static zones obtain global static configuration data one by one；Through dma controller, kilomega network transceiver module and can
The general data of bus transceiver module passes to dynamic area.
One embodiment of the FPGA reconstructing method according to the present invention based on multiple interfaces, wherein will be gone here and there by PCIE core
Row data are converted to 64 bit parallel datas.
A kind of FPGA reconfiguration system based on multiplex roles of the invention, comprising: PCIE core, kilomega network transceiver module, can are total
Line transceiver module, switch, dma controller, dlm (dynamic loading module), ICAP, FLASH module for reading and writing and user logic module；
PCIE consideration convey changes the transmission data of host computer, passes to switch；Ethernet UDP message of the kilomega network transceiver module to host computer
It unpacks；Can bus transceiver module extracts host computer data packet by can bus protocol, and global static configuration data is sent
FLASH module for reading and writing, general data send user logic module；Switch judges the type of the data of PCIE core transmission, will move
State configuration file passes to dlm (dynamic loading module), other data pass to dma controller；Dma controller, to the data group received
Packet and unpacking, judge data type, and the transmitting of global static configuration data is sent to FLASH module for reading and writing, other data are sent out
It is sent to user logic module；Dlm (dynamic loading module) is connected with switch and kilomega network transceiver module, extracts in the data packet received
Dynamic configuration file, and control ICAP, dlm (dynamic loading module) is by control ICAP by dynamic configuration file configuration to dynamic area
Complete dynamic restructuring；FLASH is written in global static configuration data by FLASH module for reading and writing.
One embodiment of the FPGA reconfiguration system of multiple interfaces according to the present invention, wherein PCIE core turns serial data
It is changed to 64 bit parallel datas and passes to switch.
The present invention can realize the static reconfiguration and dynamic restructuring of FPGA based on multiple interfaces, and loading method is more flexible more
Sample.
Detailed description of the invention
Fig. 1 is a kind of block diagram of the FPGA reconfiguration system of multiplex roles of the invention.
Specific embodiment
To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention
Specific embodiment is described in further detail.
Fig. 1 is a kind of block diagram of the FPGA reconfiguration system of multiplex roles of the invention, as shown in Figure 1, one kind of the invention is more
The FPGA reconfiguration system of interface includes: PCIE core 2, kilomega network transceiver module 14, can bus transceiver module 13, switch 3, DMA
Controller 4, dlm (dynamic loading module) 5, ICAP6, FLASH module for reading and writing 7, user logic module 12.FPGA11 can also be divided simultaneously
For static zones and dynamic area, static zones and dynamic area can carry out static reconfiguration, and dynamic area can carry out dynamic restructuring.It is static
Area includes: PCIE core 2, switch 3, dma controller 4, dlm (dynamic loading module) 5, ICAP6, FLASH module for reading and writing 7, kilomega network receipts
Send out module 14, can bus transceiver module 13；Dynamic area includes: user logic module 12.
As shown in Figure 1, the Local or Remote of FPGA can be realized by three kinds of PCIE, kilomega network, can bus interface flexibles
Static and dynamic restructuring.Each component of the system, connection relationship and function are as follows: PCIE core 2 is used to convert the transmission of host computer 1
Data connect switch 3；The unpacking of kilomega network transceiver module completion Ethernet UDP message, connection dlm (dynamic loading module) 5,
FLASH module for reading and writing 7 and user logic module 12；Can bus transceiver module 13 completes the processing of can bus protocol and extracts data
Packet connects FLASH module for reading and writing 7 and user logic module 12；Switch 3 judges data type, connects 5 He of dlm (dynamic loading module)
Dma controller 4；Group packet and unpacking of the dma controller 4 for PCIE interface data judge data type, connection FLASH read-write
Module 7 and user logic module 12；Dlm (dynamic loading module) 5 controls ICAP6；FLASH module for reading and writing 7 writes data into FLASH8.
As shown in Figure 1, further explaining a kind of course of work of the FPGA reconfiguration system of multiplex roles of the invention.It is upper
1 data of machine pass through PCIE interface, and it is total that kilomega network and CAN bus are delivered separately to PCIE core 2, kilomega network transceiver module 14 and can
Line transceiver module 13, wherein host computer input data includes dynamic configuration file, global static configuration data and general data.
PCIE core 2 completes the management control of PCIE physical link, passes to switch 3 after data conversion.Switch 3 judges
Data type is then sent to dlm (dynamic loading module) 5 if it is dynamic restructuring configuration file, and dlm (dynamic loading module) 5 extracts data packet
In dynamic configuration file, and pass to ICAP6, ICAP6 is the IP kernel for carrying out FPGA configuration, and dlm (dynamic loading module) 5 passes through control
It makes the IP kernel and dynamic configuration file configuration to dynamic area 10 is completed into dynamic restructuring；DMA control is then passed to if it is other data
Device 4 processed, dma controller 4 complete PCIE interface data group packet and unpacking, and judge data be global static configuration data or
General data then passes to FLASH module for reading and writing 7 if it is global static configuration data and FLASH8 is written, and static zones are obtained one by one
It takes the global static configuration data in FLASH8 to complete static reconfiguration, user logic module is then sent to if it is general data
12, realize the communication of host computer 1 and user logic module 12.
In some alternative embodiments, PCIE core 2 converts serial data into 64 bit parallel datas.
As shown in Figure 1, kilomega network transceiver module 14 completes management control and the Ethernet UDP of gigabit Ethernet PHY chip
The unpacking of data is divided into three kinds of situations according to data type: if it is dynamic restructuring configuration file, being then sent to dynamically load mould
Block 5, dlm (dynamic loading module) 5 extracts the dynamic configuration file in data packet, and passes to ICAP6 module, and ICAP6 module is to carry out
By controlling the IP kernel completion dynamic of dynamic area 10 is written in dynamic configuration file by the IP kernel of FPGA configuration, dlm (dynamic loading module) 5
Reconstruct；FLASH module for reading and writing 7 then being passed to if it is global static configuration data, FLASH8 being written, static zones obtain one by one
Global static configuration data in FLASH8 completes static reconfiguration；User logic module 12 is then sent to if it is general data,
Realize the communication of host computer 1 and user logic module 12.
As shown in Figure 1, can bus transceiver module 13 completes the processing of can bus protocol, data packet is extracted, according to data class
Type is divided into two kinds of situations: then passing to FLASH module for reading and writing 7 if it is global static configuration data and FLASH8, static zones are written
The global static configuration data obtained in FLASH8 one by one completes static reconfiguration；User logic is then sent to if it is general data
Module 12 realizes the communication of host computer 1 and user logic module 12.
In some alternative embodiments, the PCIE core 2 converts serial data into 64 bit parallel datas.
The invention also includes a kind of FPGA reconstructing method based on multiplex roles, including FPGA is divided into static zones and dynamic
Area, static zones and dynamic area can carry out static reconfiguration, and dynamic area can also carry out dynamic restructuring；Static zones include: PCIE
Core, kilomega network transceiver module and can bus transceiver module；PCIE core and switch carry out data interaction, judge that PCIE core passes
Dynamic configuration file is passed to dlm (dynamic loading module) by the type of defeated data, other data pass to dma controller；PCIE
Core, kilomega network transceiver module and can bus transceiver module receive input data respectively, and the input data includes dynamic configuration text
Part, global static configuration data and general data；The dynamic configuration file through switch and kilomega network transceiver module is extracted respectively,
And it is configured to dynamic area；It is static that the overall situation through dma controller, kilomega network transceiver module and can bus transceiver module is extracted respectively
Configuration data, is written FLASH, and static zones obtain global static configuration data one by one；Through dma controller, kilomega network transceiver module
Dynamic area is passed to the general data of can bus transceiver module.
In some alternative embodiments, the PCIE core 2 converts serial data into 64 bit parallel datas.
General reconfigurable system only has a kind of reconstruct interface, and PCIE, kilomega network, three kinds of can bus can be used in the present invention
Mode carries out static reconfiguration, while PCIE, kilomega network can be used to carry out dynamic local reconstruct, and can be with for the interface of reconstruct
With user logic module reuse, the flexibility of system reconfiguration is considerably increased under the premise of excessively not increasing resource consumption.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of FPGA reconstructing method based on multiple interfaces characterized by comprising
FPGA is divided into static zones and dynamic area, static zones and dynamic area can carry out static reconfiguration, and dynamic area can be with
Carry out dynamic restructuring；Static zones include: PCIE core, kilomega network transceiver module and can bus transceiver module；PCIE core and switching
Device carries out data interaction, judges the type of the data of PCIE core transmission, dynamic configuration file is passed to dlm (dynamic loading module),
He passes to dma controller at data；
PCIE core, kilomega network transceiver module and can bus transceiver module receive input data respectively, and the input data includes dynamic
State configuration file, global static configuration data and general data；
The dynamic configuration file through switch and kilomega network transceiver module is extracted respectively, and is configured to dynamic area；
The global static configuration data through dma controller, kilomega network transceiver module and can bus transceiver module is extracted respectively, is write
Enter FLASH, static zones obtain global static configuration data one by one；
General data through dma controller, kilomega network transceiver module and can bus transceiver module passes to dynamic area.
2. the FPGA reconstructing method according to claim 1 based on multiple interfaces, which is characterized in that will be gone here and there by PCIE core
Row data are converted to 64 bit parallel datas.
3. a kind of FPGA reconfiguration system based on multiple interfaces characterized by comprising PCIE core, kilomega network transceiver module,
Can bus transceiver module, switch, dma controller, dlm (dynamic loading module), ICAP, FLASH module for reading and writing and user logic
Module；
PCIE consideration convey changes the transmission data of host computer, passes to switch；
Kilomega network transceiver module unpacks the Ethernet UDP message of host computer；
Can bus transceiver module extracts host computer data packet by can bus protocol, and global static configuration data is sent
FLASH module for reading and writing, general data send user logic module；
Switch judges the type of the data of PCIE core transmission, and dynamic configuration file is passed to dlm (dynamic loading module), other numbers
According to passing to dma controller；
Dma controller judges data type to the data group packet received and unpacking, and global static configuration data is transmitted and is sent
FLASH module for reading and writing is given, sends user logic module for other data；
Dlm (dynamic loading module) is connected with switch and kilomega network transceiver module, extracts the dynamic configuration text in the data packet received
Part, and ICAP is controlled, dynamic configuration file configuration to dynamic area is completed dynamic restructuring by control ICAP by dlm (dynamic loading module)；
FLASH is written in global static configuration data by FLASH module for reading and writing.
4. the FPGA reconfiguration system according to claim 3 based on multiple interfaces, which is characterized in that the PCIE core will go here and there
Row data are converted to 64 bit parallel datas and pass to switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910564666.2A CN110287141B (en) | 2019-06-27 | 2019-06-27 | FPGA (field programmable Gate array) reconstruction method and system based on multiple interfaces |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910564666.2A CN110287141B (en) | 2019-06-27 | 2019-06-27 | FPGA (field programmable Gate array) reconstruction method and system based on multiple interfaces |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110287141A true CN110287141A (en) | 2019-09-27 |
| CN110287141B CN110287141B (en) | 2023-02-03 |
Family
ID=68007633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910564666.2A Active CN110287141B (en) | 2019-06-27 | 2019-06-27 | FPGA (field programmable Gate array) reconstruction method and system based on multiple interfaces |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110287141B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111274183A (en) * | 2020-02-21 | 2020-06-12 | 山东超越数控电子股份有限公司 | Multi-path high-speed protocol interface dynamic reconfigurable system and implementation method |
| CN112597096A (en) * | 2020-12-15 | 2021-04-02 | 中国科学院计算技术研究所 | Low-power-consumption FPGA (field programmable Gate array) partial reconfigurable method and device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9509604B1 (en) * | 2013-12-31 | 2016-11-29 | Sanmina Corporation | Method of configuring a system for flow based services for flash storage and associated information structure |
| CN108153705A (en) * | 2017-12-26 | 2018-06-12 | 北京航空航天大学 | A kind of efficient parallel acquisition method towards isomerous multi-source big data |
| CN108255755A (en) * | 2017-12-08 | 2018-07-06 | 天津津航计算技术研究所 | PCIE functional universal communication interface modules based on FPGA |
| CN108319563A (en) * | 2018-01-08 | 2018-07-24 | 华中科技大学 | A kind of network function acceleration method and system based on FPGA |
| CN108804232A (en) * | 2018-06-26 | 2018-11-13 | 郑州云海信息技术有限公司 | A kind of method, host server and the system of supporting high in the clouds FPGA to dispose |
| CN109739833A (en) * | 2018-12-18 | 2019-05-10 | 山东超越数控电子股份有限公司 | A kind of Domestic Platform database accelerator system and method based on FPGA |
| US20190171604A1 (en) * | 2017-10-31 | 2019-06-06 | Micron Technology, Inc. | System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network |
-
2019
- 2019-06-27 CN CN201910564666.2A patent/CN110287141B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9509604B1 (en) * | 2013-12-31 | 2016-11-29 | Sanmina Corporation | Method of configuring a system for flow based services for flash storage and associated information structure |
| US20190171604A1 (en) * | 2017-10-31 | 2019-06-06 | Micron Technology, Inc. | System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network |
| CN108255755A (en) * | 2017-12-08 | 2018-07-06 | 天津津航计算技术研究所 | PCIE functional universal communication interface modules based on FPGA |
| CN108153705A (en) * | 2017-12-26 | 2018-06-12 | 北京航空航天大学 | A kind of efficient parallel acquisition method towards isomerous multi-source big data |
| CN108319563A (en) * | 2018-01-08 | 2018-07-24 | 华中科技大学 | A kind of network function acceleration method and system based on FPGA |
| CN108804232A (en) * | 2018-06-26 | 2018-11-13 | 郑州云海信息技术有限公司 | A kind of method, host server and the system of supporting high in the clouds FPGA to dispose |
| CN109739833A (en) * | 2018-12-18 | 2019-05-10 | 山东超越数控电子股份有限公司 | A kind of Domestic Platform database accelerator system and method based on FPGA |
Non-Patent Citations (3)
| Title |
|---|
| DANIEL ZIENER 等: "FPGA-Based Dynamically Reconfigurable SQL Query Processing", 《ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS》 * |
| 李丽斯 等: "基于FPGA的PCIe总线DMA控制器的设计与验证", 《计算机测量与控制》 * |
| 马宁: "基于FPGA的可重构计算硬件平台设计与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111274183A (en) * | 2020-02-21 | 2020-06-12 | 山东超越数控电子股份有限公司 | Multi-path high-speed protocol interface dynamic reconfigurable system and implementation method |
| WO2021164170A1 (en) * | 2020-02-21 | 2021-08-26 | 山东超越数控电子股份有限公司 | Multi-path high-speed protocol interface dynamic reconfiguration system and implementation method therefor |
| CN112597096A (en) * | 2020-12-15 | 2021-04-02 | 中国科学院计算技术研究所 | Low-power-consumption FPGA (field programmable Gate array) partial reconfigurable method and device |
| CN112597096B (en) * | 2020-12-15 | 2023-11-21 | 中国科学院计算技术研究所 | Low-power consumption FPGA part reconfigurable method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110287141B (en) | 2023-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1750401B1 (en) | USB 1.1 over a high speed link | |
| TWI382315B (en) | Usb matrix switch system | |
| CN102281254B (en) | Design system and method of server serial port | |
| CN108595353A (en) | A kind of method and device of the control data transmission based on PCIe buses | |
| CN202870808U (en) | FPGA realization device of SPI serial port module | |
| CN102495920B (en) | Integrated logic analysis module based on PCIe (peripheral component interconnection express) for FPGA (field programmable gate array) | |
| CN101957808B (en) | Communication method among various CPUs (Central Processing Units), system and CPU | |
| CN106155960A (en) | Shake hands and the UART serial port communication method of EDMA based on GPIO | |
| CN103559152A (en) | Device and method for CPU (central processing unit) to access local bus on basis of PCIE (peripheral component interface express) protocol | |
| KR101679333B1 (en) | Method, apparatus and system for single-ended communication of transaction layer packets | |
| CN107562672A (en) | A kind of system and method for improving vector network analyzer message transmission rate | |
| CN109298839A (en) | Storage controller, storage device, system and method based on PIS | |
| CN110287141A (en) | A kind of FPGA reconstructing method and system based on multiple interfaces | |
| CN101169770A (en) | CPU interface conversion system | |
| CN110557311A (en) | Inter-processor communication method for inter-die access latency in system-in-package | |
| CN109634901A (en) | A kind of data transmission system and its control method based on UART | |
| CN107436851A (en) | The line shielding system of Serial Peripheral Interface (SPI) four and its control method | |
| CN105718396B (en) | A kind of I of big data master transmissions2C bus units and its means of communication | |
| CN101122894A (en) | Asynchronous serial communication control device | |
| CN112817774B (en) | System and method for transaction broadcasting in a network on chip | |
| CN105607874A (en) | SATA (Serial advanced technology attachment) protocol acceleration module, host and hard disk communication method, as well as solid state drive controller | |
| CN103678244B (en) | A kind of smart machine without using application processor | |
| JP2003050788A (en) | Apparatus and method for distribution of signal from high level data link controller to multiple digital signal processor core | |
| CN205263807U (en) | Double - circuit FC circuit structure of PCIe interface | |
| CN209560543U (en) | Big data operation chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |