CN205212816U - Modified anticoincidence gate logic unit circuit - Google Patents
Modified anticoincidence gate logic unit circuit Download PDFInfo
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- CN205212816U CN205212816U CN201521037610.5U CN201521037610U CN205212816U CN 205212816 U CN205212816 U CN 205212816U CN 201521037610 U CN201521037610 U CN 201521037610U CN 205212816 U CN205212816 U CN 205212816U
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Abstract
The utility model discloses a modified anticoincidence gate logic unit circuit constitutes first order circuit by PMOS transistor P1, P2 and NMOS transistor N1, N2, PMOS transistor P3, P4, P5 and NMOS transistor N3, N4, N5 constitute second level circuit. In the first order circuit, PMOS transistor P1 and PMOS transistor P2 establish ties, and NMOS transistor N1 and NMOS transistor N2 are parallelly connected. In the circuit of the second level, PMOS transistor P3 and PMOS transistor P4 are parallelly connected, then establish ties with PMOS transistor P5, NMOS transistor N3 and NMOS transistor N4 establish ties, then parallelly connected with NMOS transistor N5. The utility model discloses the transistor quantity of using is 10, lacks 2 transistors than traditional anticoincidence gate logic unit circuit, has realized the exjunction logic having reduced the area through less transistor, has reduced the consumption.
Description
Art
The utility model relates to technical field of integrated circuits, relates to a kind of XOR gate logic unit circuit of improvement more specifically.
Background technology
Constantly reduce the fast development with designing technique along with integrated circuit technology size, integrated circuit towards more on a large scale, more complicated trend development, power consumption has become one of severe challenge that integrated circuit development faces.This seems particularly important in Mobile solution field.And in order to ensure information security, being encrypted decrypt operation to data is absolutely necessary, this wherein often can use a large amount of XOR gate logical blocks.
Traditional XOR gate logical block forms primarily of 12 transistors, comprises 6 PMOS transistor and 6 nmos pass transistors, as shown in Figure 1.This NOR gate circuit is a kind of mirror-image structure, is all the circuit structure of main flow for a long time.But along with the raising with operating frequency of reducing of circuit technology size, it is more that it also exists number of tubes, the problem that power consumption is larger.
Utility model content
Technical problem to be solved in the utility model is that to overcome the number of tubes that above-mentioned traditional XOR gate unit exists more, and the problem that power consumption is larger, provides a kind of XOR gate logic unit circuit structure of improvement, the effective power problems solving circuit.
The technical scheme in the invention for solving the above technical problem is: the quantity reducing transistor, adopts two-stage circuit to connect and forms NOR gate circuit unit.
The utility model is achieved through the following technical solutions: a kind of XOR gate logic unit circuit of improvement, forms first order circuit by PMOS transistor P1, P2 and nmos pass transistor N1, N2;
PMOS transistor P3, P4, P5 and nmos pass transistor N3, N4, N5 form second level circuit.
In first order circuit, PMOS transistor P1 and PMOS transistor P2 series connection, nmos pass transistor N1 and nmos pass transistor N2 is in parallel.Wherein, the source class of P1 connects power vd D, and grid connects input signal A, the source class short circuit of drain electrode and P2; The grid of P2 connects input signal B, the drain electrode short circuit of drain electrode and N1 and N2; The grid of N1 connects input signal A, and the grid of N2 connects input signal B, and the source class of N1 with N2 is connected power supply ground VSS jointly.
In the circuit of the second level, PMOS transistor P3 and PMOS transistor P4 is in parallel, then connects with PMOS transistor P5; Nmos pass transistor N3 and nmos pass transistor N4 connects, then in parallel with nmos pass transistor N5.Wherein, the source class of P5 connects power vd D, the source class short circuit of drain electrode and P3 and P4, and the grid of grid and N5 is connected to the drain electrode of P2 jointly; The grid of P3 connects input signal A, and the grid of P4 connects input signal B, and the grid of N3 connects input signal A, and the grid of N4 connects input signal B; The source class of N3 and the drain electrode short circuit of N4, the source class of N4 with N5 is jointly connected the power supply ground drain electrode of VSS, N3 and N5 and the drain electrode of P3 and P4 is shorted together, and draws circuit output signal Z.
Therefore, the number of transistors that the utility model uses is 10,2 transistors fewer than traditional XOR gate logic unit circuit.
The beneficial effects of the utility model are the use of less transistor and achieve XOR logic, reduce area, reduce power consumption.
Accompanying drawing explanation
Fig. 1 is traditional NOR gate circuit figure.
Fig. 2 is the XOR gate logic unit circuit figure that the utility model improves.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further illustrated.
The utility model provides a kind of XOR gate logic unit circuit of improvement, adopts two-stage circuit to connect, achieves XOR.First order circuit is made up of PMOS transistor P1, P2 and nmos pass transistor N1, N2, and second level circuit is made up of PMOS transistor P3, P4, P5 and nmos pass transistor N3, N4, N5.
In first order circuit, PMOS transistor P1 and PMOS transistor P2 series connection, nmos pass transistor N1 and nmos pass transistor N2 is in parallel.Wherein, the source class of P1 connects power vd D, and grid connects input signal A, the source class short circuit of drain electrode and P2; The grid of P2 connects input signal B, the drain electrode short circuit of drain electrode and N1 and N2; The grid of N1 connects input signal A, and the grid of N2 connects input signal B, and the source class of N1 with N2 is connected power supply ground GND jointly.In fact, this first order circuit is exactly a typical OR-NOT circuit unit.
In the circuit of the second level, PMOS transistor P3 and PMOS transistor P4 is in parallel, then connects with PMOS transistor P5; Nmos pass transistor N3 and nmos pass transistor N4 connects, then in parallel with nmos pass transistor N5.Wherein, the source class of P5 connects power vd D, the source class short circuit of drain electrode and P3 and P4, and the grid of grid and N5 is connected to the drain electrode of P2 jointly; The grid of P3 connects input signal A, and the grid of P4 connects input signal B, and the grid of N3 connects input signal A, and the grid of N4 connects input signal B; The source class of N3 and the drain electrode short circuit of N4, the source class of N4 with N5 is jointly connected the power supply ground drain electrode of GND, N3 and N5 and the drain electrode of P3 and P4 is shorted together, and draws circuit output signal Z.In fact, this second level circuit is exactly a typical andorinverter unit.
When input signal A and input signal B is logical zero, the equal conducting of P1 and P2, N1 and N2 all ends, and first order circuit exports as high level, P5 is ended, N5 conducting.So it is low level that the drain electrode of N5 just exports, and namely outputing signal Z is 0.
When input signal A and input signal B is logical one, P1 and P2 all ends, the equal conducting of N1 and N2, and first order circuit exports as low level, makes P5 conducting, and N5 ends.And the equal conducting of N3 and N4, so it is low level that the drain electrode of N3 just exports, namely outputing signal Z is 0.
When input signal A is logical zero, when input signal B is logical one, N2 conducting, the drain electrode output of N2 and first order circuit export as low level, make P5 conducting, and N5 ends, and P3 now also conducting, like this, it is high level that the drain electrode of P3 just exports, and namely outputing signal Z is 1.
When input signal A is logical one, when input signal B is logical zero, N1 conducting, the drain electrode output of N1 and first order circuit export as low level, make P5 conducting, and N5 ends, and P4 now also conducting, like this, it is high level that the drain electrode of P4 just exports, and namely outputing signal Z is 1.
Can reach a conclusion from upper surface analysis, be exactly when input signal A is identical with the logic level of input signal B, and output signal Z is 0; And when input signal A is not identical with the logic level of input signal B, output signal Z is 1.Therefore, circuit realiration XOR function.
The NOR gate circuit improved is compared to traditional NOR gate circuit, and because number of tubes decreases 2, the current drain of pipe reduces, and the comprehensive power consumption of circuit also just reduces.
Claims (3)
1. the XOR gate logic unit circuit improved, is characterized in that, carry out built-up circuit unit by two-stage circuit, comprise first order circuit and second level circuit; The output of described first order circuit connects the input of second level circuit;
In described first order circuit, PMOS transistor P1 and PMOS transistor P2 series connection, nmos pass transistor N1 and nmos pass transistor N2 is in parallel;
In the circuit of the described second level, PMOS transistor P3 and PMOS transistor P4 is in parallel, then connects with PMOS transistor P5; Nmos pass transistor N3 and nmos pass transistor N4 connects, then in parallel with nmos pass transistor N5.
2. the XOR gate logic unit circuit of improvement according to claim 1, is characterized in that: in described first order circuit, and the source class of P1 connects power vd D, and grid connects input signal A, the source class short circuit of drain electrode and P2; The grid of P2 connects input signal B, the drain electrode short circuit of drain electrode and N1 and N2; The grid of N1 connects input signal A, and the grid of N2 connects input signal B, and the source class of N1 with N2 is connected power supply ground VSS jointly.
3. the XOR gate logic unit circuit of improvement according to claim 1, is characterized in that; In the circuit of the described second level, the source class of P5 connects power vd D, the source class short circuit of drain electrode and P3 and P4, and the grid of grid and N5 is connected to the drain electrode of P2 jointly; The grid of P3 connects input signal A, and the grid of P4 connects input signal B, and the grid of N3 connects input signal A, and the grid of N4 connects input signal B; The source class of N3 and the drain electrode short circuit of N4, the source class of N4 with N5 is jointly connected the power supply ground drain electrode of VSS, N3 and N5 and the drain electrode of P3 and P4 is shorted together, and draws circuit output signal Z.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521037610.5U CN205212816U (en) | 2015-12-14 | 2015-12-14 | Modified anticoincidence gate logic unit circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521037610.5U CN205212816U (en) | 2015-12-14 | 2015-12-14 | Modified anticoincidence gate logic unit circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112636736A (en) * | 2019-10-09 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | Logic circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112636736A (en) * | 2019-10-09 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | Logic circuit |
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