CN106411303A - Anti-creeping MOS switch structure applicable to integrated circuit - Google Patents
Anti-creeping MOS switch structure applicable to integrated circuit Download PDFInfo
- Publication number
- CN106411303A CN106411303A CN201610825179.3A CN201610825179A CN106411303A CN 106411303 A CN106411303 A CN 106411303A CN 201610825179 A CN201610825179 A CN 201610825179A CN 106411303 A CN106411303 A CN 106411303A
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- CN
- China
- Prior art keywords
- nmos tube
- pmos
- drain electrode
- connects
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
Abstract
The invention discloses an anti-creeping MOS switch structure applicable to an integrated circuit, which comprises a PMOS tube MP1, two NMOS tubes MN4 and MN5, and a single-ended output operational amplifier AMP1. Namely, on the basis of a serial NMOS switch, the operational amplifier AMP1 is added so as to implement source and drain voltage following control on the NMOS switch. The operational amplifier AMP1 is switched into a circuit when the NMOS switch is turned off, so that source and drain voltages can be guaranteed to be still kept equal when an NMOS switch tube is in a turn-off state, and the NMOS switch is prevented from generating a leakage current; the operational amplifier is disconnected from the circuit when the NMOS switch is turned on so as not to generate influence on switching performance. The used operational amplifier is implemented by adopting a simple five-tube operational amplification structure, the structure is simple, and an occupied area and power consumption are very small. By the switch structure disclosed by the invention, variation of a node voltage, which is caused by the leakage current of the MOS switch, can be obvious reduced, and effective protection on a key node is implemented.
Description
Technical field
The present invention relates to field of analog integrated circuit, can be used in digital and analog mixed signal circuit particularly to a kind of
Anticreep MOS switch structure.
Background technology
The fast development of semiconductor technology gives people life and brings great variety, and high-tech electronic products application is in life
Various aspects, including market supermarket, hotels and restaurants, railway station, airport etc., facilitate the clothing, food, lodging and transportion -- basic necessities of life of people, improve
People live.Wherein, CMOS technology, due to its low cost, technical maturity, is main a kind of technique in semiconductor industry
Technology.
In recent years, before Moore's Law inefficacy, CMOS technology critical size reduces year by year, micro- to 0.18 from 0.8 micron
Rice, 14 nanometers even more little.Reduce with CMOS critical size, incident is metal-oxide-semiconductor operating voltage and grid voltage reduces, with
Metal-oxide-semiconductor gate oxide thickness and channel length are also reducing simultaneously for this.In deep-submicron or nanometer-grade IC, electric leakage
Phenomenon is more and more significant, has both included the electric leakage leading to after metal-oxide-semiconductor grid oxic horizon is thinning, has also included between metal-oxide-semiconductor source and drain
Sub-threshold leakage.
In digital integrated electronic circuit, leakage current can lead to the notable power consumption of circuit to increase, and can lead to logic error when serious.
In simulation and composite signal integrated circuits field, leakage current can lead to the voltage of key node to produce change so that originally should
There is the current path over the ground or to power supply in the node of this charge conservation, cause the change of electric charge, leads to voltage signal to produce by mistake
Difference.Therefore, it is necessary to reduce the error that electric leakage leads to using particular design on the key node need special protection.
Content of the invention
In order to solve the error that above-mentioned electrical leakage problems lead to, the present invention proposes a kind of leakproof be applied to integrated circuit
Electric MOS switch structure, including the operational amplifier of PMOS MP1, NMOS tube MN4 and NMOS tube MN5 and a Single-end output
AMP1；Described NMOS tube MN4 and NMOS tube MN5 are the MOS switch on signal transmission pathway, and described PMOS MP1 is to control institute
State the switch of Single-end output operational amplifier A MP1 output feedback signal；The source electrode of described NMOS tube MN4 connects input signal, institute
The drain electrode stating NMOS tube MN4 is simultaneously connected with the source electrode of NMOS tube MN5 and the source electrode of PMOS MP1, when NMOS tube MN4 grid connects
Clock signal CLK；The drain electrode of NMOS tube MN5 connects the normal phase input end of signal output part and described operational amplifier A MP1, NMOS
The grid of pipe MN5 connects clock signal clk；The source electrode of PMOS MP1 connects the drain electrode of NMOS tube MN4, the drain electrode of PMOS MP1
The output end of concatenation operation amplifier AMP, the grid of PMOS MP1 connects clock signal clk；The positive of operational amplifier A MP1
Input and signal output part connect, and the negative-phase input of operational amplifier A MP1 is connected with the output end of operational amplifier A MP1
Afterwards and connect to the drain electrode of PMOS MP1.
Wherein, described operational amplifier A MP1 adopts five pipe amplifier structures.
Described operational amplifier A MP1 includes 4 NMOS tube, 2 PMOS and 1 resistance R1；Wherein, 4 NMOS tube are divided
It is not denoted as NMOS tube NMOS6, NMOS tube NMOS7, NMOS tube NMOS8 and NMOS tube NMOS9,2 PMOS are denoted as PMOS respectively
Pipe MP2 and PMOS MP3；One end of resistance R1 connects power vd D, and the other end of resistance R1 connects the grid of NMOS tube MN6 simultaneously
And drain electrode；The source ground of NMOS tube MN6, the grid of NMOS tube MN6 and the drain electrode of NMOS tube MN6 are simultaneously connected to NMOS tube
The grid of MN7；The source ground of NMOS tube MN7, the drain electrode of NMOS tube MN7 is simultaneously connected with the source of NMOS tube MN8 and NMOS tube MN9
Pole；The grid of NMOS tube MN8 is amplifier normal phase input end, and the source electrode of NMOS tube MN8 connects the drain electrode of NMOS tube MN7, NMOS tube
The drain electrode of MN8 is simultaneously connected with the drain and gate of PMOS MP2；The grid of NMOS tube MN9 is amplifier negative-phase input, NMOS tube
The source electrode of MN9 connects the drain electrode of NMOS tube MN7, and the drain electrode of NMOS tube MN9 connects the drain electrode of PMOS MP3, the source of PMOS MP3
Pole connects power vd D, and the grid of PMOS MP3 connects the grid of PMOS MP2, and the drain electrode of PMOS MP3 is amplifier output end.
Compared with prior art, a kind of anticreep MOS switch structure be applied to integrated circuit proposed by the present invention is
On the basis of series connection nmos switch, increased operational amplifier and realize the source-drain voltage model- following control to nmos switch.Computing
Amplifier accesses circuit when nmos switch turns off it is ensured that nmos switch pipe remains in off state maintain source-drain voltage phase
Deng, prevent nmos switch produce leakage current；Operational amplifier is disconnected from the circuit when nmos switch turns on, will not be to switch
Performance produces impact.The operational amplifier using adopts simple five pipe amplifier structures to realize, and structure is simple, area occupied and power consumption
Very little.By construction of switch proposed by the present invention, can be substantially reduced and be become due to the node voltage that MOS switch leakage current leads to
Change, realize the effective protection to key node.
Brief description
Fig. 1 is traditional nmos switch schematic diagram；
Fig. 2 is leakproof electrically coupled in series nmos switch schematic diagram；
Fig. 3 is anticreeping switch schematic diagram proposed by the present invention；
Fig. 4 is operational amplifier A MP1 schematic diagram.
Specific embodiment
With reference to specific embodiment, the present invention is described in further detail.
Traditional nmos switch structure is as shown in figure 1, wherein NMOS tube MN1 conduct under the control of clock CLK switchs.When
When CLK is high level, MN1 turns on, switch conduction, and MN1 source-drain voltage is equal, and load C 1 is driven by signal source, VC=VA；When
When CLK is low level, MN1 ends, and switches off, and electric capacity C1 on the right side of MN1 keeps the voltage before MN1 cut-off constant.But it is real
On border, there is leakage current due between MN1 source and drain, ceaselessly electric capacity C1 is charged or discharges, through after a while
Voltage on electric capacity C1 can produce change, leads to produce error.
A kind of simple switch that improves is the electrically coupled in series nmos switch of leakproof as shown in Fig. 2 wherein NMOS tube MN2 and MN3 exists
As switch under the control of clock CLK.When CLK for high level is, MN2 and MN3 turns on, switch conduction, and electric capacity C2 is by signal source
Drive, tri- node voltages of VA, VB, VC are equal；When CLK is for low level, MN2 and MN3 ends, and on electric capacity C2, maintained switch cuts
Voltage before only is constant.But in fact, due to the presence of leakage current, on electric capacity C2, voltage still can slowly change.Metal-oxide-semiconductor source and drain
Between to produce the main cause of electric leakage be that during metal-oxide-semiconductor cut-off, source-drain voltage differs, and voltage difference is bigger, and leaky is got over
Substantially.With respect to the traditional structure shown in Fig. 1, in switch cut-off, VB voltage can electric leakage between VA and VC, on MN3
Electric current can be less than the leakage current on MN1 in Fig. 1.Switch shown in Fig. 2, by the electricity between source and drain when reducing metal-oxide-semiconductor cut-off
Pressure reduction, reduces leakage current.
As shown in figure 3, a kind of anticreep MOS switch structure be applied to integrated circuit proposed by the present invention, including
PMOS MP1, NMOS tube MN4 and NMOS tube MN5 and operational amplifier A MP1 of a Single-end output；Described NMOS tube MN4 and
NMOS tube MN5 is the MOS switch on signal transmission pathway, and described PMOS MP1 is to control described Single-end output operational amplifier
The switch of AMP1 output feedback signal；The source electrode of described NMOS tube MN4 connects input signal, and the drain electrode of described NMOS tube MN4 is same
When connect the source electrode of NMOS tube MN5 and the source electrode of PMOS MP1, NMOS tube MN4 grid connects clock signal clk；NMOS tube MN5
Drain electrode connect the normal phase input end of signal output part and described operational amplifier A MP1, the grid of NMOS tube MN5 connects clock
Signal CLK；The source electrode of PMOS MP1 connects the drain electrode of NMOS tube MN4, the drain electrode concatenation operation amplifier AMP's of PMOS MP1
Output end, the grid of PMOS MP1 connects clock signal clk；The normal phase input end of operational amplifier A MP1 and signal output part
Connect, after the negative-phase input of operational amplifier A MP1 is connected with the output end of operational amplifier A MP1 and connect to PMOS
The drain electrode of MP1.
The principle of the anticreep MOS switch of the present invention is that, in switch conduction, operational amplifier A MP1 is disconnected from the circuit,
Do not affect to switch normal function；In switch cut-off, operational amplifier A MP1 accesses electricity according to the mode of unity gain buffer
Road, the switching tube MN5 source electrode being joined directly together with load and drain electrode clamper to identical voltage, it is to avoid the electric charge in load passes through to open
Close metal-oxide-semiconductor to reveal.Specific works mode is as follows, and when CLK is for high level, NMOS tube MN4 and MN5 turn on, and PMOS MP1 is cut
Only, now operational amplifier A MP1 output end is disconnected from the circuit, operational amplifier A MP1 normal phase input end and load capacitance C3
Parallel connection, because operational amplifier A MP1 input is high resistant node, obstructed overcurrent, impact will not be produced on circuit performance.When
When CLK is low level, NMOS tube MN4 and MN5 disconnect, and PMOS MP1 turns on, now operational amplifier A MP1 output end and node
VB is connected.Amplifier negative-phase input is connected to output end, as unity gain buffer so that VB and VC node voltage is equal,
MN5 source electrode and drain voltage are equal, thus almost not having leakage current on switching tube MN5.Finally achieving prevents switch drain
Lead to the effect of load capacitance node VC voltage change.
Operational amplifier A MP1 structure used in anticreeping switch structure of the present invention is as shown in figure 4, as common NMOS
Five pipe amplifier structures of pipe input, produce biasing by resistance R1, and structure is simple, save area and power consumption.Described operation amplifier
Device AMP1 includes 4 NMOS tube, 2 PMOS and 1 resistance R1；Wherein, 4 NMOS tube be denoted as respectively NMOS tube NMOS6,
NMOS tube NMOS7, NMOS tube NMOS8 and NMOS tube NMOS9,2 PMOS are denoted as PMOS MP2 and PMOS MP3 respectively；Electricity
One end of resistance R1 connects power vd D, and the other end of resistance R1 connects grid and the drain electrode of NMOS tube MN6 simultaneously；The source of NMOS tube MN6
Pole ground connection, the grid of NMOS tube MN6 and the drain electrode of NMOS tube MN6 are simultaneously connected to the grid of NMOS tube MN7；NMOS tube MN7
Source ground, the drain electrode of NMOS tube MN7 is simultaneously connected with the source electrode of NMOS tube MN8 and NMOS tube MN9；The grid of NMOS tube MN8 is
Amplifier normal phase input end, the source electrode of NMOS tube MN8 connects the drain electrode of NMOS tube MN7, and the drain electrode of NMOS tube MN8 is simultaneously connected with PMOS
The drain and gate of pipe MP2；The grid of NMOS tube MN9 is amplifier negative-phase input, and the source electrode of NMOS tube MN9 connects NMOS tube
The drain electrode of MN7, the drain electrode of NMOS tube MN9 connects the drain electrode of PMOS MP3, and the source electrode of PMOS MP3 connects power vd D, PMOS
The grid of pipe MP3 connects the grid of PMOS MP2, and the drain electrode of PMOS MP3 is amplifier output end.
To sum up, a kind of anticreep MOS switch structure proposed by the present invention is on the basis of series connection nmos switch, increased
Operational amplifier realizes the source-drain voltage model- following control to nmos switch.Operational amplifier accesses electricity when nmos switch turns off
Road, it is ensured that nmos switch pipe remains in off state maintain source-drain voltage equal, prevents nmos switch from producing leakage current；Fortune
Calculate amplifier to be disconnected from the circuit when nmos switch turns on, impact will not be produced on switch performance.The operational amplifier using
Realized using simple five pipe amplifier structures, structure is simple, area occupied and power consumption very little.By switch knot proposed by the present invention
Structure, can be substantially reduced and be changed due to the node voltage that MOS switch leakage current leads to, realize the effective guarantor to key node
Shield.
Although above in conjunction with figure, invention has been described, the invention is not limited in above-mentioned specific embodiment party
Formula, above-mentioned specific embodiment is only schematically, rather than restricted, and those of ordinary skill in the art is at this
Under bright enlightenment, without deviating from the spirit of the invention, many variations can also be made, these belong to the guarantor of the present invention
Within shield.
Claims (3)
1. a kind of anticreep MOS switch structure be applied to integrated circuit is it is characterised in that include PMOS MP1, NMOS tube
MN4 and operational amplifier A MP1 of NMOS tube MN5 and a Single-end output；Described NMOS tube MN4 and NMOS tube MN5 are that signal passes
MOS switch on defeated path, described PMOS MP1 is to control described Single-end output operational amplifier A MP1 output feedback signal
Switch；
The source electrode of described NMOS tube MN4 connects input signal, and the drain electrode of described NMOS tube MN4 is simultaneously connected with the source of NMOS tube MN5
Pole and the source electrode of PMOS MP1, NMOS tube MN4 grid connects clock signal clk；The drain electrode of NMOS tube MN5 connects signal output
End and the normal phase input end of described operational amplifier A MP1, the grid of NMOS tube MN5 connects clock signal clk；PMOS MP1
The drain electrode of source electrode connection NMOS tube MN4, the output end of the drain electrode concatenation operation amplifier AMP of PMOS MP1, PMOS MP1
Grid connects clock signal clk；The normal phase input end of operational amplifier A MP1 and signal output part connect, operational amplifier A MP1
Negative-phase input be connected with the output end of operational amplifier A MP1 after and connect to the drain electrode of PMOS MP1.
2. according to claim 1 the anticreep MOS switch structure be applied to integrated circuit it is characterised in that described fortune
Calculate amplifier AMP1 and adopt five pipe amplifier structures.
3. according to claim 2 the anticreep MOS switch structure be applied to integrated circuit it is characterised in that described fortune
Calculate amplifier AMP1 and include 4 NMOS tube, 2 PMOS and 1 resistance R1；Wherein, 4 NMOS tube are denoted as NMOS tube respectively
NMOS6, NMOS tube NMOS7, NMOS tube NMOS8 and NMOS tube NMOS9,2 PMOS are denoted as PMOS MP2 and PMOS respectively
MP3；
One end of resistance R1 connects power vd D, and the other end of resistance R1 connects grid and the drain electrode of NMOS tube MN6 simultaneously；NMOS tube
The source ground of MN6, the grid of NMOS tube MN6 and the drain electrode of NMOS tube MN6 are simultaneously connected to the grid of NMOS tube MN7；NMOS
The source ground of pipe MN7, the drain electrode of NMOS tube MN7 is simultaneously connected with the source electrode of NMOS tube MN8 and NMOS tube MN9；NMOS tube MN8
Grid is amplifier normal phase input end, and the source electrode of NMOS tube MN8 connects the drain electrode of NMOS tube MN7, and the drain electrode of NMOS tube MN8 connects simultaneously
Connect the drain and gate of PMOS MP2；The grid of NMOS tube MN9 is amplifier negative-phase input, and the source electrode of NMOS tube MN9 connects
The drain electrode of NMOS tube MN7, the drain electrode of NMOS tube MN9 connects the drain electrode of PMOS MP3, and the source electrode of PMOS MP3 connects power supply
VDD, the grid of PMOS MP3 connects the grid of PMOS MP2, and the drain electrode of PMOS MP3 is amplifier output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610825179.3A CN106411303A (en) | 2016-09-16 | 2016-09-16 | Anti-creeping MOS switch structure applicable to integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610825179.3A CN106411303A (en) | 2016-09-16 | 2016-09-16 | Anti-creeping MOS switch structure applicable to integrated circuit |
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| CN106411303A true CN106411303A (en) | 2017-02-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610825179.3A Pending CN106411303A (en) | 2016-09-16 | 2016-09-16 | Anti-creeping MOS switch structure applicable to integrated circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425847A (en) * | 2017-07-17 | 2017-12-01 | 南京邮电大学 | A kind of charge transfer type simulation based on rising edge of a pulse triggering counts reading circuit |
| CN109379067A (en) * | 2018-12-12 | 2019-02-22 | 北京集创北方科技股份有限公司 | Switching circuit and signal acquiring system |
| CN110166030A (en) * | 2018-12-12 | 2019-08-23 | 北京集创北方科技股份有限公司 | Switching circuit and signal acquiring system |
| CN110427740A (en) * | 2019-07-30 | 2019-11-08 | 深圳市智微智能软件开发有限公司 | A kind of encryption method and system |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425847A (en) * | 2017-07-17 | 2017-12-01 | 南京邮电大学 | A kind of charge transfer type simulation based on rising edge of a pulse triggering counts reading circuit |
| CN107425847B (en) * | 2017-07-17 | 2020-07-14 | 南京邮电大学 | Charge transfer type analog counting reading circuit based on pulse rising edge triggering |
| CN109379067A (en) * | 2018-12-12 | 2019-02-22 | 北京集创北方科技股份有限公司 | Switching circuit and signal acquiring system |
| CN110166030A (en) * | 2018-12-12 | 2019-08-23 | 北京集创北方科技股份有限公司 | Switching circuit and signal acquiring system |
| CN110427740A (en) * | 2019-07-30 | 2019-11-08 | 深圳市智微智能软件开发有限公司 | A kind of encryption method and system |
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