CN105720970A - XOR/XNOR gate circuit based on FinFET devices - Google Patents

XOR/XNOR gate circuit based on FinFET devices Download PDF

Info

Publication number
CN105720970A
CN105720970A CN201610044398.8A CN201610044398A CN105720970A CN 105720970 A CN105720970 A CN 105720970A CN 201610044398 A CN201610044398 A CN 201610044398A CN 105720970 A CN105720970 A CN 105720970A
Authority
CN
China
Prior art keywords
finfet pipe
finfet
pipe
circuit
xor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610044398.8A
Other languages
Chinese (zh)
Other versions
CN105720970B (en
Inventor
胡建平
张绪强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ningbo University
Original Assignee
Ningbo University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ningbo University filed Critical Ningbo University
Priority to CN201610044398.8A priority Critical patent/CN105720970B/en
Publication of CN105720970A publication Critical patent/CN105720970A/en
Application granted granted Critical
Publication of CN105720970B publication Critical patent/CN105720970B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses an XOR/XNOR gate circuit based on FinFET devices. The circuit comprises a first FinFET transistor, a second FinFET transistor, a third FinFET transistor, a fourth FinFET transistor, a fifth FinFET transistor, and a sixth FinFET transistor, the first FinFET transistor and the fourth FinFET transistor are both P-type FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all N-type FinFET transistors, the first FinFET transistor and the fourth FinFET transistor are both low-threshold FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all high-threshold FinFET transistors, the numbers of the fins of the first FinFET transistor and the fourth FinFET transistor are both 1, and the numbers of the fins of the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all 2. The circuit is advantageous in that the logic function is correct, the circuit area is small, the time delay is short, the power consumption is low, and the consumption-delay product is small.

Description

A kind of XOR based on FinFET device/same to OR circuit
Technical field
The present invention relates to a kind of XOR/same to OR circuit, especially relate to a kind of XOR based on FinFET/same to OR circuit.
Background technology
Elementary logic circuit is logic circuit most basic in digital circuit, and XOR/with OR circuit is the indispensable part of elementary logic circuit.The double rail logic of differential cascade voltage switching logic provides difference output, but conventional voltage switching logic still to face number of transistors many, the problem that power consumption is big and design is complicated.Along with the continuous progress of VISL technology, the speed of service and the power consumption requirements of digital display circuit improve constantly, and the requirement of the performance of basic logic unit is also harsher, it is desirable to basic logic unit should have low-power consumption and short time delay.
Along with constantly reducing of transistor size, by the restriction of short-channel effect and present production process, the space of common CMOS transistor size reduction extremely reduces.When the size reduction of common CMOS transistor is to below 20nm, the leakage current of device can sharply strengthen, and causes bigger circuit leakage power consumption.Further, circuit short-channel effect becomes readily apparent from, and device becomes rather unstable, significantly limit the raising of circuit performance.FinFET manages (fin field-effect transistor, FinField-EffectTransistor) be a kind of new CMOS (CMOS) transistor it is a kind of novel 3D transistor, the raceway groove of FinFET pipe adopts zero doping or low-doped, and raceway groove is enclosed by grid three bread.This special 3-D solid structure, enhances the grid control dynamics to raceway groove, inhibits short-channel effect greatly, it is suppressed that the leakage current of device.FinFET pipe has low in energy consumption, the advantage that area is little, is increasingly becoming and takes over conventional CMOS devices, one of improved device of continuity Moore's Law.
In view of this, design on a kind of basis with correct logic function, the XOR based on FinFET that circuit area, time delay, power consumption and power-consumption design are all less/significant with OR circuit.
Summary of the invention
The technical problem to be solved is to provide on a kind of basis with correct logic function, the XOR based on FinFET that circuit area, time delay, power consumption and power-consumption design are all less/same to OR circuit.
This invention address that the technical scheme that above-mentioned technical problem adopts is: a kind of XOR based on FinFET/same to OR circuit, manage including a FinFET, the 2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET manage and the 6th FinFET pipe, a described FinFET pipe and the 4th described FinFET pipe are P type FinFET pipe, and the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe are N-type FinFET pipe；A described FinFET pipe and the 4th described FinFET pipe are Low threshold FinFET pipe, the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe are high threshold FinFET pipe, a described FinFET pipe and the number of the 4th described FinFET pipe fin are 1, and the number of the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe fin is 2；
The source electrode of a described FinFET pipe and the source electrode of the 4th described FinFET pipe all access power supply, the drain electrode of a described FinFET pipe, the drain electrode of the 2nd described FinFET pipe, the drain electrode of the 3rd described FinFET pipe and the described front gate of the 4th FinFET pipe and the back-gate connection of the 4th described FinFET pipe and its link are the described XOR based on FinFET/with the first outfan of OR circuit, the described XOR based on FinFET/be used for exporting XOR signal with the first outfan of OR circuit, the front gate of a described FinFET pipe, the backgate of a described FinFET pipe, the drain electrode of the 5th described FinFET pipe, the drain electrode of the 4th described FinFET pipe and the drain electrode of described the 6th FinFET pipe connects and its link is the described XOR based on FinFET/with the second outfan of OR circuit, the described XOR based on FinFET/be used for exporting same or signal with the second outfan of OR circuit, the front gate of the front gate of the 3rd described FinFET pipe and the 5th described FinFET pipe connects and its link is the described XOR based on FinFET/with the first input end of OR circuit, described first input end is used for inputting the first input signal, the backgate of the 3rd described FinFET pipe and the back-gate connection of the 6th described FinFET pipe and its link are the described XOR based on FinFET/with the second input of OR circuit, the second described input is used for inputting the second input signal, the front gate of the front gate of the 2nd described FinFET pipe and the 6th described FinFET pipe connects and its link is the described XOR based on FinFET/with the first inverting input of OR circuit, the first described inverting input is for inputting the inversion signal of the first input signal, the backgate of the 2nd described FinFET pipe and the back-gate connection of the 5th described FinFET pipe and its link are the described XOR based on FinFET/with the second inverting input of OR circuit, the second described inverting input is used for inputting the second rp input signal, the source electrode of the 2nd described FinFET pipe, the source electrode of the 3rd described FinFET pipe, the source electrode of the 5th described FinFET pipe and the source grounding of the 6th described FinFET pipe.
A described FinFET pipe and the threshold voltage of the 4th described FinFET pipe are 0.1V, the equal 0.6V of threshold voltage of the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe.
Compared with prior art, it is an advantage of the current invention that to include a FinFET pipe, the 2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe and the 6th FinFET pipe, oneth FinFET pipe and the 4th FinFET pipe are P type FinFET pipe, and the 2nd FinFET pipe, the 3rd FinFET pipe, the 5th FinFET pipe and the 6th FinFET pipe are N-type FinFET pipe；Oneth FinFET pipe and the 4th FinFET pipe are Low threshold FinFET pipe, 2nd FinFET pipe, the 3rd FinFET pipe, the 5th FinFET pipe and the 6th FinFET pipe are high threshold FinFET pipe, the number of the oneth FinFET pipe and the 4th FinFET pipe fin is 1, and the number of the 2nd FinFET pipe, the 3rd FinFET pipe, the 5th FinFET pipe and the 6th FinFET pipe fin is 2；Managed by a FinFET, the 4th FinFET pipe realizes difference output, realizes " with function " by the 2nd FinFET pipe, the 3rd FinFET pipe, the 5th FinFET pipe and the 6th FinFET pipe, is equivalent to two traditional cmos pipe series connection, the time delay of reduction circuit.Circuit performance and traditional cmos differential cascade voltage switching logic XOR/essentially identical with OR circuit, the branch road of the 2nd FinFET pipe and the 3rd FinFET pipe composition and the branch road alternation of the 5th FinFET pipe and the 6th FinFET pipe composition, when the 2nd FinFET pipe front gate and after grid input respectively the first input signal inversion signal Ab and the second input signal inversion signal Bb, when the 3rd FinFET pipe front gate and after grid input respectively first input signal A and the second input signal B, the 2nd FinFET pipe and the 3rd FinFET pipe composition branch road output For XOR symbol；When the 5th FinFET pipe front gate and after grid input respectively first input signal A and the second input signal inversion signal Bb, when the 6th FinFET pipe front gate and after grid input respectively first input signal B and the second input signals reverse signal Ab, the 5th FinFET pipe and the 6th FinFET pipe composition branch road outputFor same or symbol, realize difference output, eliminate quiescent dissipation, and realize same or with XOR output simultaneously, need not additionally add phase inverter and obtain contrary logic output, further reducing the number of transistor, thus have on the basis of correct logic function, circuit area, time delay, power consumption and power-consumption design are all less.
When the threshold voltage of a FinFET pipe and the 4th FinFET pipe is 0.1V, during the equal 0.6V of the 2nd FinFET pipe, the 3rd FinFET pipe, the 5th FinFET pipe and the threshold voltage of the 6th FinFET pipe, in this circuit, threshold voltage is more low, circuit operating rate is more fast, but the too fast meeting of circuit operating rate causes that power consumption rises substantially, when threshold voltage is 0.1V and 0.6V, ensureing on the operating rate basis faster of circuit, power consumption is made to increase inconspicuous.
Accompanying drawing explanation
Fig. 1 is traditional cmos differential cascade voltage switching logic XOR/with the circuit diagram of OR circuit；
Fig. 2 is a kind of XOR based on FinFET/with the circuit diagram of OR circuit of the present invention；
Fig. 3 is the XOR based on FinFET of the present invention under normal voltage (1v)/with the OR circuit simulation waveform figure based on BSIMIMG standard technology；
Fig. 4 is the XOR based on FinFET of the present invention under superthreshold voltage (0.8v)/with the OR circuit simulation waveform figure based on BSIMIMG standard technology.
Detailed description of the invention
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
Embodiment one: as shown in Figure 2, a kind of XOR based on FinFET/same to OR circuit, including a FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5 and the six FinFET pipe M6, oneth FinFET pipe M1 and the four FinFET pipe M4 is P type FinFET pipe, and the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 5th FinFET pipe M5 and the six FinFET pipe M6 are N-type FinFET pipe；Oneth FinFET pipe M1 and the four FinFET pipe M4 is Low threshold FinFET pipe, 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 5th FinFET pipe M5 and the six FinFET pipe M6 are high threshold FinFET pipe, the number of the oneth FinFET pipe M1 and the four FinFET pipe M4 fin is 1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 5th FinFET pipe M5 and the six FinFET pipe M6 fin number be 2；
The source electrode of the oneth FinFET pipe M1 and the source electrode of the 4th FinFET pipe M4 all access power supply, the drain electrode of the oneth FinFET pipe M1, the drain electrode of the 2nd FinFET pipe M2, the back-gate connection of the drain electrode of the 3rd FinFET pipe M3 and the front gate of the 4th FinFET pipe M4 and the 4th FinFET pipe M4 and its link are the XOR based on FinFET/with the first outfan of OR circuit, XOR/be used for exporting XOR signal with the first outfan of OR circuit based on FinFET, the front gate of the oneth FinFET pipe M1, the backgate of the oneth FinFET pipe M1, the drain electrode of the 5th FinFET pipe M5, the drain electrode of the 4th FinFET pipe M4 and the drain electrode of the 6th FinFET pipe M6 connects and its link is the XOR based on FinFET/with the second outfan of OR circuit, based on FinFET XOR/with the second outfan of OR circuit be used for exporting with or signal, the front gate of the front gate of the 3rd FinFET pipe M3 and the 5th FinFET pipe M5 connects and its link is the XOR based on FinFET/with the first input end of OR circuit, first input end is used for inputting the first input signal, the backgate of the 3rd FinFET pipe M3 and the back-gate connection of the 6th FinFET pipe M6 and its link are the XOR based on FinFET/with the second input of OR circuit, second input is used for inputting the second input signal, the front gate of the front gate of the 2nd FinFET pipe M2 and the 6th FinFET pipe M6 connects and its link is the XOR based on FinFET/with the first inverting input of OR circuit, first inverting input is for inputting the inversion signal of the first input signal, the backgate of the 2nd FinFET pipe M2 and the back-gate connection of the 5th FinFET pipe M5 and its link are the XOR based on FinFET/with the second inverting input of OR circuit, second inverting input is used for inputting the second rp input signal, the source electrode of the 2nd FinFET pipe M2, the source electrode of the 3rd FinFET pipe M3, the source electrode of the 5th FinFET pipe M5 and the source grounding of the 6th FinFET pipe M6.
Embodiment two: as shown in Figure 2, a kind of XOR based on FinFET/same to OR circuit, including a FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5 and the six FinFET pipe M6, oneth FinFET pipe M1 and the four FinFET pipe M4 is P type FinFET pipe, and the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 5th FinFET pipe M5 and the six FinFET pipe M6 are N-type FinFET pipe；Oneth FinFET pipe M1 and the four FinFET pipe M4 is Low threshold FinFET pipe, 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 5th FinFET pipe M5 and the six FinFET pipe M6 are high threshold FinFET pipe, the number of the oneth FinFET pipe M1 and the four FinFET pipe M4 fin is 1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 5th FinFET pipe M5 and the six FinFET pipe M6 fin number be 2；
The source electrode of the oneth FinFET pipe M1 and the source electrode of the 4th FinFET pipe M4 all access power supply, the drain electrode of the oneth FinFET pipe M1, the drain electrode of the 2nd FinFET pipe M2, the back-gate connection of the drain electrode of the 3rd FinFET pipe M3 and the front gate of the 4th FinFET pipe M4 and the 4th FinFET pipe M4 and its link are the XOR based on FinFET/with the first outfan of OR circuit, XOR/be used for exporting XOR signal with the first outfan of OR circuit based on FinFET, the front gate of the oneth FinFET pipe M1, the backgate of the oneth FinFET pipe M1, the drain electrode of the 5th FinFET pipe M5, the drain electrode of the 4th FinFET pipe M4 and the drain electrode of the 6th FinFET pipe M6 connects and its link is the XOR based on FinFET/with the second outfan of OR circuit, based on FinFET XOR/with the second outfan of OR circuit be used for exporting with or signal, the front gate of the front gate of the 3rd FinFET pipe M3 and the 5th FinFET pipe M5 connects and its link is the XOR based on FinFET/with the first input end of OR circuit, first input end is used for inputting the first input signal, the backgate of the 3rd FinFET pipe M3 and the back-gate connection of the 6th FinFET pipe M6 and its link are the XOR based on FinFET/with the second input of OR circuit, second input is used for inputting the second input signal, the front gate of the front gate of the 2nd FinFET pipe M2 and the 6th FinFET pipe M6 connects and its link is the XOR based on FinFET/with the first inverting input of OR circuit, first inverting input is for inputting the inversion signal of the first input signal, the backgate of the 2nd FinFET pipe M2 and the back-gate connection of the 5th FinFET pipe M5 and its link are the XOR based on FinFET/with the second inverting input of OR circuit, second inverting input is used for inputting the second rp input signal, the source electrode of the 2nd FinFET pipe M2, the source electrode of the 3rd FinFET pipe M3, the source electrode of the 5th FinFET pipe M5 and the source grounding of the 6th FinFET pipe M6.
In the present embodiment, the threshold voltage of a FinFET pipe M1 and the four FinFET pipe M4 is 0.1V, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 5th FinFET pipe M5 and the six FinFET pipe M6 the equal 0.6V of threshold voltage.
A kind of XOR based on FinFET of the present invention/be with the operation principle of OR circuit: managed by a FinFET, the 4th FinFET pipe realizes difference output, managed by the 2nd FinFET, the 3rd FinFET pipe, the 5th FinFET manage and the 6th FinFET pipe realizes " with function ", be equivalent to two traditional cmos pipe series connection, reduce the time delay of circuit.Circuit performance and traditional cmos differential cascade voltage switching logic XOR/essentially identical with OR circuit, the branch road of the 2nd FinFET pipe and the 3rd FinFET pipe composition and the branch road alternation of the 5th FinFET pipe and the 6th FinFET pipe composition, when the 2nd FinFET pipe front gate and after grid input respectively the first input signal inversion signal Ab and the second input signal inversion signal Bb, when the 3rd FinFET pipe front gate and after grid input respectively first input signal A and the second input signal B, the 2nd FinFET pipe and the 3rd FinFET pipe composition branch road outputFor XOR symbol；When the 5th FinFET pipe front gate and after grid input respectively first input signal A and the second input signal inversion signal Bb, when the 6th FinFET pipe front gate and after grid input respectively first input signal B and the second input signals reverse signal Ab, the 5th FinFET pipe and the 6th FinFET pipe composition branch road outputFor same or symbol, realize difference output, eliminate quiescent dissipation, and realize same or with XOR output simultaneously, need not additionally add phase inverter and obtain contrary logic output, further reducing the number of transistor, thus have on the basis of correct logic function, circuit area, time delay, power consumption and power-consumption design are all less.
In order to verify a kind of XOR based on FinFET of the present invention/with the excellent benefit of OR circuit, under this standard technology of BSIMIMG, using circuit simulation tools HSPICE is 100MHz in the incoming frequency of circuit, 400MHz, 800MHz, when 1GHz, by a kind of XOR based on FinFET of the present invention/same to OR circuit, traditional cmos differential cascade voltage switching logic XOR/same to OR circuit (being called for short tradition XOR/same to OR circuit) shown in Fig. 1 and the same grid XOR/same OR circuit based on FinFET (being called for short with grid XOR/same to OR circuit) the these three XOR/carry out Comparative Simulation with the circuit of OR circuit in BSIMIMG technology library, the supply voltage that BSIMIMG technology library is corresponding is 1V.The XOR based on FinFET of the present invention under normal voltage (1v)/with the OR circuit simulation waveform figure based on BSIMIMG standard technology as it is shown on figure 3, the XOR based on FinFET of the present invention under superthreshold voltage (0.8v)/with OR circuit based on BSIMIMG standard technology simulation waveform figure as shown in Figure 4.
At BSIMIMG standard technology, to the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/compare with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/carry out emulation with OR circuit when incoming frequency is 100MHz, its Performance comparision table is as shown in table 1.
When table 1 incoming frequency is 100MHz, the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/with the Performance comparision table of OR circuit
As can be drawn from Table 1: the XOR based on FinFET of the present invention/with OR circuit with based on FinFET with grid XOR/with the DCVSL logic XOR/with compared with OR circuit of OR circuit and traditional cmos, number of transistors reduces 2, time delay reduces 33% respectively and reduces 58%, average total power consumption reduces 15% respectively and increases 1%, and power-consumption design reduces 42% respectively and reduces 58%.
At BSIMIMG standard technology, to the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/compare with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/carry out emulation with OR circuit when incoming frequency is 400MHz, its Performance comparision table is as shown in table 2.
When table 2 incoming frequency is 400MHz, the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/with the Performance comparision table of OR circuit
As can be drawn from Table 2: the XOR based on FinFET of the present invention/with OR circuit with based on FinFET with grid XOR/with the DCVSL logic XOR/with compared with OR circuit of OR circuit and traditional cmos, number of transistors reduces 2, time delay reduces 33% respectively and reduces 58%, average total power consumption reduces 15% respectively and increases 1%, and power-consumption design reduces 44% respectively and reduces 60%.
At BSIMIMG standard technology, to the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/compare with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/carry out emulation with OR circuit when incoming frequency is 800MHz, its Performance comparision table is as shown in table 3.
When table 3 incoming frequency is 800MHz, the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/with the Performance comparision table of OR circuit
As can be drawn from Table 3: the XOR based on FinFET of the present invention/with OR circuit with based on FinFET with grid XOR/with the DCVSL logic XOR/with compared with OR circuit of OR circuit and traditional cmos, number of transistors reduces 2, time delay reduces 33% respectively and reduces 58%, average total power consumption reduces 17% respectively and increases 1%, and power-consumption design reduces 44% respectively and reduces 60%.
At BSIMIMG standard technology, to the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/compare with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/carry out emulation with OR circuit when incoming frequency is 1G, its Performance comparision table is as shown in table 4.
When table 4 incoming frequency is 1G, the traditional cmos differential cascade voltage switching logic XOR shown in a kind of XOR based on FinFET of the present invention/same to OR circuit, Fig. 1/with the same grid XOR based on FinFET in OR circuit and BSIMIMG technology library/with the Performance comparision table of OR circuit
As can be drawn from Table 4: the XOR based on FinFET of the present invention/with OR circuit with based on FinFET with grid XOR/with the DCVSL logic XOR/with compared with OR circuit of OR circuit and traditional cmos, number of transistors reduces 2, time delay reduces 33% respectively and reduces 58%, average total power consumption reduces 21% respectively and increases 1%, and power-consumption design reduces 44.5% respectively and reduces 60%.
From above-mentioned comparison data, have correct logic function and do not affect circuit performance basis on, XOR based on FinFET proposed by the invention/with OR circuit with based on FinFET with grid XOR/with the DCVSL logic XOR/with compared with OR circuit of OR circuit and traditional cmos, the quantity of transistor decreases 2, and time delay, power consumption and power-consumption design have also arrived notable optimization.

Claims (2)

1. the XOR based on FinFET/same to OR circuit, it is characterized in that including a FinFET pipe, the 2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe and the 6th FinFET pipe, a described FinFET pipe and the 4th described FinFET pipe are P type FinFET pipe, and the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe are N-type FinFET pipe；A described FinFET pipe and the 4th described FinFET pipe are Low threshold FinFET pipe, the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe are high threshold FinFET pipe, a described FinFET pipe and the number of the 4th described FinFET pipe fin are 1, and the number of the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe fin is 2；
The source electrode of a described FinFET pipe and the source electrode of the 4th described FinFET pipe all access power supply, the drain electrode of a described FinFET pipe, the drain electrode of the 2nd described FinFET pipe, the drain electrode of the 3rd described FinFET pipe and the described front gate of the 4th FinFET pipe and the back-gate connection of the 4th described FinFET pipe and its link are the described XOR based on FinFET/with the first outfan of OR circuit, the described XOR based on FinFET/be used for exporting XOR signal with the first outfan of OR circuit, the front gate of a described FinFET pipe, the backgate of a described FinFET pipe, the drain electrode of the 5th described FinFET pipe, the drain electrode of the 4th described FinFET pipe and the drain electrode of described the 6th FinFET pipe connects and its link is the described XOR based on FinFET/with the second outfan of OR circuit, the described XOR based on FinFET/be used for exporting same or signal with the second outfan of OR circuit, the front gate of the front gate of the 3rd described FinFET pipe and the 5th described FinFET pipe connects and its link is the described XOR based on FinFET/with the first input end of OR circuit, described first input end is used for inputting the first input signal, the backgate of the 3rd described FinFET pipe and the back-gate connection of the 6th described FinFET pipe and its link are the described XOR based on FinFET/with the second input of OR circuit, the second described input is used for inputting the second input signal, the front gate of the front gate of the 2nd described FinFET pipe and the 6th described FinFET pipe connects and its link is the described XOR based on FinFET/with the first inverting input of OR circuit, the first described inverting input is for inputting the inversion signal of the first input signal, the backgate of the 2nd described FinFET pipe and the back-gate connection of the 5th described FinFET pipe and its link are the described XOR based on FinFET/with the second inverting input of OR circuit, the second described inverting input is used for inputting the second rp input signal, the source electrode of the 2nd described FinFET pipe, the source electrode of the 3rd described FinFET pipe, the source electrode of the 5th described FinFET pipe and the source grounding of the 6th described FinFET pipe.
2. a kind of XOR based on FinFET according to claim 1/same or circuit, it is characterized in that the threshold voltage of a described FinFET pipe and the 4th described FinFET pipe is 0.1V, the equal 0.6V of threshold voltage of the 2nd described FinFET pipe, the 3rd described FinFET pipe, the 5th described FinFET pipe and the 6th described FinFET pipe.
CN201610044398.8A 2016-01-22 2016-01-22 A kind of exclusive or based on FinFET/same to OR circuit Active CN105720970B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610044398.8A CN105720970B (en) 2016-01-22 2016-01-22 A kind of exclusive or based on FinFET/same to OR circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610044398.8A CN105720970B (en) 2016-01-22 2016-01-22 A kind of exclusive or based on FinFET/same to OR circuit

Publications (2)

Publication Number Publication Date
CN105720970A true CN105720970A (en) 2016-06-29
CN105720970B CN105720970B (en) 2018-06-26

Family

ID=56153823

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610044398.8A Active CN105720970B (en) 2016-01-22 2016-01-22 A kind of exclusive or based on FinFET/same to OR circuit

Country Status (1)

Country Link
CN (1) CN105720970B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204770A (en) * 2017-04-18 2017-09-26 宁波大学 Same or/NOR gate circuit based on FinFET
CN107222200A (en) * 2017-04-18 2017-09-29 宁波大学 Current-mode RM or non-XOR units based on FinFET
CN107222204A (en) * 2017-04-20 2017-09-29 宁波大学 Current-mode RM or non-XOR units based on FinFET transistors
CN109327206A (en) * 2018-09-30 2019-02-12 天津大学 Power consumption planarizes standard integrated circuit
CN109671454A (en) * 2018-11-16 2019-04-23 华南理工大学 A kind of differential logic memory lines column select circuit and chip
CN111313889A (en) * 2020-02-21 2020-06-19 宁波大学 Positive feedback XOR/XNOR gate and mixed logic adder

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060237774A1 (en) * 2004-04-28 2006-10-26 International Business Machines Corporation Backgated finfet having different oxide thicknesses
CN102857217A (en) * 2012-09-11 2013-01-02 宁波大学 Low-power-consumption xor/xnor gate circuit
CN105144389A (en) * 2013-03-19 2015-12-09 Soitec公司 Finfet with back-gate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060237774A1 (en) * 2004-04-28 2006-10-26 International Business Machines Corporation Backgated finfet having different oxide thicknesses
CN102857217A (en) * 2012-09-11 2013-01-02 宁波大学 Low-power-consumption xor/xnor gate circuit
CN105144389A (en) * 2013-03-19 2015-12-09 Soitec公司 Finfet with back-gate

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204770A (en) * 2017-04-18 2017-09-26 宁波大学 Same or/NOR gate circuit based on FinFET
CN107222200A (en) * 2017-04-18 2017-09-29 宁波大学 Current-mode RM or non-XOR units based on FinFET
CN107222200B (en) * 2017-04-18 2020-07-28 宁波大学 Current mode RM or non-exclusive OR unit circuit based on FinFET device
CN107222204A (en) * 2017-04-20 2017-09-29 宁波大学 Current-mode RM or non-XOR units based on FinFET transistors
CN107222204B (en) * 2017-04-20 2020-07-24 宁波大学 Current mode RM or non-exclusive OR unit circuit based on FinFET transistor
CN109327206A (en) * 2018-09-30 2019-02-12 天津大学 Power consumption planarizes standard integrated circuit
CN109327206B (en) * 2018-09-30 2020-09-25 天津大学 Power consumption flattening standard integrated circuit
CN109671454A (en) * 2018-11-16 2019-04-23 华南理工大学 A kind of differential logic memory lines column select circuit and chip
CN109671454B (en) * 2018-11-16 2021-05-14 华南理工大学 Differential logic memory row and column selection circuit and chip
CN111313889A (en) * 2020-02-21 2020-06-19 宁波大学 Positive feedback XOR/XNOR gate and mixed logic adder
CN111313889B (en) * 2020-02-21 2023-05-12 宁波大学 Positive feedback exclusive-or/exclusive-or gate and mixed logic adder

Also Published As

Publication number Publication date
CN105720970B (en) 2018-06-26

Similar Documents

Publication Publication Date Title
CN105720970A (en) XOR/XNOR gate circuit based on FinFET devices
CN102857217B (en) Low-power-consumption xor/xnor gate circuit
CN106385250B (en) A kind of same or XOR circuit based on FinFET grid dividing structure mutual symmetry logic
CN105720969B (en) A kind of one-bit full addres based on FinFET
CN102082561B (en) SOI (silicon on insulator) clock double-edge static D type trigger
CN103580479A (en) Voltage conversion circuit
US20180182450A1 (en) Ternary 2-9 line address decoder realized by cnfet
CN107222187B (en) Short pulse type D trigger based on FinFET device
CN107623518B (en) Level shifter circuit and method for applying level shifter circuit
CN104836570A (en) AND/XOR gate circuit based on transistor level
CN105720948B (en) A kind of clock control flip-flops based on FinFET
CN103957002A (en) Grid voltage bootstrapping xor/xnor circuit and grid voltage bootstrapping single-bit full adder
CN104617916B (en) Master-slave flip-flop based on FinFET transistor
CN105958975B (en) A kind of pulse-type D flip-flop based on FinFET
CN106505995B (en) A kind of single track current-mode one-bit full addres based on FinFET
CN107222200B (en) Current mode RM or non-exclusive OR unit circuit based on FinFET device
CN204376867U (en) Low energy logic and there is the NOR gate of this logical circuit, NAND gate and inverter
CN208299781U (en) A kind of PERES gate circuit applied to reversible logic circuits
CN208299779U (en) A kind of TR gate circuit applied to reversible logic circuits
CN105958974B (en) A kind of TSPC trigger based on FinFET
CN107222204A (en) Current-mode RM or non-XOR units based on FinFET transistors
CN107196627A (en) A kind of current-mode d type flip flop based on FinFET
CN213342181U (en) TSG reversible logic gate circuit applied to reversible logic circuit
CN108494386B (en) FinFET-based master-slave trigger
CN105871359B (en) A kind of pulse trigger based on FinFET

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant