CN100495915C

CN100495915C - CMOS single stabilization circuit

Info

Publication number: CN100495915C
Application number: CNB2006101697259A
Authority: CN
Inventors: 王晋; 乐立鹏; 赵宁; 蒋敏强
Original assignee: China Aerospace Modern Electronic Co 772nd Institute; Mxtronics Corp
Current assignee: Beijing times people core technology Co., Ltd.; China Aerospace Modern Electronic Company 772nd Institute
Priority date: 2006-12-28
Filing date: 2006-12-28
Publication date: 2009-06-03
Anticipated expiration: 2026-12-28
Also published as: CN1996751A

Abstract

This invention relates to one CMOS signal stable circuit, which comprises integral circuit, three status circuit and its control circuit and logic output circuit, wherein, the control circuit generates control signals with input end, zero clear end and output end; the three status control circuit adopts two Smite trigger for sample on integral circuit to generate three status circuit needed control signals by sample result; the two Smite trigger generates output signals through logical computation.

Description

A kind of CMOS monostable circuit

Technical field

The present invention relates to a kind of CMOS monostable circuit, can be widely used in the application such as shaping pulse, time-delay and timing.

Background technology

The distinguishing feature of monostable circuit is to have two different operating states: stable state and temporary stable state.Under the effect of extraneous trigger impulse, can be turned to temporary stable state from stable state, after stable state is kept a period of time temporarily, automatically restore to stable state again.The length that temporary stable state is held time depends on the parameter of circuit itself, and is irrelevant with the amplitude of trigger impulse.In general, monostable circuit is made up of integrating circuit, triple gate and tri state gate control circuit.The output of monostable circuit is directly by the result of integrating circuit decision, and the control signal of tri state gate control circuit also is that result according to integrating circuit obtains by the simple logic computing.Therefore, when integrating circuit was interfered, monostable circuit will produce wrong output.So there is poor anti jamming capability in existing monostable circuit, the shortcoming that reliability is low.

Summary of the invention

Technology of the present invention is dealt with problems and is: overcomes the deficiency of existing monostable circuit technology, provides a kind of antijamming capability strong, but the CMOS monostable circuit of reliability high repeated trigger.

Technical solution of the present invention is: a kind of CMOS monostable circuit, its characteristics are to comprise: integrating circuit, three state circuit, tri-state control circuit and logic output circuit, have input, clear terminal and output, integrating circuit is made up of off chip resistor R and capacitor C, three state circuit is made up of a PMOS and nmos pass transistor, the control input of three state circuit is produced by tri-state control circuit, and tri-state control circuit produces control signal according to the state of integrating circuit; Tri-state control circuit adopts two Schmidt triggers that the state of integrating circuit is sampled, and produces the required control signal of three state circuit according to sampled result through logical operation; The output signal of two Schmidt triggers generations in the tri-state control circuit is through the output of logic output circuit simultaneously.

Principle of the present invention: when reset signal was effective, the state of tri-state control circuit and three state circuit was initialised, and integrating circuit is output as high level, and entire circuit is in stable state; When input end signal descended, the state of tri-state control circuit changed, and caused the state of three state circuit to change, thereby made the capacitor discharge in the integrating circuit, and at this moment entire circuit plays pendulum, logic output circuit output high level; After the discharge of integrating circuit reached certain threshold value, the state of tri-state control circuit changed again, and the state of three state circuit also changes thereupon, thereby the electric capacity in the integrating circuit is charged; After the electric capacity charging reaches certain threshold value, make entire circuit recover stable state again, logic output circuit output low level.

The present invention's advantage compared with prior art is: because Schmidt trigger has the work characteristics of hysteresis, can be used for the amplitude of signal is carried out shaping, thus the influence of filtering interference signals.The present invention utilizes this distinguishing feature of Schmidt trigger just, adopts two Schmidt triggers that the state of integrating circuit is sampled in the control circuit of three state circuit, and effectively filtering interference signals is to the influence of integrating circuit.In addition, the logic output circuit does not directly join with integrating circuit, and some signals produce the direct influence of having avoided integrating circuit that logic is exported in the control circuit of three state circuit but utilize.Compare with traditional monostable circuit, improved the antijamming capability and the reliability of circuit.In addition, when chip design, can change the metastable duration by the retarding window size of regulating Schmidt trigger.

Description of drawings

Fig. 1 is the general structure block diagram of CMOS monostable circuit of the present invention;

Fig. 2 is the electrical schematic diagram of CMOS monostable circuit of the present invention;

Fig. 3 is the electrical schematic diagram of latch Latch of the present invention.

Embodiment

As shown in Figure 1, 2, be overall circuit figure of the present invention, be citation form of the present invention, it is made up of the control circuit 3 and the logic output circuit 4 of integrating circuit 1, three state circuit 2, three state circuit, and this monostable circuit has an input Input, clear terminal CLR and output.The control of three state circuit 2 input is to be produced by tri-state control circuit 3, and tri-state control circuit 3 to be states according to integrating circuit 1 produce control signal.In addition, tri-state control circuit 3 adopts two Schmidt triggers that the state of integrating circuit is sampled, and produce the required control signal of three state circuit 2 through logical operation according to sampled result, and logic output circuit 4 is relevant with the state of integrating circuit 1, but is produced by the relevant signal in the tri-state control circuit 3.

As shown in Figure 2, the integrating circuit 1 that the present invention adopts is made up of sheet outer resistance R and capacitor C, and three state circuit 2 is made of PMOS and nmos pass transistor serial connection, and wherein Shang Mian transistor is the PMOS pipe, and following is that NMOS manages.

As shown in Figure 2, tri-state control circuit 3 is made up of latch Latch, two Schmidt trigger SCHMITT1, SCHMITT2 and dependent LU, and its effect is to produce the control signal of three state circuit 2 and export 4 relevant signals with logic.Two Schmidt triggers are sampled to the state of integrating circuit, send in the latch, through producing the control signal of three state circuit after the logical block, produce logic output signal simultaneously and deliver to the output of logic output circuit.

Tri-state control circuit 3 concrete composed as follows described: the Input input signal carries out NAND operation through two inverters and CLR signal counter and produces the nCLK signal, and the nCLK signal is used for controlling the PMOS that is connected with power supply and manages.The nCLK signal produces the CLK signal through an inverter, and sends into latch.In addition, nCLK signal and CLK signal are also being controlled the transmission gate that is made of PMOS and NMOS pipe.The inverted signal of CLR signal also is admitted to latch Latch.The output RC of integrating circuit sends into latch Latch after through a Schmidt trigger SCHMITT1 and an inverter.The output of latch Latch through an inverter after, obtain a signal with the output of transmission gate or the PMOS pipe that is connected with power vd D do NAND operation, a signal is admitted to latch Latch simultaneously.In addition, the output of a signal and latch Latch produces the K signal through NOR gate, and a signal and CLR signal produce the O1 signal through NOR gate.The output RC of integrating circuit produces the O2 signal through another Schmidt trigger SCHMITT2, and the anti-and a signal of O2 signal obtains the L signal through a NAND gate.K, L, O1 and O2 signal are used for controlling three state circuit and logic output circuit as the output signal of tri-state control circuit.

As shown in Figure 3, be the circuit diagram of latch Latch used in the monostable circuit of the present invention.Common latch has only 2 inputs, and the latch in the circuit of the present invention has 4 input In1-In4.The input that difference is following NAND gate by the output of top NAND gate and input signal In2 through and computing produce, and another input is to be obtained through exclusive disjunction by other two input signal In3 and In4.

As shown in Figure 2, operation principle of the present invention: the monostable circuit labile state is to be triggered by the rising edge of input signal Input.When clear terminal CLR is high effectively the time, the state of latch Latch is initialised, and K, L are changed to zero, and external capacitor R is recharged paramount, and the current potential of a end be a height.Because the RC end is high potential, the output of two Schmidt triggers is electronegative potential, thereby monostable circuit is output as electronegative potential.When clear terminal CLR is an electronegative potential, when input signal A was electronegative potential, the state of latch changed, and the upper end is 1, and the lower end is 0, and the state of other end is constant.When input signal Input becomes high potential by electronegative potential, the state of latch keeps not changing, the upper end is 1, and the lower end is 0, but the current potential of nCLK end is low, thereby make with three state circuit that VDD links to each other in the PMOS conducting, therefore a end becomes electronegative potential, and then the K end becomes high potential, manages conducting with NMOS in the three state circuit that K links to each other, cause the external capacitor discharge, output Output becomes high potential.When capacitor discharge reached the low evoked potential of Schmidt trigger SCHMITT1 and SCHMITT2, h, nb and a became high potential, and then the state of latch Latch is changed, and the upper end is 0, and the lower end is 1.When the lower end of latch Latch was 1, K became electronegative potential, end with NMOS pipe in the three state circuit that K end links to each other, and the L end still remained high potential, and external integrating capacitor C stops to discharge, and changes by outer meeting resistance R and charges.When the high evoked potential of Schmidt SCHMITT2 below integrating capacitor R charges to, h becomes electronegative potential, causes output to become electronegative potential; Simultaneously, L becomes electronegative potential, makes PMOS pipe conducting in the three state circuit 2 that links to each other with L, and to external integrating capacitor C charging, quickens to make it reach VDD.

In addition, the clear terminal signal also can be used to trigger labile state, and operating principle is similar to the above.

In a word, the present invention has improved antijamming capability and the reliability of circuit, and has low-power consumption, power supply electricity Press wide ranges, antijamming capability strong, the pulsewidth of generation such as can regulate at the advantage, can be widely used in shaping pulse, Time-delay (generation lags behind the output pulse of trigger impulse) and the regularly (pulse of generation certain hour width Signal).

Claims

1, a kind of CMOS monostable circuit, it is characterized in that comprising: integrating circuit, three state circuit, tri-state control circuit and logic output circuit, have input, clear terminal and output, the control input of three state circuit is produced by tri-state control circuit, and tri-state control circuit produces control signal according to the state of integrating circuit; Tri-state control circuit adopts two Schmidt triggers that the state of integrating circuit is sampled, and produces the required control signal of three state circuit according to sampled result through logical operation; By the output of logic output circuit, the logic output circuit is not connected with integrating circuit the output signal of two Schmidt triggers generations in the tri-state control circuit after the interrelated logic computing simultaneously.

2, CMOS monostable circuit according to claim 1 is characterized in that: described integrating circuit is made up of sheet outer resistance and capacitances in series.

3, CMOS monostable circuit according to claim 1 is characterized in that: described three state circuit is made of PMOS and nmos pass transistor serial connection.

4, CMOS monostable circuit according to claim 1, it is characterized in that: described tri-state control circuit comprises: latch, two Schmidt triggers and logical block, two Schmidt triggers are sampled to the state of integrating circuit, send in the latch, through producing the control signal of three state circuit after the logical block, produce logic output signal simultaneously and deliver to the output of logic output circuit.

5, CMOS monostable circuit according to claim 4, it is characterized in that: described latch comprises two NAND gate, 4 inputs are arranged, wherein first input of first NAND gate is through producing with computing by the output of second NAND gate and second input signal, and another input of first NAND gate is by other two input signals, and promptly the third and fourth input signal exclusive disjunction obtains.