CN204305043U - A kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting - Google Patents
A kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting Download PDFInfo
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Abstract
The utility model discloses a kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting.Comprise synchronization module basic time: be provided with real-time timepiece chip, real-time timepiece chip sends interruption pulse signal and wakes power down signal processing module up before and after time integral point; Comprise power down signal processing module: receive interruption pulse signal sends and wakes exact time synchronization module up; And receive the audio signal of exact time synchronization module and carry out A/D sampling, to sending integral point signal after sampled-data processing to synchronization module basic time, realize time synchronized; Comprise exact time synchronization module: wake up after receive interruption pulse signal, receive FM broadcast singal, FM broadcast singal is demodulated into audio signal and sends to power down signal processing module.The utility model is used for the time synchronized in radio sensing network, and hardware cost is low, and the scope of application is wide, and low power consumption high-precision, service time is long.
Description
Technical field
The utility model relates to a kind of radio sensing network time synchronized circuit, particularly relates to a kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting of integrated circuit fields.
Background technology
Wireless sensor network (Wireless Sensor Networks, WSN) be current that receive much concern, relate to the integrated hot research field, forward position of multidisciplinary height intersection, knowledge height.Wireless sensor network can obtain objective physical information, has very wide application prospect.In wireless sensor network application, time synchronized is important component part, and Data Fusion of Sensor, sensor node self poisoning etc. all require that internodal clock keeps synchronous.
The method being widely used in radio sensing network time synchronized at present mainly contains GPS(Global Positioning System)) and NTP (Network Time protocol).GPS has quite high synchronization accuracy, but its cost is higher, energy consumption comparatively large and also under rugged environment synchronization accuracy can be greatly affected.NTP is the synchronous agreement of the enterprising row clock of Internet, and when it can realize high-precision computer school on network, but it belongs to computation-intensive, has very large computing cost.In WSN application, sensor node has strict requirement to power consumption, and require to keep less profile and cheap cost to be disposed in a large number as far as possible, its deployed environment is often the inaccessible adverse circumstances of ordinary person, this makes the maintenance after disposing normally impossible, and the time synchronized obviously GPS and NTP being used for WSN is difficult.
Summary of the invention
In order to solve Problems existing in background technology, the purpose of this utility model is to propose a kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting, when carrying out integral point school, the time signal of FM frequency modulation broadcasting is used to realize time synchronized, low power consumption high-precision, can be used for the time synchronized of radio sensing network.
The technical solution adopted in the utility model comprise synchronization module basic time, power down signal processing module and school time synchronization module:
Comprise synchronization module basic time: be provided with real-time timepiece chip, real-time timepiece chip sends interruption pulse signal and wakes power down signal processing module up before and after time integral point;
Comprise power down signal processing module: after receive interruption pulse signal, send synchronization module when FM enable signal wakes school up; And when receiving school synchronization module audio signal and carry out A/D sampling, to sending integral point correcting delay signal after sampled-data processing to synchronization module basic time, realize time synchronized;
Synchronization module when comprising school: be waken up after receiving FM enable signal, start to receive FM broadcast singal, FM broadcast singal is demodulated into FM audio signal and sends to power down signal processing module.
Described synchronization module basic time adopts real-time timepiece chip, and real-time timepiece chip receives calibrating signal by I2C communication interface, sends interruption pulse signal by INT pin.
Described power down signal processing module adopts model to be the low-power microprocessor of EFM32TG842 and crystal oscillating circuit thereof and mu balanced circuit, the low-power microprocessor of EFM32TG842 is provided with I2C communication interface and A/D translation interface, the low-power microprocessor of EFM32TG842 is connected with synchronization module basic time by I2C communication interface, receive interruption pulse signal and transmission integral point signal; Be connected with synchronization module during school by A/D translation interface, received audio signal.
The FM on-off circuit that during described school, synchronization module comprises FM receiving circuit and is connected with FM receiving circuit, FM receiving circuit comprises chip TA7792 and FM frequency-discriminating circuit, FM local oscillation circuit, FM selective frequency amplifier circuit and FM intermediate frequency filtering circuit; FM broadcast singal successively after FM selective frequency amplifier circuit, chip TA7792, FM local oscillation circuit and FM intermediate frequency filtering circuit, then exports FM audio signal after chip TA7792 and FM frequency-discriminating circuit, and FM enable signal is input to FM on-off circuit.
Compared with background technology, the beneficial effect that the utility model has is:
1. the utility model adopts and carries out high-accuracy network time synchronized based on FM frequency modulation broadcasting time signal, and hardware cost is low, and the scope of application is wide.
2. the utility model adopts low-power consumption components and parts, and overall energy consumption is low, and can use powered battery, service time is long.
3. the utility model adopts the sample frequency of 50kHz, and correcting delay precision is high, and time accuracy can reach 20us.
4. the utility model can be used for the time synchronized in radio sensing network.
Accompanying drawing explanation
Fig. 1 is the connection block diagram of the utility model module.
Fig. 2 is general principles block diagram of the present utility model.
Fig. 3 is synchronization module circuit diagram basic time.
Fig. 4 is power down signal processing module circuit diagram.
Synchronization module circuit diagram when Fig. 5 is school.
Fig. 6 is the circuit diagram of FM frequency-discriminating circuit.
Fig. 7 is the circuit diagram of FM local oscillation circuit.
Fig. 8 is the circuit diagram of FM selective frequency amplifier circuit.
Fig. 9 is the circuit diagram of FM intermediate frequency filtering circuit.
Figure 10 is the circuit diagram of FM on-off circuit.
Figure 11 is the desirable time signal format figure of FM frequency modulation broadcasting.
Detailed description of the invention
Below in conjunction with drawings and Examples, the utility model is further described.
As depicted in figs. 1 and 2, when the utility model comprises synchronization module I basic time, power down signal processing module II and school synchronization module III, power down signal processing module II respectively with basic time synchronization module I, rectify time synchronization module III:
Comprise synchronization module I basic time: be provided with real-time timepiece chip, real-time timepiece chip sends interruption pulse signal and wakes power down signal processing module II up before and after time integral point;
Comprise power down signal processing module II: after receive interruption pulse signal, send synchronization module III when FM enable signal wakes school up; And when receiving school synchronization module III audio signal and carry out A/D sampling, to sending integral point correcting delay signal after sampled-data processing to synchronization module I basic time, realize time synchronized;
Synchronization module III when comprising school: wake up after receiving FM enable signal, start to receive FM broadcast singal, FM broadcast singal is demodulated into FM audio signal and sends to power down signal processing module II.
Basic time synchronization module I, power down signal processing module II and school time synchronization module III be connected with battery and power.
Above-mentioned synchronization module I employing basic time real-time timepiece chip, real-time timepiece chip receives calibrating signal by I2C communication interface, sends interruption pulse signal by INT pin.
Above-mentioned power down signal processing module II adopts model to be the low-power microprocessor of EFM32TG842 and crystal oscillating circuit thereof and mu balanced circuit, the low-power microprocessor of EFM32TG842 is provided with I2C communication interface and A/D translation interface, the low-power microprocessor of EFM32TG842 is connected with synchronization module I basic time by I2C communication interface, receive interruption pulse signal and send integral point signal, is used for calibrating the time of synchronization module basic time; Be connected with synchronization module III during school by A/D translation interface, received audio signal, is completed by synchronization module III during school and samples and signal transacting to the A/D of FM broadcast singal.This low-power microprocessor has low-power consumption energy saver mode, to reduce power consumption.
The FM on-off circuit that during above-mentioned school, synchronization module III comprises FM receiving circuit and is connected with FM receiving circuit, FM receiving circuit comprises chip TA7792 and FM frequency-discriminating circuit, FM local oscillation circuit, FM selective frequency amplifier circuit and FM intermediate frequency filtering circuit; As shown in Figure 10, FM frequency-discriminating circuit, FM local oscillation circuit, FM selective frequency amplifier circuit and FM intermediate frequency filtering circuit as shown in figs. 6-9, are all connected with chip TA7792 FM on-off circuit, FM local oscillation circuit and FM intermediate frequency filtering circuit.FM broadcast singal exports FM audio signal successively after FM selective frequency amplifier circuit, chip TA7792, FM local oscillation circuit, FM intermediate frequency filtering circuit, chip TA7792 and FM frequency-discriminating circuit, and FM enable signal is input to FM on-off circuit.Specifically, FM broadcast singal is after the frequency-selecting of FM frequency selection circuit is amplified, input TA7792 chip, 10.7MHz intermediate-freuqncy signal is demodulated into through local oscillation circuit, after intermediate frequency filtering circuit filtering, input TA7792 chip, is exported as FM audio signal by frequency-discriminating circuit demodulation, then FM audio signal is sent to power down signal processing module II.
According to the feature of FM frequency modulation broadcasting time signal, through signal detection and pattern match, the time after correction is sent to synchronization module I basic time by power down signal processing module II, and then realizes the time synchronized of synchronization module basic time; Synchronization module III during the basic time of synchronization module I timing wake-up school, after time synchronized terminates, power down signal processing module II enters park mode, thus reduces system power dissipation.
The ringing at every hour signal of FM frequency modulation broadcasting, i.e. the FM broadcast singal of integral point time, being the audio signal of " five short is long ", by carrying out A/D sampling to audio signal, obtaining sampled audio signal data; Sampled data calculated and judges, differentiate audio signal in the integral point moment and produce integral point correcting delay signal, the time is carried out synchronously.
Specific embodiment of the utility model is as follows:
As shown in Figure 3, basic time synchronization module I: adopt DS3231 clock chip, DS3231 chip is connected with power down signal processing module II bus, DS3231 chip adopts I2C universal serial bus, i.e. bidirectional data line SDA and clock line SCL, the I2C serial bus port SDA pin of DS3231 chip and SCL pin need coupling to be connected to the I2C port of power down signal processing module II, in the utility model, DS3231 chip and power down signal processing module II connection layout are as Fig. 3, shown in Fig. 4 control chip, SDA pin in Fig. 3 is connected to the PA0 pin in Fig. 4, PA0 pin in Fig. 4 is I2C0_SDA port, SCL pin in Fig. 3 is connected to the PA1 pin in Fig. 4, PA1 pin in Fig. 4 is I2C0_SCL port, RST is the reset output terminal mouth of DS3231 chip, INT is the interrupt signal output pin of DS3231 chip, interrupt signal can be exported when clocked flip.When system starts, DS3231 chip is by the PA0 pin of INT pin timed sending interrupt signal to power down signal processing module II, thus synchronization module III when waking school up, in addition, power down signal processing module II sends correcting delay signal to the data pin SDA of DS3231 chip by PA0 pin, pass through PA1 pin tranmitting data register signal to the clock pins SCL of DS3231 chip simultaneously, realize the time synchronized to DS3231 chip.
Power down signal processing module II: adopt EFM32TG842 chip, inner integrated A/D modular converter, managing power consumption module and timing module, power down signal process can be realized, EFM32TG842 chip is connected with synchronization module III during school with synchronization module I basic time respectively as system core chip, connection layout is as Fig. 3, shown in Fig. 4 and Fig. 5, EFM32TG842 chip PE4 pin is connected with the FM on-off circuit of synchronization module III during school, when the PE4 pin output FM enable signal of EFM32TG842 chip is high level, FM on-off circuit is in conducting state, FM receiving circuit normally works, EFM32TG842 chip PD0 pin is connected with the AF pin of synchronization module III during school, this pin is ADC0 port, whole clock synchronization system carries out time synchronized work according to FM frequency modulation broadcasting time signal, during school, the time signal of the FM frequency modulation broadcasting received is converted into FM audio signal and sends to EFM32TG842 chip by synchronization module III, FM audio frequency time signal feature is five short length, audio frequency minor signal 800Hz, continue 0.25 second, audio frequency long signal 1600Hz, continue 0.5 second, desirable time signal format as shown in figure 11, after EFM32TG842 chip internal A/D modular converter carries out A/D conversion to the FM audio signal received, by detecting and pattern match, obtain high precision clock, the utility model adopts the A/D sampling clock of 50kHz to reach as high as 1MHz, time precision can reach 20us.
Synchronization module III during school: as shown in Fig. 6 ~ Figure 10, comprise FM receiving circuit and FM on-off circuit, as shown in Figure 10, FM on-off circuit is made up of FET M1 and triode Q1 and resistance R1, R2, the base stage of Q1 is connected with power down signal processing module II, when the PE4 pin output FM enable signal of the EFM32TG842 chip of power down signal processing module II is high level, FM on-off circuit is opened, and FM receiving circuit starts to receive FM broadcast singal.As shown in Fig. 6 ~ Figure 10, FM receiving circuit is made up of TA7792 chip and FM selective frequency amplifier circuit, FM local oscillation circuit, FM intermediate frequency filtering circuit and FM frequency-discriminating circuit.As shown in Figure 8, the LC oscillating circuit that FM selective frequency amplifier circuit is made up of inductance L 1, electric capacity C1, electric capacity C2 and TA7792 chip internal circuits are formed jointly, and wherein C2 is variable capacitance, can by the frequency resonant point regulating C2 to change frequency selection circuit; As shown in Figure 7, the LC oscillating circuit that FM local oscillation circuit is made up of inductance L 2, electric capacity C3, electric capacity C4 forms, and wherein C4 is variable capacitance, is changed the frequency receiving FM broadcast singal by the value changing C4; As shown in Figure 9, FM intermediate frequency filtering circuit is composed in series by two 10.7MHz intermediate-frequency filters; As shown in Figure 6, FM frequency-discriminating circuit comprises the LC oscillating circuit of inductance L 3 and electric capacity C5 composition.FM broadcast singal result FM frequency selection circuit and local oscillation circuit acting in conjunction, be demodulated into FM intermediate-freuqncy signal, and frequency is that 10.7MHz, FM intermediate-freuqncy signal is demodulated into FM audio signal by FM frequency-discriminating circuit again after FM filter circuit.TA7792 chip is connected with power down signal processing module II, pin connection layout is as shown in Fig. 4, Fig. 5, and TA7792 chip will receive after FM broadcast singal is demodulated into FM audio signal, by AF pin, FM audio signal is sent to the PD0 pin of power down signal processing module II, carries out A/D conversion.
Above-mentioned detailed description of the invention is used for explaining and the utility model is described; instead of the utility model is limited; in the protection domain of spirit of the present utility model and claim, any amendment make the utility model and change, all fall into protection domain of the present utility model.
Claims (4)
1., based on a low power consumption high-precision network time synchronization circuit for FM frequency modulation broadcasting, it is characterized in that:
Comprise synchronization module basic time (I): be provided with real-time timepiece chip, real-time timepiece chip sends interruption pulse signal and wakes power down signal processing module (II) up before and after time integral point;
Comprise power down signal processing module (II): after receive interruption pulse signal, send synchronization module (III) when FM enable signal wakes school up; And when receiving school synchronization module (III) audio signal and carry out A/D sampling, to sending integral point correcting delay signal after sampled-data processing to synchronization module basic time (I), realize time synchronized;
Synchronization module (III) when comprising school: be waken up after receiving FM enable signal, start to receive FM broadcast singal, FM broadcast singal is demodulated into FM audio signal and sends to power down signal processing module (II).
2. a kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting according to claim 1, it is characterized in that: described synchronization module basic time (I) adopts real-time timepiece chip, real-time timepiece chip receives calibrating signal by I2C communication interface, sends interruption pulse signal by INT pin.
3. a kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting according to claim 1, it is characterized in that: described power down signal processing module (II) adopts model to be the low-power microprocessor of EFM32TG842 and crystal oscillating circuit thereof and mu balanced circuit, the low-power microprocessor of EFM32TG842 is provided with I2C communication interface and A/D translation interface, the low-power microprocessor of EFM32TG842 is connected with synchronization module basic time (I) by I2C communication interface, receive interruption pulse signal and transmission integral point signal; Be connected with synchronization module during school (III) by A/D translation interface, received audio signal.
4. a kind of low power consumption high-precision network time synchronization circuit based on FM frequency modulation broadcasting according to claim 1, it is characterized in that: the FM on-off circuit that during described school, synchronization module (III) comprises FM receiving circuit and is connected with FM receiving circuit, FM receiving circuit comprises chip TA7792 and FM frequency-discriminating circuit, FM local oscillation circuit, FM selective frequency amplifier circuit and FM intermediate frequency filtering circuit; FM broadcast singal successively after FM selective frequency amplifier circuit, chip TA7792, FM local oscillation circuit and FM intermediate frequency filtering circuit, then exports FM audio signal after chip TA7792 and FM frequency-discriminating circuit, and FM enable signal is input to FM on-off circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104333431A (en) * | 2014-11-08 | 2015-02-04 | 浙江大学 | FM (Frequency Modulation) broadcast based low power consumption high accuracy network time synchronous circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104333431A (en) * | 2014-11-08 | 2015-02-04 | 浙江大学 | FM (Frequency Modulation) broadcast based low power consumption high accuracy network time synchronous circuit |
| CN104333431B (en) * | 2014-11-08 | 2017-02-15 | 浙江大学 | FM (Frequency Modulation) broadcast based low power consumption high accuracy network time synchronous circuit |
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