CN216531265U - Digital burr filtering circuit with adjustable width - Google Patents
Digital burr filtering circuit with adjustable width Download PDFInfo
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- CN216531265U CN216531265U CN202122568788.4U CN202122568788U CN216531265U CN 216531265 U CN216531265 U CN 216531265U CN 202122568788 U CN202122568788 U CN 202122568788U CN 216531265 U CN216531265 U CN 216531265U
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Abstract
The utility model provides a digital burr filtering circuit with adjustable width, which comprises: the input end of the first D flip-flop inputs a signal, and the CLK end of the first D flip-flop inputs a sampling clock signal; the input end of the second D trigger is electrically connected with the output end of the first D trigger, and the CLK end of the second D trigger is electrically connected with the CLK end of the first D trigger; and a first input end of the selector is electrically connected with an output end of the second D trigger. The digital burr filtering circuit with adjustable width provided by the utility model has the advantages that the filtering width is adjustable, the register turnover of the counter is reduced through the control logic of the counter, the power consumption is reduced, the circuit structure is simple, the scale is small, the interface is clear, and the system integration and the later maintenance are easy.
Description
Technical Field
The utility model relates to the technical field of digital integrated circuits, in particular to a digital burr filtering circuit with adjustable width.
Background
Because digital burrs are easy to generate at an input port of a chip or an internal combined digital logic output place, at present, a method for filtering the digital burrs mainly uses periodic sampling with certain frequency or a counter to measure the effective width of a signal to distinguish and filter the digital burrs, wherein the method for periodic sampling with certain frequency has irrational property, when the width of the burrs is less than the period of a sampling clock, the sampling burrs have randomness, the randomness can be destructively attacked in the mass production stage of the chip, and the randomness is not easy to reappear in the test stage of the chip; on the other hand, when the width of the burr is larger than the sampling period, the burr signal with a certain width is eliminated by using the counting principle, and as long as the digital burr filtering circuit is enabled, the register of the counter is always turned over, so that the power consumption of the circuit is large.
SUMMERY OF THE UTILITY MODEL
The utility model provides a width-adjustable digital burr filtering circuit, and aims to solve the problems that a register of a counter can be always turned over and the power consumption of the circuit is large as long as the traditional digital burr filtering circuit is enabled.
In order to achieve the above object, an embodiment of the present invention provides a digital glitch filtering circuit with adjustable width, including:
the input end of the first D flip-flop is inputted with a signal, and the CLK end of the first D flip-flop is inputted with a sampling clock signal;
the input end of the second D flip-flop is electrically connected with the output end of the first D flip-flop, and the CLK end of the second D flip-flop is electrically connected with the CLK end of the first D flip-flop;
a first input end of the selector is electrically connected with an output end of the second D trigger;
and the input end of the third D flip-flop is electrically connected with the output end of the selector, the CLK end of the third D flip-flop is electrically connected with the CLK end of the second D flip-flop, and the output end of the third D flip-flop is electrically connected with the second input end of the selector.
Wherein, still include:
and a first input end of the first comparator is electrically connected with an output end of the first D trigger, and a second input end of the first comparator is electrically connected with an output end of the second D trigger.
Wherein, still include:
and a first input end of the second comparator is electrically connected with the output end of the third D trigger, and a second input end of the second comparator is electrically connected with the output end of the first D trigger.
Wherein, still include:
and a first input end of the third comparator is electrically connected with an output end of the third D trigger, and a second input end of the third comparator is electrically connected with an output end of the second D trigger.
Wherein, still include:
the CLK end of the counter is electrically connected with the CLK end of the third D trigger, the Reset end of the counter inputs a Reset signal, the first input end of the counter is electrically connected with the output end of the first comparator, the second input end of the counter is electrically connected with the output end of the second comparator, the third input end of the counter is electrically connected with the output end of the third comparator, the fourth input end of the counter inputs a second zero clearing signal, and the output end of the counter is electrically connected with the third input end of the selector.
The scheme of the utility model has the following beneficial effects:
the digital burr filtering circuit with the adjustable width, disclosed by the embodiment of the utility model, has the advantages that the filtering width is adjustable, the register turnover of the counter is reduced through the control logic of the counter, the power consumption is reduced, the circuit structure is simple, the scale is small, the interface is clear, and the system integration and the later maintenance are easy.
Drawings
FIG. 1 is a schematic structural view of the present invention;
fig. 2 is a waveform diagram of the present invention.
[ description of reference ]
1-a first D flip-flop; 2-a second D flip-flop; 3-a selector; 4-a third D flip-flop; 5-a first comparator; 6-a second comparator; 7-a third comparator; 8-a counter.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The utility model provides a width-adjustable digital burr filtering circuit, aiming at the problems that a register of a counter can be always turned over and the power consumption of the circuit is large as long as the conventional digital burr filtering circuit is enabled.
As shown in fig. 1 to 2, an embodiment of the present invention provides a width-adjustable digital glitch filtering circuit, including: the input end of the first D flip-flop 1 inputs a signal, and the CLK end of the first D flip-flop 1 inputs a sampling clock signal; the input end of the second D flip-flop 2 is electrically connected with the output end of the first D flip-flop 1, and the CLK end of the second D flip-flop 2 is electrically connected with the CLK end of the first D flip-flop 1; a selector 3, wherein a first input end of the selector 3 is electrically connected with an output end of the second D flip-flop 2; and an input end of the third D flip-flop 4 is electrically connected with the output end of the selector 3, a CLK end of the third D flip-flop 4 is electrically connected with a CLK end of the second D flip-flop 2, and an output end of the third D flip-flop 4 is electrically connected with the second input end of the selector 3.
Wherein, still include: and a first input end of the first comparator 5 is electrically connected with the output end of the first D flip-flop 1, and a second input end of the first comparator 5 is electrically connected with the output end of the second D flip-flop 2.
Wherein, still include: and a second comparator 6, wherein a first input end of the second comparator 6 is electrically connected with an output end of the third D flip-flop 4, and a second input end of the second comparator 6 is electrically connected with an output end of the first D flip-flop 1.
Wherein, still include: and a third comparator 7, wherein a first input end of the third comparator 7 is electrically connected with an output end of the third D flip-flop 4, and a second input end of the third comparator 7 is electrically connected with an output end of the second D flip-flop 2.
Wherein, still include: the CLK end of the counter 8 is electrically connected to the CLK end of the third D flip-flop 4, the Reset end of the counter 8 inputs a Reset signal, the first input end of the counter 8 is electrically connected to the output end of the first comparator 5, the second input end of the counter 8 is electrically connected to the output end of the second comparator 6, the third input end of the counter 8 is electrically connected to the output end of the third comparator 7, the fourth input end of the counter 8 inputs a second Reset signal, and the output end of the counter 8 is electrically connected to the third input end of the selector 3.
In the digital burr filtering circuit with adjustable width according to the embodiment of the present invention, a Reset signal is input to the Reset end of the counter 8, and the count value of the counter 8 is cleared; after the reset of the counter 8 is completed, the digital burr filtering circuit with adjustable width starts to work, a sampling clock signal is input into the first D trigger 1, the second D trigger 2, the third D trigger 4 and the CLK end of the counter 8, a serial input signal to be transmitted is input into the input end of the first D trigger 1, the count value of the counter 8 is set, wherein the count value of the counter 8 is the width of burrs to be filtered, the unit of the numerical value of the width of the burrs is one sampling clock period, when the effective width of the input signal is smaller than the numerical value of the width of the burrs, the input signal can be regarded as the burr signal, and the numerical value of the width of the burrs can be set to 1 to (2)n-1) clock cycles, after the serial input signal is input, the signal after filtering the glitch is output after the sampling by the first D flip-flop 1, the second D flip-flop 2 and the third D flip-flop 4, the counter 8 acts synchronously according to the output levels of the first D flip-flop 1, the second D flip-flop 2 and the third D flip-flop 4, and when the output level of the first D flip-flop 1 and the output level of the third D flip-flop 4When the output levels are not consistent, the second comparator 6 generates a first enable signal; when the level output by the second D flip-flop 2 and the level output by the third D flip-flop 4 are not identical, the third comparator 7 generates a second enable signal; when the second comparator 6 generates an enable signal or the third comparator 7 generates an enable signal, the counter 8 starts counting; when the level output by the first D flip-flop 1 is inconsistent with the level output by the second D flip-flop 2, the first comparator 5 generates a first clear signal; when the actual count value of the counter 8 reaches the set count value, inputting a second clear signal into the counter 8; when the first zero clearing signal or the second zero clearing signal is effective, the counter 8 is cleared, and the priority of the zero clearing signal is higher than that of the enabling signal of the counter 8; when the count value of the counter 8 reaches the set count value, the counter 8 generates a data output enable signal, the data output enable signal is input to the third input end of the selector 3, when the data output enable signal is valid, the selector 3 outputs a signal output after sampling by the second D flip-flop 2, and when the data output enable signal is invalid, the selector 3 outputs a signal output after sampling by the third D flip-flop 4.
In the digital burr filtering circuit with adjustable width according to the embodiment of the present invention, a serial input signal is sampled and output through the first D flip-flop 1, the second D flip-flop 2, and the third D flip-flop 4, an output of the third D flip-flop 4 is controlled by a data output enable signal of the counter 8, and when the data output enable signal output by the counter 8 is valid, the third D flip-flop 4 outputs the content of the second D flip-flop 2; the counter 8 has two functions of zero clearing and counting, when the counter 8 is in a zero clearing state, the count value of the counter 8 is zero, and when the counter 8 is in a counting state, the count value of the counter 8 is increased by 1 at the effective edge of each clock cycle; condition for clearing the counter 8: when the first comparator 5 detects that the output level of the first D flip-flop 1 is inconsistent with the output level of the second D flip-flop 2, the count value of the counter 8 is cleared, or when the count value of the counter 8 reaches a set count period value, the count value of the counter 8 is cleared; condition for the counter 8 to start counting: when the second comparator 6 detects that the output level of the first D flip-flop 1 is inconsistent with the output level of the third D flip-flop 4 or when the first comparator detects that the output level of the second D flip-flop 2 is inconsistent with the output level of the third D flip-flop 4, the counter 8 is enabled and the counter 8 starts counting.
In the digital burr filtering circuit with adjustable width according to the embodiment of the present invention, the digital burr filtering circuit with adjustable width is integrated into a digital signal processing chip, an input terminal of the first D flip-flop 1 in the digital burr filtering circuit with adjustable width is electrically connected to an input terminal of the chip, and a Reset terminal of the counter 8 in the digital burr filtering circuit with adjustable width is electrically connected to a Reset terminal of the chip; the CLK end of the device in the digital burr filtering circuit with adjustable width is input into a system clock of a chip; the output end of the third D trigger 4 is electrically connected with a CPU of the digital signal processing chip; the set count value of the counter 8 is 4 bits and the value is 15, in fig. 2, clk is a sampling clock, cnt _ p is the counting state of the counter 8, the format shown in fig. 2 is a 16-ary number, in fig. 2, the signal name 1 is a serial input signal, the signal name 2 is a signal output by the first D flip-flop 1, the signal name 3 is a signal output by the second D flip-flop 2, the signal name 4 is a second enable signal of the third comparator 7, the signal name 5 is a signal output by the third D flip-flop 4, the signal name 6 is a first enable signal of the second comparator 6, the signal name 7 is a data output enable signal output by the counter 8, the signal name 8 is a second clear signal, the signal name 9 is a first clear signal of the first comparator 5, before the time point T1, the serial input signal is consistent with the level of the signal output by the third D flip-flop 4 after filtering the glitch number, by observing the counting state cnt _ p, the register of the counter 8 is not turned over, the power consumption is reduced, at the time of T1, the serial input signal jumps from low level to high level, the first D flip-flop 1 performs sampling, the first D flip-flop 1 outputs high level, the first enable signal output by the second comparator 6 becomes high level, but at this time, the serial input signal is not subjected to secondary sampling, so the first clear signal is valid, and since the priority of the clear signal is higher than that of the enable signal of the counter 8, the cnt _ p does not start counting; at time T2, after the second D flip-flop 2 samples and outputs a high level, the first clear signal is pulled low, at this time, the counter 8 is enabled to be valid, the counter 8 starts to count, at time T3, cnt _ p counts to f (the set count value of the counter 8), at this time, the data output enable signal output by the counter 8 is pulled high, at time T4, the signal output by the third D flip-flop 4 is pulled high, transmission from the serial input signal to the output signal is completed, at this time, the counter 8 is cleared, and at this time, the counter 8 is enabled to be closed.
The digital burr filtering circuit with the adjustable width, disclosed by the embodiment of the utility model, has the advantages that the filtering width is adjustable, the register turnover of the counter is reduced through the control logic of the counter, the power consumption is reduced, the circuit structure is simple, the scale is small, the interface is clear, and the system integration and the later maintenance are easy.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the utility model as defined in the appended claims.
Claims (5)
1. A digital glitch filtering circuit of adjustable width, comprising:
the input end of the first D flip-flop is inputted with a signal, and the CLK end of the first D flip-flop is inputted with a sampling clock signal;
the input end of the second D flip-flop is electrically connected with the output end of the first D flip-flop, and the CLK end of the second D flip-flop is electrically connected with the CLK end of the first D flip-flop;
a first input end of the selector is electrically connected with an output end of the second D trigger;
and the input end of the third D flip-flop is electrically connected with the output end of the selector, the CLK end of the third D flip-flop is electrically connected with the CLK end of the second D flip-flop, and the output end of the third D flip-flop is electrically connected with the second input end of the selector.
2. The adjustable-width digital glitch rejection circuit of claim 1, further comprising:
and a first input end of the first comparator is electrically connected with an output end of the first D trigger, and a second input end of the first comparator is electrically connected with an output end of the second D trigger.
3. The adjustable-width digital glitch rejection circuit of claim 2, further comprising:
and a first input end of the second comparator is electrically connected with the output end of the third D trigger, and a second input end of the second comparator is electrically connected with the output end of the first D trigger.
4. The adjustable-width digital glitch rejection circuit of claim 3, further comprising:
and a first input end of the third comparator is electrically connected with an output end of the third D trigger, and a second input end of the third comparator is electrically connected with an output end of the second D trigger.
5. The adjustable-width digital glitch rejection circuit of claim 4, further comprising:
the CLK end of the counter is electrically connected with the CLK end of the third D trigger, the Reset end of the counter inputs a Reset signal, the first input end of the counter is electrically connected with the output end of the first comparator, the second input end of the counter is electrically connected with the output end of the second comparator, the third input end of the counter is electrically connected with the output end of the third comparator, the fourth input end of the counter inputs a second zero clearing signal, and the output end of the counter is electrically connected with the third input end of the selector.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122568788.4U CN216531265U (en) | 2021-10-25 | 2021-10-25 | Digital burr filtering circuit with adjustable width |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122568788.4U CN216531265U (en) | 2021-10-25 | 2021-10-25 | Digital burr filtering circuit with adjustable width |
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| CN216531265U true CN216531265U (en) | 2022-05-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117200765A (en) * | 2023-11-06 | 2023-12-08 | 灿芯半导体(成都)有限公司 | Clock selection circuit capable of eliminating burrs |
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2021
- 2021-10-25 CN CN202122568788.4U patent/CN216531265U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117200765A (en) * | 2023-11-06 | 2023-12-08 | 灿芯半导体(成都)有限公司 | Clock selection circuit capable of eliminating burrs |
| CN117200765B (en) * | 2023-11-06 | 2024-01-23 | 灿芯半导体(成都)有限公司 | Clock selection circuit capable of eliminating burrs |
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