CN202798579U - Tracking oscillator circuit and controller local area network bus system - Google Patents
Tracking oscillator circuit and controller local area network bus system Download PDFInfo
- Publication number
- CN202798579U CN202798579U CN 201120578226 CN201120578226U CN202798579U CN 202798579 U CN202798579 U CN 202798579U CN 201120578226 CN201120578226 CN 201120578226 CN 201120578226 U CN201120578226 U CN 201120578226U CN 202798579 U CN202798579 U CN 202798579U
- Authority
- CN
- China
- Prior art keywords
- oscillator
- circuit
- frequency
- bus
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model relates to a tracking oscillator circuit and a controller local area network bus system so as to be used for HS-CAN bus clock recovery. Specifically, the utility model provides a tracking oscillator circuit which is configured to be used for recovering the clock frequency of the bus. The tracking oscillator circuit comprises a detector-along circuit used for detecting state transition of received data signals, and an oscillator core circuit which is configured to be used for generating an internal oscillator of a first frequency, wherein the first frequency is synchronous with a second frequency of the received data signals.
Description
Technical field
Technical field described here relates generally to pierce circuit, and more specifically, relates to the pierce circuit for the clock and data recovery of HS-CAN bus system.
Background technology
Pierce circuit produces the electronic signal that repeats.Pierce circuit is widely used in innumerable application.Especially, pierce circuit can use in the circuit that recovers CAN (controller local area network) bus clock.CAN is a kind of how main broadcast serial bus standard, is used for connecting the electronic circuit such as transducer, actuator and other control devices.
In the CAN network, tranmitting data register not during transfer of data.The CAN node monitors the CAN bus, and the processing bit timing logic (BTL) relevant with the sending and receiving of data.The CAN node recovers CAN bus clock and data with pierce circuit.
The evolution standard of the CAN bus such as HS-CAN (high-speed controller local area network (LAN)) may require to have the more CAN bus monitoring of high accuracy (for example, 4.5%), and may also will improve the frequency of bus.For example, HS-CAN introduces and wakes frame up, is used for node is become active state from low power state.For fear of being transformed into mistake the request of active state such as missing from low power state, accurately monitor it is essential.In addition, the HS-CAN bus monitoring can improve the oscillator frequency requirement (for example, 16MHz).
In order to realize accurate supervision, the traditional circuit that need to satisfy the high accuracy requirement can carry out over-sampling to the serial data of importing into.Then can estimate for the data transaction position stream, and then can be from over-sampling extracting data valid data position.BTL is normally known in traditional C AN controller circuitry, carries out over-sampling in order to utilize than the much higher frequency of baud rate in using.For over-sampling, need to have the clock of the one-tenth overtones band more much higher than CAN bus frequency.
In order to realize high accuracy, traditional C AN node can comprise high precision oscillator.This high precision oscillator can dispose for operating with the frequency that fully is higher than CAN bus data rate.High precision oscillator (for example, quartz, pottery resonance etc.) may be introduced higher cost.And, for to the data over-sampling and usually known with the higher frequencies of operation pierce circuit be to increase current consumption requirements.Higher current drain is considered to key parameter usually, particularly in the HS-CAN transceiver of realizing selective wake-up.
The utility model content
Execution mode aims to provide a kind of low frequency oscillator tracking, and it monitors the CAN bus exactly, and recovers the clock frequency of bus and received the CAN bus data based at least one the state conversion that receives the CAN bus data.This oscillator tracking circuit is directly from deriving sampling clock with the CAN bus data with the internal oscillator of same frequency operation.The oscillator tracking circuit provides programmable duty cycle for this sampling clock, in order to generate the CAN bus data.
According to an execution mode, a kind of method of the clock frequency for recovering the CAN bus is provided, the method comprises: reception of data signal, wherein this data-signal comprises at least one state conversion; The detected state conversion; And the frequency of regulating the clock signal of pierce circuit generation, wherein this frequency is conditioned when detecting the state conversion, and regulating frequency is for the clock frequency of recovering the CAN bus.
According to an execution mode, the method further comprises: calculate the reboot time that is used for the replacement oscillator, and generate synchronizing signal based on the reboot time that calculates, wherein this synchronizing signal configuration is used for restarting oscillator when detecting the state conversion.
According to an execution mode of the present utility model, the method further comprises: calculate the make-up time being used for the capacity cell charging and discharging to pierce circuit, but so that frequency is conditioned and the frequency of operation of pierce circuit is maintained.
According to an execution mode, the method further comprises: when detecting the state conversion, determine increase and the reduction of frequency based on the signal level of clock signal.
According to an execution mode, the method further comprises: the sampled signal that generates the sampled point of determining the data accepted signal, wherein the duty ratio of this sampled signal is programmable, and the sampling of data accepted signal recovers at least one CAN position of this data accepted signal.
According to an execution mode, the state conversion is trailing edge.
According to an execution mode, a kind of oscillator tracking Circnit Layout is used for recovering the clock frequency of bus, and this circuit comprises: along detector circuit, for detection of the state conversion of data accepted signal; The oscillator core circuit, configuration is used for generating the internal oscillator of first frequency, and wherein the second frequency of this first frequency and data accepted signal is synchronous.
According to an execution mode, this oscillator core circuit comprises: by first group of switch of the first state of synchronizing signal control, and by second group of switch of the second state of synchronizing signal control, wherein this oscillator is reset during the first state, and the free-running operation during the second state of this oscillator.
According to an execution mode, synchronizing signal is generated by the synchronous generator circuit that is coupled to along detector circuit.
According to an execution mode, the oscillator tracking circuit further comprises: follow the tracks of the sum counter circuit, be used for regulating the frequency of internal oscillator.
According to an execution mode, the oscillator tracking circuit further comprises: sample circuit, configuration are used in programmable sample point the data accepted signal being sampled.
According to an execution mode, a kind of CAN bus system comprises: the CAN bus, and it is coupled at least one from equipment with main equipment; This main equipment comprises: clock generator is suitable for being provided for the clock frequency of CAN bus; And transmitting apparatus, be suitable for sending the data with this clock frequency via the CAN bus; This at least one comprise from equipment: receiver is used for receiving the data on the bus; And the oscillator tracking circuit, configuration is used for recovering the clock frequency of bus, and this oscillator tracking circuit comprises: along detector circuit, for detection of the state conversion of data accepted signal; And the oscillator core circuit, configuration is used for generating the internal oscillator of first frequency, and wherein the second frequency of this first frequency and data accepted signal is synchronous.
According to an execution mode, first frequency equals second frequency.
According to an execution mode, the oscillator tracking circuit further comprises compensating circuit, is used for the capacity cell charging and discharging to the oscillator core circuit.
According to an execution mode, capacity cell has value 2pF.
Description of drawings
In the accompanying drawings, the assembly that is equal to or substantially is equal to of each shown in each figure is represented by similar reference number.Being clear purpose, is not to have marked each assembly in each figure.
In the accompanying drawings:
Fig. 1 shows the schematic block diagram of execution mode of the CAN bus system of the execution mode with oscillator tracking circuit.
Fig. 2 shows the schematic block diagram of the execution mode of oscillator tracking circuit.
Fig. 3 shows oscillator tracking circuit signal execution mode regularly.
Fig. 4 shows the schematic block diagram of the execution mode of traditional oscillators.
Fig. 5 shows the schematic block diagram of execution mode of the oscillator core circuit of oscillator tracking circuit.
Embodiment
Technology design described here is used for the pierce circuit of the clock and data recovery of CAN bus system.Especially, a kind of oscillator tracking circuit has been described.This oscillator tracking Circnit Layout is used for monitoring exactly the CAN bus, and recovers the clock frequency of bus and received the CAN bus data based at least one the state conversion that receives the CAN bus data.
Fig. 1 shows the schematic block diagram of execution mode of the CAN bus system 100 of the execution mode with oscillator tracking circuit 130.CAN bus system 100 shows CAN bus 150, main equipment 110, and two from equipment 120.CAN bus 150 is coupled to main equipment 110 from equipment 120.Only showing two is for the reduced representation Fig. 1 from equipment.Main equipment 110 has clock generator circuit 112 and a transmitting apparatus 114.Clock generator circuit 112 provides CAN CLK and CAN BIT.Transmitting apparatus 114 sends CAN BIT via RXD on CAN bus 150.
Each has receiving equipment 122 and oscillator tracking circuit 130 from equipment 120.Receiving equipment 122 receives the RXD 124 that is sent via CAN bus 150 by main equipment 110.According to an execution mode, CAN bus 150 is implemented as open collector.RXD 124 can comprise " dominant " and " recessiveness " CAN position, and wherein dominant is that logical zero and recessiveness are logical ones.Dominant position can be asserted by creating the voltage of crossing over lead-in wire, and does not assert in CAN bus 150 simply recessive position.
According to an execution mode, has at least one oscillator tracking circuit 130 from equipment 120.Fig. 2 shows the execution mode of oscillator tracking circuit 130, and its configuration is used for recovering CAN CLK based at least one the state conversion that receives CAN data RXD 124
126 frequency and data CAN BIT 128.
As shown in Figure 2, oscillator tracking circuit 130 comprise fine setting (trimming) circuit 200, oscillator core circuit 202, along detector circuit 208, synchronously generator circuit 210, compensator circuit 218, follow the tracks of sum counter circuit 214 and sample circuit 206.Oscillator tracking 130 is unrestricted in this regard.
Fig. 2 illustrates, and input IBIAS 230 can provide bias current to trimming circuit 200.According to an execution mode, trimming circuit 200 configurations are used for the electric current of oscillator core circuit 202 is finely tuned.In one aspect, internal clocking 222 frequencies can be based on being finely tuned with step-length+/-0.3% with the electric current of step-length+/-0.3% fine setting.According to an execution mode, after fine setting, can be at the internal clocking 222 of room temperature generated frequency 500kHz+/-0.3%.
RXD 124 is inputs of oscillator tracking circuit 130.The baud rate of RXD 124 can be 500 kilobits/second, 250 kilobits/second and 125 kilobits/second.Oscillator core circuit 202 can dispose the internal clocking 222 for the frequency that generates RXD 124.According to an execution mode, can generate a plurality of internal clocking frequencies (for example, 500kHz, 250kHz, 125kHz).As shown in Figure 2, oscillator core circuit 202 can be coupled to divider circuit 204.Divider circuit 204 can dispose for generating phase clock 212, and wherein phase clock signal 212 has the one-tenth overtones band of internal clocking 222.According to an execution mode, phase clock signal 212 can have the double frequency of the frequency of internal clock signal 22.
As shown in Figure 2, RXD 124 is the input signals along detector 208.According to an execution mode, RXD 124 has at least one state conversion 302.Can carry out the detection that the state of RXD 124 is changed along detector circuit 208.Fig. 3 shows the execution mode of RXD 124 and the execution mode of state conversion 302.According to an execution mode, the state conversion can be trailing edge (for example, the conversion from the CAN recessive state to dominance condition).
Can dispose for the ring of filtering on the RXD 124 along detector circuit 208.Ring is known defect, when it can occur in RXD 124 transition status.The filtration of ring can be described to " blanking (blanking) ".By blanking RXD 124, can detect " true (true) " state conversion of RXD 124 along detector circuit 208.Can be coupled to synchronous generator circuit 210 along detector circuit 208, provide outgoing signaling 228 to synchronous generator circuit 210.Generator circuit 210 can be coupled to oscillator core circuit 202, compensator circuit 218 and follow the tracks of sum counter circuit 214 synchronously.
Can be used for generating synchronizing signal 226 by synchronous generator circuit along detector 208 outgoing signalings 228, its configuration is used for changing and restarting oscillator core circuit 202 at 302 o'clock detecting RXD 124 states.According to an execution mode, synchronizing signal 226 can be based on the trailing edge of RXD 124 and is generated.
According to another execution mode, synchronizing signal 226 can comprise that configuration is used at least one synchronizing signal of at least one switch element of control generator core circuit 202.According to another execution mode, synchronizing signal 226 can comprise that configuration is used for a plurality of signals of the switch element of control generator core circuit 202.According to another execution mode, synchronizing signal 226 can generate based on the reboot time that calculates.Fig. 3 shows the reboot time td 316 that calculates of synchronizing signal 226.
According to an execution mode, oscillator core circuit 202 can be based on the traditional oscillators circuit 400 that schematically shows in Fig. 4.This will can not describe traditional oscillators circuit 400 common known element and aspect.Yet, some aspect will be described, because its discussion with oscillator core circuit 202 is relevant.Current i Up 402 and iDn 404 represent charging current and discharging current.The free-running operation frequency of traditional oscillators circuit 400 can be expressed as:
f＝2*iBias/(C*V)，when?iUp＝iDn＝iBias
The free-running operation frequency is partly determined in the selection of the value C of capacity cell 414 and electromotive force V, and is as implied above.According to an execution mode, the value of C is 2pF, and the value of V is 5V, and the value of iBias is 2.5uA, and the free-running operation frequency f is 500kHz.
Fig. 5 schematically shows the oscillator core circuit 202 based on traditional oscillators circuit 400.Be similar to traditional oscillators circuit 400,404 pairs of capacity cell 414 charging and dischargings of iUp 402 and iDn are to produce internal clocking 222.
Yet oscillator core circuit 202 has been introduced shown switch element 502,518,508,522 and 510.As mentioned above, synchronizing signal 226 can comprise that configuration is used at least one synchronizing signal of at least one switch element of control generator core circuit 202.According to an execution mode, synchronizing signal 226 control switch elements 502,518,508,522 and 510 disconnection and closure state.
According on the other hand, switch element 508,510 and 518 closures, and switch element 502 and 522 disconnects so that by voltage 542 is coupled to GND () produce the Reset Status of internal clocking 222.Fig. 5 shows the switch element cut-off/close setting when internal clocking 222 is reset.According on the other hand, Reset Status occurs in during the reboot time td 316 of synchronizing signal 226 as shown in Figure 3.
According on the other hand, synchronizing signal 226 Closing Switch elements 502 and 522 and cut-off switch element 508,510 and 518 are so that the free-run state of internal clocking 222 can be generated.
According to an execution mode, when synchronizing signal 226 is in high state, shown in the td 316 among Fig. 3, then 530 be set to 532 and be coupled to electromotive force, 534 are coupled to GND, and 538 are coupled to electromotive force, 536 are coupled to GND, 540 are coupled to GND, and 542 are coupled to electromotive force, and internal oscillator clock 222 is coupled to GND.
According to another execution mode, when synchronizing signal 226 was converted to low state, then the voltage initial maintenance at 534 places was at GND, and 538 and 540 be coupled to electromotive force, 536 and 542 was coupled to GND simultaneously.Simultaneously, the lower voltage at 530 and 544 places, the voltage at 532 places increases, and oscillator core circuit 202 can be resumed and be free-run state, thereby makes 222 vibrations of internal oscillator signal.
According to another execution mode, synchronizing signal 226 comprises that configuration is for a plurality of synchronizing signals of the setting of the switch element of control generator core circuit 202, and this synchronizing signal is based on regularly, and this regularly provides: the voltage at 530 places equals the voltage at 532 places in 150 nanoseconds at least; When synchronizing signal 226 was converted to low state from high state, the voltage at 540 places was converted to GND from electromotive force, so that the voltage at 530 places is changed with identical direction when Reset Status is converted to the free-run state of internal clocking 222; When synchronizing signal 126 was converted to high state, 544 disconnected from 530 so that avoid overshoot current on 544 in the required time voltage at 544 places equal the voltage at 530 places; Synchronizing signal 226 control switch elements 508 than switch element 518 to 20 nanoseconds of the youthful and the elderly, so that the voltage transitions at 534 places is with the intended conversion direction (for example, increase or reduce) of control voltage 542.
According to an execution mode, programmable duty cycle can be determined the sampled point of 70-84% in the cycle of RXD 124, and can be to utilize step-length 2% programmable.According to an execution mode, sampled point can be RXD 124 cycle 75%.
The major function of sample circuit 206 is accurately RXD 124 to be sampled.According to an execution mode, sampled point can be programmable to 84% from 70% with step-length 2%.According to another execution mode, sampled point can generate at the rising edge place of phase signal 212.According to another execution mode, sampled signal 126 can utilize the tdc 320 of following calculating to generate:
tdc＝C*(V/(k*iUp))＝2*C*V/(k*iUp)
By changing k, can realize different sampled points.
According to an execution mode, td 316 should long enough, becomes the voltage that equals 532 places with the voltage of guaranteeing 530 places when synchronizing signal 226 is in high state.According to another execution mode, td 316 provides less than 1 microsecond
(td?316)+(tc?318)＝(t1?312)＝(t2?314)＝1us
Control to the error compensation of internal clocking 222 accuracy is provided, this error based on td 316 during the replacement of internal oscillator clock 222.According to an execution mode, capacity cell 414 is 2pF, and td is calculated as
td＝C*(V/(3*iUp))＝2pF*(2.5V/3*5uA)＝333ns。
Follow the tracks of sum counter circuit 214 and be coupled to synchronous generator circuit 210, oscillator core circuit 202, compensator circuit 218, divider circuit 204 and sample circuit 206.Phase clock 212 and synchronizing signal 226 are to follow the tracks of the input of sum counter circuit 214, increase and reduce in order to determine the frequency of internal oscillator clock 222.
According to an execution mode, when detecting the trailing edge of RXD 124, then restart internal oscillator clock 222.If the falling edge phase clock 212 at RXD 124 is in high state, then the frequency of internal oscillator clock 222 was confirmed as low.If the falling edge phase clock 212 at RXD124 is in low state, then the frequency of internal oscillator clock 222 is confirmed as too fast.
Follow the tracks of sum counter circuit adjustment counter, thereby the charging and discharging electric current that increases oscillator core circuit 202 reduces the charging and discharging electric current of oscillator core circuit 202 with reducing work frequency to increase frequency thereby perhaps reduce counter.In this way, the frequency of internal clocking 222 can become the frequency that equals RXD 124.
Because oscillator core circuit 202 is reset during time td 316, based on the trailing edge of RXD124, time remaining period td 316 is considered to the oscillator synchronization phase place.The sustained periods of time of time tc 318 after the td 316 is considered to compensation of phase.According to an execution mode, charging current increases in tc 318 sustained periods of time, in order to eliminate the frequency error of being introduced by locking phase.According to an execution mode, the locking phase of oscillator core circuit 202 (td 316) but do not affect operation cycle of oscillator core circuit 202, as shown in Figure 3 (td316)+(tc 318)=t1.
Follow the tracks of sum counter circuit 214 and can provide adjusting 220 to trimming circuit 200, wherein should regulate the frequency of determining internal oscillator clock 222 increases or reduction.Level phase clock 212 when following the tracks of sum counter circuit 214 and can state-based conversion 302 occuring is determined to regulate 220.According to an execution mode, can regulate by the counter that increases or reduce the charging and discharging of control generator core circuit 202.Fig. 5 shows the compensation control 504 according to an execution mode.By regulating the frequency of oscillator core circuit 202, the frequency of CAN CLK 126 and RXD 124 can become equal.
Described some illustrated embodiment of the present utility model, it will be apparent to those skilled in the art that foregoing only is illustrative and nonrestrictive, it only provides with the form of example.Can use a lot of modifications or other execution modes that fall into the utility model scope.
The order terms itself such as " first ", " second ", " the 3rd " that uses in order to modify the project in claim element or the specification in the claim does not represent that an element has any priority, existence or order than another element.And the use of order term itself does not represent the maximum number of the element with specific names that can exist in claimed equipment or the method.Unless claim is requirement separately, otherwise can use the additional elements of any proper number.Use order term only is as indicating in order to distinguish an element with specific names and another element with same names in the claims.Any other claim element that itself does not represent to lack similar qualifier such as " at least one " or " at least the first " that uses in order to modify the claim element in the claim is limited to the existence of individual element.Unless claim is requirement separately, otherwise can use the additional elements of any proper number.Use to " comprising ", " comprising ", " having ", " relating to " and distortion thereof is intended to contain after this listed project and equivalence item and sundry item.
Claims (8)
1. an oscillator tracking circuit disposes the clock frequency that is used for recovering bus, it is characterized in that described oscillator tracking circuit comprises:
Along detector circuit, for detection of the state conversion of the data-signal that receives; And
The oscillator core circuit, configuration is used for generating the internal oscillator of first frequency, and the second frequency of the data-signal of wherein said first frequency and described reception is synchronous.
2. oscillator tracking circuit according to claim 1, it is characterized in that described oscillator core circuit comprises first group of switch by the first state control of synchronizing signal, and by second group of switch of the second state of described synchronizing signal control, wherein said oscillator is reset during described the first state, and the free-running operation during described the second state of described oscillator.
3. oscillator tracking circuit according to claim 2 is characterized in that further comprising: synchronous generator circuit, it is coupled to and describedly is used for generating described synchronizing signal along detector circuit and configuration.
4. oscillator tracking circuit according to claim 1 is characterized in that further comprising: follow the tracks of the sum counter circuit, be used for the described frequency of regulating described internal oscillator.
5. oscillator tracking circuit according to claim 1 is characterized in that further comprising: sample circuit, configuration are used in programmable sample point the data-signal of described reception being sampled.
6. controller area network bus system is characterized in that comprising:
The CAN bus, it is coupled at least one from equipment with main equipment;
Described main equipment comprises:
Clock generator is suitable for being provided for the clock frequency of described CAN bus; And
Transmitting apparatus is suitable for sending the data with described clock frequency via described CAN bus;
Described at least one comprise from equipment:
Receiver is used for receiving the described data on the described bus; And
The oscillator tracking circuit, configuration is used for recovering the clock frequency of described bus, and described oscillator tracking circuit comprises:
Along detector circuit, for detection of the state conversion of the data-signal that receives;
And
The oscillator core circuit, configuration is used for generating the internal oscillator of first frequency, and the second frequency of the data-signal of wherein said first frequency and described reception is synchronous.
7. CAN bus system according to claim 6 is characterized in that described oscillator tracking circuit comprises compensating circuit, is used for the capacity cell charging and discharging to described oscillator core circuit.
8. CAN bus system according to claim 7 is characterized in that described capacity cell is the capacity cell with value of 2pF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120578226 CN202798579U (en) | 2011-12-31 | 2011-12-31 | Tracking oscillator circuit and controller local area network bus system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120578226 CN202798579U (en) | 2011-12-31 | 2011-12-31 | Tracking oscillator circuit and controller local area network bus system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202798579U true CN202798579U (en) | 2013-03-13 |
Family
ID=47825748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120578226 Expired - Lifetime CN202798579U (en) | 2011-12-31 | 2011-12-31 | Tracking oscillator circuit and controller local area network bus system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202798579U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104168524A (en) * | 2013-05-17 | 2014-11-26 | 无锡华润矽科微电子有限公司 | Control circuit and control method of digital power amplifier device |
| CN106598018A (en) * | 2015-10-20 | 2017-04-26 | 恩智浦有限公司 | Controller area network (CAN) device and method for operating a CAN device |
| CN111713076A (en) * | 2018-02-21 | 2020-09-25 | 罗伯特·博世有限公司 | Apparatus and method for transmitting/receiving device of bus system |
-
2011
- 2011-12-31 CN CN 201120578226 patent/CN202798579U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104168524A (en) * | 2013-05-17 | 2014-11-26 | 无锡华润矽科微电子有限公司 | Control circuit and control method of digital power amplifier device |
| CN106598018A (en) * | 2015-10-20 | 2017-04-26 | 恩智浦有限公司 | Controller area network (CAN) device and method for operating a CAN device |
| CN111713076A (en) * | 2018-02-21 | 2020-09-25 | 罗伯特·博世有限公司 | Apparatus and method for transmitting/receiving device of bus system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103187925B (en) | The HS-CAN bus clock using oscillator tracking circuit recovers | |
| CN101501995B (en) | Phase comparator, phase comparison device, and clock data recovery system | |
| US8689035B2 (en) | Communication system, communication interface, and synchronization method | |
| WO2012075881A1 (en) | Ieee1588-based sampled value multi-interface synchronization system for multiple slave clocks | |
| TWI424731B (en) | Master device for an ethernet system and related clock synchronization method | |
| WO2012062207A9 (en) | Standard frequency and time adjusting method based on rubidium oscillator | |
| CN101183927B (en) | Clock synchronization device and synchronization method thereof | |
| CN102412957B (en) | High-precision synchronous clock adjusting method | |
| CN202798579U (en) | Tracking oscillator circuit and controller local area network bus system | |
| US10027468B1 (en) | Ethernet physical layer circuit and clock recovery method thereof | |
| CN103957003A (en) | Time to digital converter and frequency tracking device and method | |
| US10965442B2 (en) | Low-power, low-latency time-to-digital-converter-based serial link | |
| CN1842070B (en) | Timing recovery circuit with multiple stages | |
| CN112072706A (en) | Inverter parallel operation synchronous phase locking method | |
| CN109490714A (en) | Wireless synchronization method for distribution fault recording system | |
| CN103399808B (en) | A kind of method that realizes the two redundancies of crystal oscillator in flight control computer | |
| CN103092256A (en) | Clock frequency adjusting circuit and clock frequency adjusting method thereof | |
| CN104506270B (en) | A kind of temporal frequency synchronous integrated realizes system and implementation method | |
| CN101621346B (en) | Source synchronous receiving device with adaptive feedback and source synchronizing method | |
| US8705596B2 (en) | System and method for physical layer device enabled clock diagnostics | |
| CN104333431B (en) | FM (Frequency Modulation) broadcast based low power consumption high accuracy network time synchronous circuit | |
| CN105337591B (en) | The circuit structure and method of clock recovery are realized based on USB device | |
| CN115102657B (en) | Clock frequency synchronization method and device of metering device and storage medium | |
| CN102857222A (en) | Method and circuit for dynamic regulation of system clock | |
| CN102868517A (en) | Clock recovery device and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130313 |