CN204206159U - The phase-locked loop circuit of a kind of wide lock-in range voltage controlled oscillator gain - Google Patents
The phase-locked loop circuit of a kind of wide lock-in range voltage controlled oscillator gain Download PDFInfo
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- CN204206159U CN204206159U CN201420678829.2U CN201420678829U CN204206159U CN 204206159 U CN204206159 U CN 204206159U CN 201420678829 U CN201420678829 U CN 201420678829U CN 204206159 U CN204206159 U CN 204206159U
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Abstract
The utility model discloses the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range, it comprises two voltage controlled oscillator gain different phase-locked loops of height and a logic judgment module, phase-locked loop is made up of phase frequency detector, charge pump, low pass filter, voltage controlled oscillator and frequency divider respectively, and two phase-locked loops have shared voltage controlled oscillator and the frequency divider of dual input; Input reference clock signal is connected with the phase frequency detector in logic judgment module, two phase-locked loops respectively, the output of low pass filter is connected with two inputs of voltage controlled oscillator respectively, the output of frequency divider respectively with logic judgment module and phase frequency detector be connected, the output of logic judgment module is connected with phase frequency detector and charge pump respectively.The utility model realizes the function of wide lock-in range low jitter by two different phase-locked loops of voltage controlled oscillator gain height.
Description
Technical field
The utility model relates to phase-locked loop circuit, the phase-locked loop circuit of the particularly low voltage controlled oscillator gain of a kind of wide lock-in range.
Background technology
Conventional phase locked loops road only has a loop, comprises five modules, respectively: phase frequency detector, charge pump, low pass filter, voltage controlled oscillator and frequency divider, mainly realizes the frequency multiplication to input reference frequency signal.
Traditional phase-locked loop signal processing as shown in Figure 1, phase frequency detector produces the pulse-modulated signal of different in width according to the difference of two input square-wave signals, charge pump is according to the pulse-modulated signal output current pulse of input, low pass filter carries out anomalous integral filtering to current impulse, complete the transformation of electric current to voltage, voltage controlled oscillator exports corresponding frequency signal according to above-mentioned voltage, and frequency divider carries out frequency division to this frequency signal.Frequency-the voltage transfer curve of voltage controlled oscillator as shown in Figure 2, because the gain of voltage controlled oscillator is the slope of curve shown in Fig. 2 at certain frequency of locking, so within the scope of effective input control voltage Δ V during corresponding necessary covering frequence range delta f, f is larger for this Δ, then this slope of a curve is also larger.Considering technique, supply voltage, the deviation of temperature, in order to effectively cover Δ f, must strengthen frequency coverage, the slope of curve is at this moment just very large, usually reaches the order of magnitude of GHZ/V.Above way ensure that the covering to wide frequency ranges, but the gain of high voltage controlled oscillator, and the obvious drawback brought is exactly the sensitivity of voltage controlled oscillator to noise on input control voltage, is degrading jitter performance.From improving the angle of jitter performance, be the gain wishing a low voltage controlled oscillator in fact.From the above, can find out that traditional phase-locked loop structures exists the contradiction between wide lock-in range and low voltage controlled oscillator gain.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range is provided, this circuit can realize wide-range operation and low voltage controlled oscillator gain simultaneously, also achieves and utilize low voltage controlled oscillator gain to reach the object of low jitter while realizing wideband lock function.
The purpose of this utility model is achieved through the following technical solutions: the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range, it comprises two voltage controlled oscillator gain height different phase-locked loop A and phase-locked loop B, and a logic judgment module, phase-locked loop A is by phase frequency detector A, charge pump A, low pass filter A, voltage controlled oscillator and frequency divider composition, phase-locked loop B is by phase frequency detector B, charge pump B, low pass filter B, voltage controlled oscillator and frequency divider composition, phase-locked loop A and phase-locked loop B has shared voltage controlled oscillator and frequency divider, input reference clock signal respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, phase frequency detector A is connected with charge pump A and charge pump B respectively with the output of phase frequency detector B, charge pump A is connected with low pass filter A and low pass filter B respectively with the output of charge pump B, low pass filter A is connected with two inputs of voltage controlled oscillator respectively with the output of low pass filter B, the output of voltage controlled oscillator is connected with the input of frequency divider, the output of frequency divider respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of logic judgment module respectively with phase frequency detector A, phase frequency detector B, charge pump A is connected with charge pump B.
Described voltage controlled oscillator is dual input structure, the corresponding loop of a kind of input, and the Voltage-current conversion rate of one of them input correspondence is large, so the gain of the voltage controlled oscillator of correspondence is large; The Voltage-current conversion rate of outer input correspondence is little, so the gain of the voltage controlled oscillator of correspondence is little.
Described logic judgment module, for judging whether high-gain phase-locked loop locks or approach locking, in this way, then turns off this high-gain loop and exports as high resistant by charge pump, to preserve the electric charge on low pass filter, be switched to the phase-locked loop of low gain simultaneously.The beneficial effects of the utility model are:
The utility model comprises two voltage controlled oscillator gain height different phase-locked loop A and phase-locked loop B, the high phase-locked loop of voltage controlled oscillator gain is utilized to carry out locked frequency point, then be switched to the low phase-locked loop of voltage controlled oscillator gain to ensure low jitter, make phase-locked loop realize the function of wide lock-in range low jitter.
Accompanying drawing explanation
Fig. 1 is traditional phase-locked loop structures figure;
Fig. 2 is the frequency-voltage transfer curve synoptic diagram of voltage controlled oscillator;
Fig. 3 is the structural representation of the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range of the utility model;
Fig. 4 is the structural representation of dual input voltage controlled oscillator in the utility model;
Fig. 5 is to demonstrate the frequency-voltage transfer curve synoptic diagram of the dual input voltage controlled oscillator that wide lock-in range and low voltage controlled oscillator gain effect provide in the utility model;
Fig. 6 is the structure chart of the low pass filter recommended in the utility model;
Fig. 7 is the structural representation of logic judgment module in the utility model.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection range of the present utility model is not limited to the following stated.
As shown in Figure 3, the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range, it comprises two voltage controlled oscillator gain height different phase-locked loop A and phase-locked loop B, and a logic judgment module, phase-locked loop A is made up of phase frequency detector A, charge pump A, low pass filter A, voltage controlled oscillator and frequency divider, phase-locked loop B is made up of phase frequency detector B, charge pump B, low pass filter B, voltage controlled oscillator and frequency divider, and phase-locked loop A and phase-locked loop B has shared voltage controlled oscillator and frequency divider, input reference clock signal respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, phase frequency detector A is connected with charge pump A and charge pump B respectively with the output of phase frequency detector B, charge pump A is connected with low pass filter A and low pass filter B respectively with the output of charge pump B, low pass filter A is connected with two inputs of voltage controlled oscillator respectively with the output of low pass filter B, the output of voltage controlled oscillator is connected with the input of frequency divider, the output of frequency divider respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of logic judgment module respectively with phase frequency detector A, phase frequency detector B, charge pump A is connected with charge pump B.
Described phase frequency detector A and phase frequency detector B, produces the pulse-modulated signal of different in width respectively according to the difference of two input square-wave signals.
Described charge pump A and charge pump B, respectively according to the pulse-modulated signal output current pulse of input.
Described low pass filter A and low pass filter B, carries out anomalous integral filtering to current impulse respectively, completes the transformation of electric current to voltage, output voltage signal.
Described voltage controlled oscillator, exports the signal of different frequency according to different input voltages.
Described frequency divider, carries out frequency division to the frequency of input signal.
Described logic judgment module, for judging whether high-gain phase-locked loop locks or approach locking, in this way, then turns off this high-gain loop and exports as high resistant by charge pump, to preserve the electric charge on low pass filter, be switched to the phase-locked loop of low gain simultaneously.
The gain of voltage controlled oscillator corresponding in described phase-locked loop A is high-gain, and the gain of voltage controlled oscillator corresponding in phase-locked loop B is low gain; That phase-locked loop A works when just starting, when logic judgment module judges loop-locking or approach locking according to the two paths of signals of input, be switched to phase-locked loop B to work, charge pump A is exported simultaneously and be arranged to high-impedance state, to preserve the electric charge on low pass filter A, phase-locked loop B is assisted to complete last locking.
As shown in Figure 4, described voltage controlled oscillator is dual input structure, it comprises NMOS tube N1, N2, PMOS P1, P2, P3, P4 and current control oscillator, NMOS tube N1, PMOS P1 and P2 completes the Voltage-current conversion to input voltage signal, their correspondences be the voltage controlled oscillator gain of phase-locked loop A, because this Voltage-current conversion rate of design is high, so the gain of the voltage controlled oscillator of correspondence is high, concrete methods of realizing is that the breadth length ratio of NMOS tube N1 is strengthened, its mutual conductance will become large like this, so just achieve Voltage-current conversion rate high, large electric current can cause current control oscillator output frequency to become large, so just achieve the object that the gain of voltage controlled oscillator is high, NMOS tube N2, PMOS P3 and P4 complete the Voltage-current conversion to input voltage signal, their correspondences be the voltage controlled oscillator gain of loop B, because this Voltage-current conversion rate of design is low, so the gain of the voltage controlled oscillator of correspondence is low, concrete methods of realizing is that the breadth length ratio of NMOS tube N2 is reduced, its mutual conductance will diminish like this, so just achieve Voltage-current conversion rate low, little electric current can cause current control oscillator output frequency to diminish, so the object that the gain just achieving voltage controlled oscillator is low, described two current/charge-voltage convertors electric current out flows to current control oscillator respectively, and the frequency that current control oscillator exports is with electric current monotone variation, and electric current is larger, and output frequency is larger, current control oscillator can be the loop of phase inverter form, also can be the loop of pseudo-differential form, or other structures.
Fig. 5 is to demonstrate the frequency-voltage transfer curve synoptic diagram of the dual input voltage controlled oscillator that wide lock-in range and low voltage controlled oscillator gain effect provide in the utility model, as shown in Figure 5, this is demonstrated in conjunction with whole dual loop phase-locked loop circuit, such as object is exactly locking this frequency of f1 and has the performance of low jitter, just start phase-locked loop A to work, frequency-voltage transfer the curve of corresponding voltage controlled oscillator is this curve shown in A, can see that this slope of a curve is large, locking can be completed in very wide frequency range.When phase-locked loop A locking or approach locking f1 frequency, logic judgment module can be switched to phase-locked loop B loop, frequency-voltage transfer the curve of corresponding voltage controlled oscillator is this curve shown in B, can see that this slope of a curve is little, the locking of very wide frequency range can not be completed, but phase-locked loop A has completed this task of locking of very wide frequency range, phase-locked loop B is not needed to have this function yet, the function of phase-locked loop B is on the basis of phase-locked loop A, after phase-locked loop A catches frequency, be switched to phase-locked loop B, the voltage temperature fluctuation that the frequency-voltage transfer curve of the voltage controlled oscillator that phase-locked loop B is corresponding only need deal with this frequency corresponding is just passable, so the frequency range needed is not wide, so now the gain of voltage controlled oscillator is low, just in time be beneficial to guarantee low jitter, because the low gain of voltage controlled oscillator is the key point ensureing low jitter.
As shown in Figure 6, described low pass filter, because after phase-locked loop A loop is switched to phase-locked loop B, it is high-impedance state that charge pump A exports, and the electric capacity in low pass filter A can preserve former electric charge, assists phase-locked loop B to carry out the locking of frequency.
As shown in Figure 7, described logic judgment module comprises counter A, counter B and multilevel iudge module, input A connects input reference clock signal, input B is the feedback signal connecting frequency divider output, counter A sum counter B calculates the square wave number of input separately in same time section, count results is exported to multilevel iudge module, multilevel iudge module decides to export PFD_A according to this count results, export PFD_B, export the signal of CP_A and output CP_B, concrete operations are: if the square wave number that calculates of counter A much larger than or the square wave number that calculates much smaller than counter B, so illustrate that phase-locked loop A does not also lock, the signal exporting PFD_B and output CP_B allows PFD and CP of phase-locked loop B not work, the signal exporting PFD_A and output CP_A allows PFD and CP of phase-locked loop A work, if the square wave number that counter A calculates is very close or equal the square wave number that counter B calculates, so illustrate that phase-locked loop A locks, the signal of output PFD_B and output CP_B allows PFD and CP of phase-locked loop B work, and the signal exporting PFD_A and output CP_A allows PFD and CP of phase-locked loop A not work.
Claims (3)
1. the phase-locked loop circuit of the low voltage controlled oscillator gain of wide lock-in range, it is characterized in that: it comprises two voltage controlled oscillator gain height different phase-locked loop A and phase-locked loop B, and a logic judgment module, phase-locked loop A is made up of phase frequency detector A, charge pump A, low pass filter A, voltage controlled oscillator and frequency divider, phase-locked loop B is made up of phase frequency detector B, charge pump B, low pass filter B, voltage controlled oscillator and frequency divider, and phase-locked loop A and phase-locked loop B has shared voltage controlled oscillator and the frequency divider of dual input, input reference clock signal respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, phase frequency detector A is connected with charge pump A and charge pump B respectively with the output of phase frequency detector B, charge pump A is connected with low pass filter A and low pass filter B respectively with the output of charge pump B, low pass filter A is connected with two inputs of voltage controlled oscillator respectively with the output of low pass filter B, the output of voltage controlled oscillator is connected with the input of frequency divider, the output of frequency divider respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of logic judgment module respectively with phase frequency detector A, phase frequency detector B, charge pump A is connected with charge pump B.
2. the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range according to claim 1, it is characterized in that: described voltage controlled oscillator is dual input structure, the corresponding loop of a kind of input, the Voltage-current conversion rate of one of them input correspondence is large, so the gain of the voltage controlled oscillator of correspondence is large; The Voltage-current conversion rate of outer input correspondence is little, so the gain of the voltage controlled oscillator of correspondence is little.
3. the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range according to claim 1, it is characterized in that: described logic judgment module is for judging whether the phase-locked loop of high-gain voltage controlled oscillator locks or approach locking, in this way, the loop then turning off the voltage controlled oscillator of this high-gain exports as high resistant by charge pump, to preserve the electric charge on low pass filter, be switched to the phase-locked loop of the voltage controlled oscillator of low gain simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420678829.2U CN204206159U9 (en) | 2014-11-14 | 2014-11-14 | A kind of phase-locked loop circuit of wide lock-in range low pressure controlled oscillator gain |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420678829.2U CN204206159U9 (en) | 2014-11-14 | 2014-11-14 | A kind of phase-locked loop circuit of wide lock-in range low pressure controlled oscillator gain |
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| CN204206159U true CN204206159U (en) | 2015-03-11 |
| CN204206159U9 CN204206159U9 (en) | 2017-12-19 |
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| CN201420678829.2U Expired - Fee Related CN204206159U9 (en) | 2014-11-14 | 2014-11-14 | A kind of phase-locked loop circuit of wide lock-in range low pressure controlled oscillator gain |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109756191A (en) * | 2018-11-22 | 2019-05-14 | 合肥市芯海电子科技有限公司 | A kind of low-power consumption crystal-oscillator circuit with pseudo differential architectures |
| CN112202424A (en) * | 2020-11-06 | 2021-01-08 | 珠海市一微半导体有限公司 | N-time pulse width expansion circuit and pulse width expanded phase-locked loop system |
-
2014
- 2014-11-14 CN CN201420678829.2U patent/CN204206159U9/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109756191A (en) * | 2018-11-22 | 2019-05-14 | 合肥市芯海电子科技有限公司 | A kind of low-power consumption crystal-oscillator circuit with pseudo differential architectures |
| CN109756191B (en) * | 2018-11-22 | 2023-04-28 | 合肥市芯海电子科技有限公司 | Low-power-consumption crystal oscillator circuit with pseudo-differential structure |
| CN112202424A (en) * | 2020-11-06 | 2021-01-08 | 珠海市一微半导体有限公司 | N-time pulse width expansion circuit and pulse width expanded phase-locked loop system |
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| Publication number | Publication date |
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| CN204206159U9 (en) | 2017-12-19 |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CU01 | Correction of utility model patent |
Correction item: Denomination of Utility Model Correct: A PLL circuit with wide lock range low voltage controlled oscillator gain False: A PLL circuit with wide lock range voltage controlled oscillator gain Number: 10 Volume: 31 Correction item: Denomination of Utility Model|Description Correct: A PLL circuit with wide lock range low voltage controlled oscillator gain|Zheng Que False: A PLL circuit with wide lock range voltage controlled oscillator gain|Cuo Wu Number: 10 Page: full text Volume: 31 |
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| CU01 | Correction of utility model patent | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150311 Termination date: 20191114 |
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| CF01 | Termination of patent right due to non-payment of annual fee |