CN105656479A - Wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit - Google Patents
Wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit Download PDFInfo
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- CN105656479A CN105656479A CN201410644714.6A CN201410644714A CN105656479A CN 105656479 A CN105656479 A CN 105656479A CN 201410644714 A CN201410644714 A CN 201410644714A CN 105656479 A CN105656479 A CN 105656479A
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Abstract
The invention discloses a wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit. The wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit comprises two phase-locked loops with different voltage controlled oscillator gains and a logical judgment module, wherein each phase-locked loop is composed of a phase frequency detector, a charge pump, a low-pass filter, a voltage controlled oscillator and a frequency divider, and the two phase-locked loops share the double-input voltage controlled oscillator and the frequency divider; input reference clock signals are connected with the logic judgment module and the phase frequency detectors in the two phase-locked loops respectively; the output of the low-pass filter is connected with two input ends of the voltage controlled oscillator respectively; the output of the frequency divider is connected with the logic judgment module and the phase frequency detectors respectively; and the output of the logic judgment module is connected with the phase frequency detectors and the charge pumps respectively. According to the wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit of the invention, the two phase-locked loops with different voltage controlled oscillator gains are adopted, and thus, the wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit has the advantages of wide locking range and low jitter function.
Description
Technical field
The present invention relates to phase-locked loop circuit, particularly the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range.
Background technology
Conventional phase locked loops road only has a loop, comprises five modules, respectively: phase frequency detector, charge pump, low pass filter, voltage controlled oscillator and frequency divider, mainly realize the frequency multiplication to input reference frequency signal.
Traditional phaselocked loop signal processing as shown in Figure 1, phase frequency detector is according to the pulse-modulated signal that produces different in width that differs of two input square-wave signals, charge pump is according to the pulse-modulated signal output current pulse of input, low pass filter carries out integration and filtering to current impulse, complete the transformation of electric current to voltage, the frequency signal that voltage controlled oscillator is corresponding according to above-mentioned Voltage-output, frequency divider carries out frequency division to this frequency signal. Frequency-voltage transfer curve of voltage controlled oscillator as shown in Figure 2, because the gain of voltage controlled oscillator is the slope of curve shown in Fig. 2 at certain frequency of locking, so corresponding must covering frequence range delta f time within the scope of effective input control voltage Δ V, f is larger for this Δ, and this slope of a curve is also just larger. Consider technique, supply voltage, the deviation of temperature, in order effectively to cover Δ f, must strengthen frequency coverage, and the slope of curve is at this moment just very large, usually reaches the order of magnitude of GHZ/V. Above way is the covering having ensured wide frequency ranges, but the gain of high voltage controlled oscillator, and the obvious drawback of bringing is exactly the sensitivity of voltage controlled oscillator to noise on input control voltage, has worsened jitter performance. From improving the angle of jitter performance, be the gain that wishes a low voltage controlled oscillator in fact. From the above, can find out that traditional phase-locked loop structures exists the contradiction between wide lock-in range and the gain of low voltage controlled oscillator.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range is provided, this circuit can be realized wide-range operation and low voltage controlled oscillator gain simultaneously, has also realized the object of utilizing low voltage controlled oscillator to gain to reach low jitter in realizing wideband lock function.
The object of the invention is to be achieved through the following technical solutions: the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range, it comprises two different phase-locked loop A and phase-locked loop B of voltage controlled oscillator gain height, an and logic judgment module, phase-locked loop A is made up of phase frequency detector A, charge pump A, low pass filter A, voltage controlled oscillator and frequency divider, phase-locked loop B is made up of phase frequency detector B, charge pump B, low pass filter B, voltage controlled oscillator and frequency divider, and phase-locked loop A and phase-locked loop B have shared voltage controlled oscillator and frequency divider, input reference clock signal respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of phase frequency detector A and phase frequency detector B is connected with charge pump A and charge pump B respectively, the output of charge pump A and charge pump B is connected with low pass filter A and low pass filter B respectively, the output of low pass filter A and low pass filter B is connected with two inputs of voltage controlled oscillator respectively, the output of voltage controlled oscillator is connected with the input of frequency divider, the output of frequency divider respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of logic judgment module respectively with phase frequency detector A, phase frequency detector B, charge pump A is connected with charge pump B.
Described voltage controlled oscillator is dual input structure, the corresponding loop of a kind of input, and it is large that one of them inputs corresponding Voltage-current conversion rate, so the gain of corresponding voltage controlled oscillator is large; Voltage-current conversion rate corresponding to outer input is little, so the gain of corresponding voltage controlled oscillator is little.
Described logic judgment module is used for judging whether high-gain phase-locked loop locks or approach locking, in this way, turn-offs this high-gain loop and is output as high resistant by charge pump, to preserve the electric charge on low pass filter, is switched to the phase-locked loop of low gain simultaneously. The invention has the beneficial effects as follows:
The present invention includes two different phase-locked loop A and phase-locked loop B of voltage controlled oscillator gain height, utilize the voltage controlled oscillator high phase-locked loop that gains to carry out locked frequency point, then be switched to the voltage controlled oscillator low phase-locked loop that gains and ensure low jitter, make phaselocked loop realize the function of wide lock-in range low jitter.
Brief description of the drawings
Fig. 1 is traditional phase-locked loop structures figure;
Fig. 2 is frequency-voltage transfer curve synoptic diagram of voltage controlled oscillator;
Fig. 3 is the structural representation of the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range of the present invention;
Fig. 4 is the structural representation of dual input voltage controlled oscillator in the present invention;
Fig. 5 is in order to demonstrate frequency-voltage transfer curve synoptic diagram of the dual input voltage controlled oscillator that wide lock-in range and low voltage controlled oscillator gain effect provide in the present invention;
Fig. 6 is the structure chart of the low pass filter recommended in the present invention;
Fig. 7 is the structural representation of logic judgment module in the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
As shown in Figure 3, the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range, it comprises two different phase-locked loop A and phase-locked loop B of voltage controlled oscillator gain height, an and logic judgment module, phase-locked loop A is made up of phase frequency detector A, charge pump A, low pass filter A, voltage controlled oscillator and frequency divider, phase-locked loop B is made up of phase frequency detector B, charge pump B, low pass filter B, voltage controlled oscillator and frequency divider, and phase-locked loop A and phase-locked loop B have shared voltage controlled oscillator and frequency divider, input reference clock signal respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of phase frequency detector A and phase frequency detector B is connected with charge pump A and charge pump B respectively, the output of charge pump A and charge pump B is connected with low pass filter A and low pass filter B respectively, the output of low pass filter A and low pass filter B is connected with two inputs of voltage controlled oscillator respectively, the output of voltage controlled oscillator is connected with the input of frequency divider, the output of frequency divider respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of logic judgment module respectively with phase frequency detector A, phase frequency detector B, charge pump A is connected with charge pump B.
Described phase frequency detector A and phase frequency detector B, respectively according to the pulse-modulated signal that produces different in width that differs of two input square-wave signals.
Described charge pump A and charge pump B, respectively according to the pulse-modulated signal output current pulse of input.
Described low pass filter A and low pass filter B, carry out integration and filtering to current impulse respectively, completes the transformation of electric current to voltage, output voltage signal.
Described voltage controlled oscillator, according to the signal of different input voltage output different frequencies.
Described frequency divider, carries out frequency division to the frequency of input signal.
Described logic judgment module is used for judging whether high-gain phase-locked loop locks or approach locking, in this way, turn-offs this high-gain loop and is output as high resistant by charge pump, to preserve the electric charge on low pass filter, is switched to the phase-locked loop of low gain simultaneously.
In described phase-locked loop A, the gain of corresponding voltage controlled oscillator is high-gain, and in phase-locked loop B, the gain of corresponding voltage controlled oscillator is low gain; While just beginning, be phase-locked loop A work, in the time that logic judgment module is judged loop-locking or approach locking according to the two paths of signals of input, be switched to phase-locked loop B work, charge pump A output is arranged to high-impedance state simultaneously, to preserve the electric charge on low pass filter A, assist phase-locked loop B to complete last locking.
As shown in Figure 4, described voltage controlled oscillator is dual input structure, it comprises NMOS pipe N1, N2, PMOS manages P1, P2, P3, P4 and current control oscillator, NMOS manages N1, PMOS pipe P1 and P2 have completed the Voltage-current conversion to input voltage signal, their correspondences be the voltage controlled oscillator gain of phase-locked loop A, because it is high to have a mind to design this Voltage-current conversion rate, so the gain of corresponding voltage controlled oscillator is high, concrete methods of realizing is that the breadth length ratio of NMOS pipe N1 is strengthened, its mutual conductance will become large like this, so just realize Voltage-current conversion rate high, large electric current can cause current control oscillator output frequency to become large, so just realized the high object of the gain of voltage controlled oscillator, NMOS pipe N2, PMOS pipe P3 and P4 have completed the Voltage-current conversion to input voltage signal, their correspondences be the voltage controlled oscillator gain of loop B, because it is low to have a mind to design this Voltage-current conversion rate, so the gain of corresponding voltage controlled oscillator is low, concrete methods of realizing is that the breadth length ratio of NMOS pipe N2 is reduced, its mutual conductance will diminish like this, so just realize Voltage-current conversion rate low, little electric current can cause current control oscillator output frequency to diminish, so just realized the low object of the gain of voltage controlled oscillator, two described current/charge-voltage convertors electric current out flows to respectively current control oscillator, and the frequency of current control oscillator output is with electric current monotone variation, and electric current is larger, and output frequency is larger, current control oscillator can be the loop of phase inverter form, can be also the loop of pseudo-differential form, or other structures.
Fig. 5 is in order to demonstrate frequency-voltage transfer curve synoptic diagram of the dual input voltage controlled oscillator that wide lock-in range and low voltage controlled oscillator gain effect provide in the present invention, as shown in Figure 5, this is demonstrated in conjunction with whole dual loop phase-locked loop circuit, such as object is exactly locking this frequency of f1 and the performance that has low jitter, just start phase-locked loop A work, frequency-voltage transfer curve of corresponding voltage controlled oscillator is this curve shown in A, can see that this slope of a curve is large, can in very wide frequency range, complete locking. in the time of phase-locked loop A locking or approach locking f1 frequency, logic judgment module can be switched to phase-locked loop B loop, frequency-voltage transfer curve of corresponding voltage controlled oscillator is this curve shown in B, can see that this slope of a curve is little, can not complete the locking of very wide frequency range, but phase-locked loop A has completed this task of locking of very wide frequency range, do not need phase-locked loop B to there is this function yet, the function of phase-locked loop B is on the basis of phase-locked loop A, after phase-locked loop A catches frequency, be switched to phase-locked loop B, it is just passable that frequency-voltage transfer curve of the voltage controlled oscillator that phase-locked loop B is corresponding only need be dealt with the voltage temperature fluctuation that this frequency is corresponding, so the frequency range needing is not wide, so now the gain of voltage controlled oscillator is low, just in time be beneficial to guarantee low jitter, because the low gain of voltage controlled oscillator is the key point that ensures low jitter.
As shown in Figure 6, described low pass filter, because phase-locked loop A loop is switched to after phase-locked loop B, charge pump A output is high-impedance state, the electric capacity in low pass filter A can be preserved former electric charge, assists phase-locked loop B to carry out the locking of frequency.
As shown in Figure 7, described logic judgment module comprises counter A, counter B and relatively judge module, input A connects input reference clock signal, input B is the feedback signal that connects frequency divider output, counter A sum counter B calculates the square wave number of input separately in same time section, count results is exported to comparison judge module, relatively judge module decides output PFD_A according to this count results, output PFD_B, the signal of output CP_A and output CP_B, concrete operations are: if the square wave number that counter A calculates much larger than or the square wave number that calculates much smaller than counter B, illustrate that so phase-locked loop A does not also lock, the signal of output PFD_B and output CP_B is to allow the PFD of phase-locked loop B and CP not work, the signal of output PFD_A and output CP_A is to allow the PFD of phase-locked loop A and CP work, if the square wave number that counter A calculates is very approaching or equal the square wave number that counter B calculates, illustrate that so phase-locked loop A locks, the signal of output PFD_B and output CP_B is to allow the PFD of phase-locked loop B and CP work, and the signal of output PFD_A and output CP_A is to allow the PFD of phase-locked loop A and CP not work.
Claims (3)
1. the phase-locked loop circuit of the low voltage controlled oscillator gain of wide lock-in range, it is characterized in that: it comprises two different phase-locked loop A and phase-locked loop B of voltage controlled oscillator gain height, an and logic judgment module, phase-locked loop A is made up of phase frequency detector A, charge pump A, low pass filter A, voltage controlled oscillator and frequency divider, phase-locked loop B is made up of phase frequency detector B, charge pump B, low pass filter B, voltage controlled oscillator and frequency divider, and phase-locked loop A and phase-locked loop B have shared voltage controlled oscillator and the frequency divider of dual input, input reference clock signal respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of phase frequency detector A and phase frequency detector B is connected with charge pump A and charge pump B respectively, the output of charge pump A and charge pump B is connected with low pass filter A and low pass filter B respectively, the output of low pass filter A and low pass filter B is connected with two inputs of voltage controlled oscillator respectively, the output of voltage controlled oscillator is connected with the input of frequency divider, the output of frequency divider respectively with logic judgment module, phase frequency detector A is connected with phase frequency detector B, the output of logic judgment module respectively with phase frequency detector A, phase frequency detector B, charge pump A is connected with charge pump B.
2. the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range according to claim 1, it is characterized in that: described voltage controlled oscillator is dual input structure, the corresponding loop of a kind of input, it is large that one of them inputs corresponding Voltage-current conversion rate, so the gain of corresponding voltage controlled oscillator is large; Voltage-current conversion rate corresponding to outer input is little, so the gain of corresponding voltage controlled oscillator is little.
3. the phase-locked loop circuit of the low voltage controlled oscillator gain of a kind of wide lock-in range according to claim 1, it is characterized in that: described logic judgment module is for judging whether the phase-locked loop of high-gain voltage controlled oscillator locks or approach locking, in this way, the loop that turn-offs the voltage controlled oscillator of this high-gain is output as high resistant by charge pump, so that the electric charge on preservation low pass filter, be switched to the phase-locked loop of the voltage controlled oscillator of low gain simultaneously.
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| CN201410644714.6A CN105656479B (en) | 2014-11-14 | 2014-11-14 | A kind of phase-locked loop circuit of width lock-in range low pressure control oscillator gain |
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| CN201410644714.6A CN105656479B (en) | 2014-11-14 | 2014-11-14 | A kind of phase-locked loop circuit of width lock-in range low pressure control oscillator gain |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106210442A (en) * | 2016-07-08 | 2016-12-07 | 成都振芯科技股份有限公司 | A kind of pixel clock generating circuit based on leggy phaselocked loop |
| CN108880536A (en) * | 2017-05-11 | 2018-11-23 | 美高森美半导体无限责任公司 | Clock synthesizer with not damaged benchmark switching and frequency stability |
| CN109547017A (en) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | A kind of dual loop phase-locked loop analog core circuit and phaselocked loop applied to FPGA |
| CN110289853A (en) * | 2019-07-19 | 2019-09-27 | 加特兰微电子科技(上海)有限公司 | Oscillator, phaselocked loop and radar system |
| CN114759917A (en) * | 2022-06-16 | 2022-07-15 | 南京观海微电子有限公司 | ISP receiver compatible with PLL and DLL modes |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106210442A (en) * | 2016-07-08 | 2016-12-07 | 成都振芯科技股份有限公司 | A kind of pixel clock generating circuit based on leggy phaselocked loop |
| CN106210442B (en) * | 2016-07-08 | 2019-05-24 | 成都振芯科技股份有限公司 | A kind of pixel clock generating circuit based on leggy phaselocked loop |
| CN108880536A (en) * | 2017-05-11 | 2018-11-23 | 美高森美半导体无限责任公司 | Clock synthesizer with not damaged benchmark switching and frequency stability |
| CN108880536B (en) * | 2017-05-11 | 2020-02-18 | 美高森美半导体无限责任公司 | Clock synthesizer with lossless reference switching and frequency stability |
| CN109547017A (en) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | A kind of dual loop phase-locked loop analog core circuit and phaselocked loop applied to FPGA |
| CN110289853A (en) * | 2019-07-19 | 2019-09-27 | 加特兰微电子科技(上海)有限公司 | Oscillator, phaselocked loop and radar system |
| CN110289853B (en) * | 2019-07-19 | 2024-05-14 | 加特兰微电子科技(上海)有限公司 | Oscillator, phase-locked loop and radar system |
| CN114759917A (en) * | 2022-06-16 | 2022-07-15 | 南京观海微电子有限公司 | ISP receiver compatible with PLL and DLL modes |
| CN114759917B (en) * | 2022-06-16 | 2022-09-02 | 南京观海微电子有限公司 | ISP receiver compatible with PLL and DLL modes |
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