CN112202424A - N-time pulse width expansion circuit and pulse width expanded phase-locked loop system - Google Patents

N-time pulse width expansion circuit and pulse width expanded phase-locked loop system Download PDF

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CN112202424A
CN112202424A CN202011232531.5A CN202011232531A CN112202424A CN 112202424 A CN112202424 A CN 112202424A CN 202011232531 A CN202011232531 A CN 202011232531A CN 112202424 A CN112202424 A CN 112202424A
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pulse width
signal
module
delay
signal input
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韩怀宇
邵要华
赵伟兵
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Zhuhai Amicro Semiconductor Co Ltd
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Zhuhai Amicro Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth

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  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention discloses an n-time pulse width expansion circuit and a pulse width expanded phase-locked loop system, wherein the n-time pulse width expansion circuit comprises: the pulse width transmission sequence module comprises n-1 cascaded D triggers; a delay array module including n groups of delay sub-arrays; an OR logic group module including a preset number of OR logic units; and the output shaping unit module comprises 1D flip-flop. The invention also discloses a phase-locked loop system applying the pulse width expansion circuit. The n-time pulse width expansion circuit disclosed by the invention is simple in structure, can adjust the corresponding pulse width expansion multiple according to the signal pulse width expansion requirement, is high in flexibility and adaptability, and is easy to realize. The phase-locked loop system applying the pulse width expansion circuit guarantees the stability of the phase-locked loop system based on the pulse width expansion circuit.

Description

N-time pulse width expansion circuit and pulse width expanded phase-locked loop system
Technical Field
The invention relates to the technical field of analog circuits, in particular to an n-time pulse width expansion circuit and a pulse width expanded phase-locked loop system.
Background
The phase-locked loop system is mainly composed of a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider, and the phase-locked loop system mainly compares the frequency and phase relationship of an input reference signal and a feedback signal output by the phase-locked loop through the phase frequency detector, outputs a corresponding control signal, controls the charge pump to control the current flowing in and out of the low-pass filter, thereby adjusting the output voltage of the low pass filter, adjusting the voltage-controlled oscillator by the output voltage of the low pass filter, thereby changing the output frequency of the voltage-controlled oscillator, dividing the frequency of the output signal of the voltage-controlled oscillator by the frequency divider and feeding the frequency-divided output signal back to the phase frequency detector, and the output control signal of the phase frequency detector is adjusted, the operation is repeated in a circulating mode until the phase locking is stable, and the frequency of the reference signal is equal to the frequency of the output signal or is in a relation of multiple n when the phase locking is stable. The duty ratio of a feedback signal output by a frequency divider module in a traditional phase-locked loop system is small, so that although the feedback signal is low, the speed of processing signals by a phase frequency detector often cannot meet the requirement, when the frequency of a clock signal FVCO output by a voltage-controlled oscillator is high, the speed requirement on the phase frequency detector is higher, therefore, the stability of the traditional phase-locked loop is poor when the system output frequency is high, once the speed of the phase frequency detector is insufficient, the situation that the circuit works at the highest frequency by error locking is probably caused, the circuit structure of the existing pulse width expansion circuit is complex, the production cost of the pulse width expansion circuit is increased, and the pulse width expansion efficiency is reduced.
Disclosure of Invention
In order to solve the problems, the invention provides an n-time pulse width expansion circuit and a pulse width expanded phase-locked loop system, simplifies the structure of the pulse width expansion circuit, reduces the speed requirement on a phase frequency detector by expanding the high level width of a feedback signal, and greatly improves the adaptability and the stability of the phase-locked loop system. The specific technical scheme of the invention is as follows:
an n-fold pulse width expansion circuit, the n-fold pulse width expansion circuit comprising: the pulse width transmission device comprises a pulse width transmission sequence module, a delay array module, an OR logic group module and an output shaping unit module; the pulse width transmission sequence module comprises n-1 cascaded D triggers; the delay array module comprises a delay unit; the OR logic group module comprises a preset number of OR logic units; the output shaping unit module comprises a D trigger D _ 0; the input reference clock signal Clk is connected with the clock signal input end of an n-1 level D trigger D _ n-1 of a pulse width transmission sequence module, the signal input ends of n-1 cascaded D triggers of the pulse width transmission sequence module are connected with the matched signal input end of a delay array module, the signal output end of a first level D trigger of the pulse width transmission sequence module is connected with the matched signal input end of the delay array module, the signal output end of the delay array module is connected with the signal input end of an OR logic group module, or the signal output end of the logic group module is connected with the signal input end of a D trigger D _0 of an output shaping unit module; n is an integer greater than or equal to 2. The n-time pulse width expansion circuit simplifies the structure of the pulse width expansion circuit, and can allocate pulse signals with different times of pulse widths according to the actual requirements of users, thereby realizing the expected broadening effect.
Further, the pulse width transmission sequence comprises n-1 cascaded D triggers, and the signal output end of the n-1 st stage D trigger D _ n-1 is connected with the signal input end of the n-2 nd stage D trigger D _ n-2; the signal input end of the D flip-flop with the highest series number is used for inputting a signal Fbk _ t to be expanded. The pulse width transmission sequence of the n-time pulse width expansion circuit inputs an input signal to be expanded into the D trigger, the D trigger plays a role of storing the signal to be expanded in the pulse width transmission sequence module to realize shift register, and the D trigger outputs the signal to be expanded after corresponding pulse width transmission.
Furthermore, the delay array module comprises n signal input ends and n signal output ends, the signal output ends of n-1 cascaded D flip-flops of the pulse width transmission sequence module and the signal output end of the first-stage D flip-flop are respectively connected with the signal input ends matched with the delay array module, a group of delay sub-arrays are connected between the n signal input ends and the corresponding n signal output ends thereof to form n groups of delay sub-arrays, the n signal input ends of the delay array module are respectively configured as the signal input ends corresponding to the group of delay sub-arrays, and the n signal output ends of the delay array module are respectively configured as the signal output ends corresponding to the group of delay sub-arrays; the signal output end of the first-stage D trigger D _1 is connected with the signal input ends of the corresponding group of delay sub-arrays, and the group of delay sub-arrays connected with the signal output end of the first-stage D trigger D _1 comprises 0 delay units; the signal input end of the n-1 st D trigger D _ n-1 is connected with the signal input ends of the corresponding group of delay sub-arrays, and the group of delay sub-arrays connected with the signal input end of the n-1 st D trigger D _ n-1 comprises n-1 cascaded delay units; in the group of delay subarrays, the signal output end of the (n-1) th-level delay unit is connected with the signal input end of the (n-2) th-level delay unit, the signal input end of the delay unit with the highest level number is connected with the signal input end of the group of delay subarrays, and the signal output end of the delay unit with the lowest level number is connected with the signal output end of the group of delay subarrays. The delay array module is provided with n groups of delay sub-arrays, each group of delay sub-array is composed of 0 to n-1 delay units, each delay unit delays signals by delta t so as to achieve the purpose that a plurality of signals are partially overlapped, the delay time length can be adjusted according to the requirement of pulse width expansion multiple, so that signals after pulse width expansion are obtained, and the error signals caused by feedback signal jitter and the like due to delay problems are avoided by utilizing the design of overlapping of the delay units.
Further, the or logic group module includes a first preset number of or logic units, and the or logic units include a second preset number of signal input ends; the n signal output ends of the delay array module are respectively and correspondingly connected with the signal input ends of a first preset number of OR logic units matched in the OR logic group module, so that the n signal output ends of the delay array module are respectively and correspondingly connected with the matched signal input ends of the OR logic group module; the first preset number of OR logic units perform OR logic operation on the n signals input by the delay array module and output one signal as an output signal of the OR logic group module. The OR logic group module performs OR logic operation on the input signals, so that the signal overlapping parts of the input signals are eliminated, the signal pulse width expansion is performed, error signals are avoided, and the pulse width expansion requirement when the n value is larger can be met through the common processing of a first preset number of OR logic units.
Further, if the first preset number of the or logic units is equal to 1, the signal output end of the or logic unit is connected with the signal input end of the D flip-flop D _0 of the output shaping unit module; if the first preset number of OR logic units is greater than OR equal to 2, one OR logic unit OR1 in the preset number of OR logic units is used for performing OR logic operation on signals output by the remaining OR logic units and outputting a final signal as an output signal of the OR logic group module, and the signal output end of the OR logic unit OR1 is connected with the signal input end of the D flip-flop D _0 of the output shaping unit module.
Further, the connection between the signal output end of the or logic group module and the signal input end of the D flip-flop D _0 of the output shaping unit module means that the signal output end of the or logic unit that outputs the final signal of the or logic group module is connected to the signal input end of the D flip-flop D _0 of the output shaping unit module.
Further, the output shaping unit comprises a single D flip-flop D _0, and a clock signal input end of the D flip-flop D _0 is connected with clock signal input ends of the n-1D flip-flops of the pulse width transmission sequence. The technical scheme enables the input reference clock signal to be used as the integral clock reference signal of the pulse width expansion circuit.
The invention also discloses a pulse width expansion circuit, which is formed by connecting m n-time pulse width expansion circuits with the same or different values in series according to any one of claims 1 to 7, so that the pulse width expansion multiple of the pulse width expansion circuit is the sum of the m n-time pulse width expansion multiples of the pulse width expansion circuits according to any one of claims 1 to 7, and the sum is reduced by one. The technical scheme can be applied to realizing the requirement of large-multiple pulse width expansion by connecting a plurality of pulse width expansion circuits in series when the pulse width expansion circuit needs the large-multiple pulse width expansion.
The invention also discloses a phase-locked loop system applying the pulse width expansion circuit, which comprises the following components: a phase frequency detector PFD, a charge pump module CP, a low pass filter LPF, a voltage controlled oscillator VCO, a frequency divider N divider and an N-times pulse width extension circuit module fbk _ pwe as claimed in claims 1 to 8; the signal output end of the phase frequency detector PFD is connected with the signal input end of the charge pump module CP, the signal output end of the charge pump module CP is connected with the signal input end of the low pass filter LPF, the signal output end of the low pass filter LPF is connected with the signal input end of the voltage controlled oscillator VCO, the signal output end of the voltage controlled oscillator VCO is connected with the signal input end of the frequency divider N divider, the signal output end of the frequency divider N divider is connected with the signal input end of the pulse width expansion circuit module fbk _ pwe, the signal output end of the pulse width expansion circuit module fbk _ pwe is connected with the feedback signal input end of the phase frequency detector PFD, and a reference signal is input from the signal input end of the phase frequency detector. The phase-locked loop system applying the pulse width expansion circuit can flexibly adjust the pulse width expansion multiple according to the actual pulse width multiple requirement based on the fact that the pulse width of the expanded signal of the pulse width expansion circuit is n times of the original pulse width, the feedback signal level width in the phase-locked loop system is increased, the stability of the phase-locked loop system is ensured, and the working reliability of the phase frequency detector PFD is improved.
Drawings
Fig. 1 is a schematic structural diagram of an n-times pulse width expansion circuit according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a 2-time pulse width expansion circuit according to an embodiment of the present invention.
Fig. 3 is a circuit diagram of a 3-times pulse width expansion circuit according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of a phase-locked loop according to an embodiment of the invention.
Fig. 5 is a waveform diagram of signals at nodes of the 3-times pulse width expansion circuit of the embodiment shown in fig. 3.
Fig. 6 is a schematic structural diagram of a 4-time pulse width expansion circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention.
In an embodiment of the present invention, an n-time pulse width expansion circuit is provided, and as shown in fig. 1, the n-time pulse width expansion circuit is composed of a pulse width transmission sequence module, a delay array module, or a logic group module, and an output shaping unit module. The n-fold pulse width expansion circuit can be applied to, but is not limited to, a phase-locked loop as shown in fig. 4.
Specifically, the pulse width transmission sequence module comprises n-1 cascaded D triggers, and the signal output end of the n-1 st-stage D trigger D _ n-1 is connected with the signal input end of the n-2 nd-stage D trigger D _ n-2; the delay array module comprises n signal input ends and n signal output ends, and the signal input ends of n-1 cascaded D triggers of the pulse width transmission sequence module and the signal output end of the first-stage D trigger D _0 are respectively connected with the signal input ends matched with the delay array module.
Specifically, a group of delay sub-arrays are connected between n signal input ends and n corresponding signal output ends in the delay array module to form n groups of delay sub-arrays, the n signal input ends of the delay array module are respectively configured as the signal input ends of the corresponding group of delay sub-arrays, the n signal output ends of the delay array module are respectively configured as the signal output ends of the corresponding group of delay sub-arrays, the signal input end of the n-1-th-stage D flip-flop D _ n-1 is connected with the signal input end of the corresponding group of delay sub-arrays, a group of delay sub-arrays connected with the signal input end of the n-1-th-stage D flip-flop D _ n-1 comprises n-1 cascaded delay units, in a group of delay sub-arrays, the signal output end of the n-1-stage delay unit is connected with the signal input end of the n-2-stage delay unit, the signal input end of the delay unit with the highest series number is connected with the signal input end of the group of delay sub-arrays, the signal output end of the delay unit with the lowest series number is connected with the signal output end of the group of delay sub-arrays, the signal output end of the delay array module is connected with the signal input end of the OR logic group module, particularly, the signal output end of the first-stage D trigger D _0 is connected with the signal input end of the corresponding group of delay sub-arrays, and the group of delay sub-arrays connected with the absorption output end of the first-stage D trigger D _0 comprises 0 delay units. The delay unit is formed by connecting two stages of inverters in series, the delay unit can carry out corresponding delay adjustment according to specific delay requirements, one delay unit is used for delaying the input signal by delta t, the delay effect of a group of delay sub-arrays on the input signal is determined according to the number of the delay units contained in the delay sub-arrays, and n cascaded delay units are used for delaying the input signal by n x delta t.
Specifically, the or logic group module includes a first preset number of one or more or logic units with three input ends, signal input ends of the or logic units are connected with signal output ends of corresponding delay array modules, so that n signal output ends of the delay array modules are respectively and correspondingly connected with matched signal input ends of the or logic group module, and final signal output ends of the first preset number of or logic units are connected with signal input ends of the output shaping unit module; the first preset number and the number of the input ports of the OR logic unit can be adaptively adjusted according to the pulse width expansion multiple n value of the actual circuit; if the first preset number of the OR logic units is equal to 1, the signal output end of the OR logic unit is connected with the signal input end of a D trigger D _0 of the output shaping unit module; if the first preset number of OR logic units is greater than OR equal to 2, one OR logic unit OR1 in the first preset number of OR logic units is used to perform an OR logic operation on the signals output by the remaining OR logic units and output the final signal as an output signal of the OR logic group module, and the signal output end of the OR logic unit OR1 is connected to the signal input end of the D flip-flop D _0 of the output shaping unit module.
Specifically, the output shaping unit module includes a D flip-flop D _0, a signal input terminal of the D flip-flop D _0 is connected to a signal output terminal of the or logic unit that outputs the final signal of the or logic group module, and a clock signal input terminal of the D flip-flop D _0 is connected to clock signal input terminals of the n-1D flip-flops of the pulse width transfer sequence.
Specifically, a reference clock signal Clk is input into an n-time pulse width expansion circuit through a clock signal input end of an n-1 stage D trigger of a pulse width transmission sequence, a signal to be expanded Fbk _ t is input into the n-time pulse width expansion circuit through a signal input end of an n-1 stage D trigger D _ n-1 of the pulse width transmission sequence, the signal to be expanded Fbk _ t is input into an n-1 stage delay unit of a delay sub-array with n-1 delay units of a delay array module, after delay processing is carried out through n-1 delay units, the delayed signal to be expanded QDf is output to a signal input end of a corresponding or logic unit by the 1 stage delay unit, the n-1 stage D trigger D _ n-1 outputs a signal to be expanded Qn-1 after pulse width transmission, and the signal to be expanded Qn-1 after pulse width transmission is output The signal output ends of n-1D triggers of the pulse width transmission sequence respectively output signals Qn-1, Qn-2.. Q2 and Q1 to be expanded after pulse width transmission, the signal Qn-1 to be expanded after pulse width transmission is output to the n-2 level delay unit of a group of delay subarrays with n-2 delay units of the delay array module, the signal Qn-1 to be expanded after pulse width transmission passes through the n-2 delay units and outputs a signal QDn-1 to be expanded after delay to the signal input end of a corresponding or logic unit, and the like, the signals Qn-1, Qn-2.. Q2 and Q1 to be expanded after pulse width transmission pass through the group of subarrays and output signals QDn-1, QDn-1 after delay, QDn-2.. QD2 outputs to a signal input end of a corresponding or logic unit, specifically, a signal Q1 to be expanded after pulse width transmission output by the 1 st-level D flip-flop D1 passes through 0 delay units and outputs a delayed signal Q1 to a signal input end of the corresponding or logic unit, a first preset number of or logic units perform or logic operation on n signals transmitted by the delay array module, output a final signal Fbk _ or to be expanded after the or logic operation to a D flip-flop D _0 of an output shaping unit module, and the D flip-flop D _0 shapes and outputs the signal Fbk _ or to be expanded after the or logic operation, and finally outputs a signal Fbk _ nt after n times of pulse width expansion.
The present invention further provides a pulse width expansion circuit, wherein the pulse width expansion circuit is formed by connecting m pulse width expansion circuits with n times, which have the same or different values, in series as in the foregoing embodiment shown in fig. 1, and if the pulse width expansion circuit is formed by connecting m pulse width expansion circuits with n times, which have the same or different values, in series, the pulse width expansion multiple of the pulse width expansion circuit is m pulse width expansion multiple of n timesThe sum of the pulse width expansion multiples of the pulse width expansion circuit minus n times the number m of the pulse width expansion circuit plus 1, i.e. the pulse width expansion multiple = (n)1+n2+n3+...+nm) -m +1, m being an integer greater than or equal to 2.
In an embodiment of the present invention, a 2-time pulse width expansion circuit is provided, as shown in fig. 2, the 2-time pulse width expansion circuit is composed of a pulse width transmission sequence module, a delay array module, an or logic group module, and an output shaping unit module; the pulse width transmission sequence module comprises 1D trigger D _1, the delay array module comprises 1 delay unit, the OR logic group module comprises an OR logic unit with double input ends, and the output shaping unit module comprises 1D trigger D _ 0.
Specifically, the reference clock signal Clk is input to the 2-time pulse width expansion circuit from the clock signal input end of the D flip-flop D _1 of the pulse width transfer sequence module, the clock signal input end of the D flip-flop D _1 of the pulse width transfer sequence module is connected to the clock signal input end of the D flip-flop D _0 of the output shaping unit module, the signal Fbk _ t to be expanded is input to the 2-time pulse width expansion circuit from the signal input end of the D flip-flop D _1 of the pulse width transfer sequence module, the signal Fbk _ t to be expanded is delayed by the delay unit of the delay module, the delay unit outputs the delayed signal QDf to be expanded to one of the signal input ends of the or logic units of the or logic group module, the signal output end of the D flip-flop D _1 of the pulse width transfer sequence module outputs the signal Q1 to the signal input end corresponding to the delay array, and outputs the zero-delay signal to the signal input end corresponding to the or, that is, the signal Q1 is the same as the zero-delayed signal QD1, the or logic unit of the two input ends outputs the signal Fbk _ or to be expanded, which is subjected to the or logic processing, to the signal input end of the D flip-flop D _0 of the output shaping unit module, and the D flip-flop D _0 outputs the signal Fbk _2t which is 2 times the pulse width expansion after the shaping processing.
In an embodiment of the present invention, a 3-time pulse width expansion circuit applied to a phase-locked loop is provided, as shown in fig. 3, the 3-time pulse width expansion circuit is composed of a pulse width transmission sequence module, a delay array module, an or logic group module, and an output shaping unit module; the pulse width transmission sequence module comprises 2D triggers D _1 and D _2, the delay array module comprises 3 groups of delay subarrays and 3 delay units, the OR logic group module comprises an OR logic unit with three input ends, and the output shaping unit module comprises 1D trigger D _ 0. Referring to fig. 4, the phase-locked loop PLL includes a phase frequency detector PFD, a charge pump CP, a low pass filter LPF, a voltage controlled oscillator VCO, a frequency divider N divider, and an N-fold pulse width expansion circuit, where the value of the pulse width expansion multiple N of the pulse width expansion circuit is 3 in this embodiment.
Specifically, when the phase-locked loop PLL operates, the voltage-controlled oscillator VCO generates a clock output signal fout, the clock output signal fout is divided by the frequency divider N divider to generate a feedback signal Fbk, the feedback signal Fbk is a signal Fbk _ t to be expanded, the signal Fbk _ nt to be expanded generates a signal Fbk _ nt with a pulse width N times after passing through the pulse width expanding circuit N times, the signal Fbk _ nt after the pulse width expansion is used as a new feedback signal to be input to the phase frequency detector PPL, the phase frequency detector PPL performs phase comparison between the feedback signal Fbk _ nt and the input reference signal fre and outputs a control signal with phase information to the charge pump CP, the control signal received by the charge pump CP converts a current to control and adjust the voltage of the low-pass filter LPF and adjusts the output clock frequency of the voltage-controlled oscillator VCO, and starts the next cycle modulation until the feedback signal Fbk _ nt and the reference signal Fref are in the same frequency, the whole phase-locked loop is in a stable state, the frequency of a VCO (voltage controlled oscillator) output clock signal fout is stable, and phase-locked loop output based on the n-time pulse width expansion circuit is completed.
Specifically, the waveforms of the node signals when the feedback signal Fbk _ t is input into the 3-time pulse width expansion circuit can be shown in fig. 5, when the frequency divider N divider in the phase-locked loop PLL completes one frequency division, the feedback signal Fbk outputs a high level, and the signal Fbk _ t to be expanded changes from a low level to a high level; before the first rising edge of the reference clock signal Clk comes, the signal to be expanded Fbk _ t is in a low level state, when the first rising edge of the reference clock signal Clk comes, the signal to be expanded Fbk _ t is changed from a low level to a high level at this time, but still is in a low level state, the signal to be expanded Q2 output by the 2 nd-stage D flip-flop D _2 after pulse width transmission is in a low level, and similarly, the signal to be expanded Q1 output by the 1 st-stage D flip-flop D _1 after pulse width transmission is in a low level; when the second rising edge of the reference clock signal Clk comes, the signal to be expanded Fbk _ t changes from high level to low level, but is still at high level, the signal to be expanded Q2 output by the 2 nd-stage D flip-flop D _2 after pulse width transmission changes from low level to high level, but still remains at low level when the second rising edge of the reference clock signal Clk comes, so the signal to be expanded Q1 output by the 1 st-stage D flip-flop D _1 after pulse width transmission still remains at low level; when the third rising edge of the reference clock signal Clk comes, the signal to be expanded Fbk _ t is at a low level, the signal to be expanded Q2 output by the 2 nd-stage D flip-flop D _2 after pulse width transmission changes from a high level to a low level but still at a high level, and the signal to be expanded Q1 output by the 1 st-stage D flip-flop D _1 after pulse width transmission changes from a low level to a high level but still at a low level; when the fourth rising edge of the reference clock signal Clk comes, the signal to be spread Fbk _ t is still at a low level, the signal to be spread Q2 output by the 2 nd-stage D flip-flop D _2 after pulse width transmission is at a low level, and the signal to be spread Q1 output by the 1 st-stage D flip-flop D _1 after pulse width transmission is changed from a high level to a low level. A signal Fbk _ t to be expanded generates a signal QDf with a delay of 2 × Δ t through a group of delay subarrays with two delay units in a delay array module, a signal Q2 to be expanded after pulse width transmission output by a 2 nd-stage D flip-flop D _2 generates a signal QD2 with a delay Δ t through a group of delay subarrays with one delay unit in a delay array module, a signal Q1 to be expanded after pulse width transmission output by a 1 st-stage D flip-flop D _1, a signal QDf with a delay of 2 × Δ t and a signal QD2 with a delay Δ t are respectively input into corresponding signal input ends of a three-input-end or logic unit, the three-input-end or logic unit performs or logic operation processing on input signals Q1, QDf and 2, and error signals are prevented from being generated by partial overlapping of signals of three signals Q1, QDf and QD 2; when the first rising edge of the reference clock signal Clk comes, the signal Fbk _ t to be expanded changes from low level to high level, due to the delay action of the delay array module, the signal Fbk _ or output by the or logic unit signal output end of the three input ends changes into high level at the time when the first rising edge of the reference clock signal is delayed by 2 × Δ t, the waveform of the signal Fbk _ or output by the or logic unit signal output end of the three input ends can be shown in fig. 5, the D flip-flop D _0 of the output shaping unit receives the signal Fbk _ or to be expanded, which is output by the or logic unit of the three input ends and is subjected to the or logic operation processing, and shapes and outputs the signal Fbk _ or, when the first rising edge of the reference clock signal Clk comes, the signal Fbk _ or output by the or logic unit signal output end of the three input ends is low level, and after the delay of 2 × Δ t, the signal Fbk _ or output by the or logic unit signal output end of the three input ends changes from low level to high level, when the second rising edge of the reference clock signal Clk comes, the output signal Fbk _ or of the or logic cell signal output terminal of the three input terminals is kept at the high level, the shaped output signal Fbk _3t is changed from the low level to the high level, when the third rising edge of the reference clock signal Clk comes, the output signal Fbk _ or of the or logic cell signal output terminal of the three input terminals is kept at the high level, the shaped output signal Fbk _3t is kept at the high level, when the fourth rising edge of the reference clock signal Clk comes, the output signal Fbk _ or of the or logic cell signal output terminal of the three input terminals is changed from the high level to the low level but still at the high level, the shaped output signal Fbk _3t is kept at the high level, when the fifth rising edge of the reference clock signal Clk comes, the output signal Fbk _ or of the three input terminals is kept at the low level, the shaped output signal Fbk _3t is changed from the high level to the low level, specific waveform variations can be seen in fig. 5.
The terms "first", "second", "third", and the like in this embodiment are used for convenience of distinguishing the order of the related features, and cannot be understood as indicating or implying relative importance or the number of technical features.
In an embodiment of the present invention, a 4-time pulse width expansion circuit is provided, as shown in fig. 6, the 4-time pulse width expansion circuit includes a pulse width transmission sequence module, a delay array module, or a logic group module, and an output shaping unit module; the pulse width transmission sequence module comprises 3D triggers D _1, the delay array module comprises 4 groups of delay sub-arrays, the 4 groups of delay sub-arrays respectively comprise 3, 2, 1 and 0 delay units, the OR logic group module comprises an OR logic unit with four input ends, and the output shaping unit module comprises 1D trigger D _ 0.
In one embodiment of the present invention, a pulse width expansion circuit is provided, where the pulse width expansion circuit is formed by connecting two n-fold pulse width expansion circuits in series in the above embodiment; the n values of the two n-time pulse width expansion circuits can be the same or different, and the pulse width expansion multiple of the pulse width expansion circuit is equal to the pulse width expansion multiple and the value of the two n-time pulse width expansion circuits is reduced by one.
Further, the pulse width expansion circuit may be formed by connecting m n-times pulse width expansion circuits in series in the above embodiment; the n values of the m n-times pulse width expansion circuits may be the same or different, the pulse width expansion multiple of the pulse width expansion circuit is equal to the sum of the pulse width expansion multiple of the m n-times pulse width expansion circuits minus m plus one, where n is an integer greater than or equal to 2, and m is an integer greater than or equal to 2.
Finally, it should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and that several modifications and alterations can be made by those skilled in the art without departing from the principle of the present invention, and these modifications and alterations should also be construed as the protection scope of the present invention.

Claims (9)

1. An n-fold pulse width expansion circuit, the n-fold pulse width expansion circuit comprising: the pulse width transmission device comprises a pulse width transmission sequence module, a delay array module, an OR logic group module and an output shaping unit module;
the pulse width transmission sequence module comprises n-1 cascaded D triggers; the delay array module comprises a delay unit; the OR logic group module comprises a preset number of OR logic units; the output shaping unit module comprises a D flip-flop (D _ 0);
the input reference clock signal (Clk) is connected with the clock signal input end of an n-1 level D trigger (D _ n-1) of a pulse width transmission sequence module, the signal input ends of n-1 cascaded D triggers of the pulse width transmission sequence module are connected with the matched signal input end of a delay array module, the signal output end of a first level D trigger of the pulse width transmission sequence module is connected with the matched signal input end of the delay array module, the signal output end of the delay array module is connected with the signal input end of an OR logic group module, or the signal output end of the logic group module is connected with the signal input end of a D trigger (D _ 0) of an output shaping unit module; n is an integer greater than or equal to 2.
2. The n-fold pulse width expansion circuit of claim 1, wherein the pulse width transmission sequence comprises n-1 cascaded D flip-flops, and a signal output terminal of the n-1 st-stage D flip-flop (D _ n-1) is connected to a signal input terminal of the n-2 nd-stage D flip-flop (D _ n-2); the signal input end of the D flip-flop with the highest series number is used for inputting a signal (Fbk _ t) to be expanded.
3. The n-fold pulse width expansion circuit according to claim 2, wherein the delay array module includes n signal input terminals and n signal output terminals, the signal output terminals of the n-1 cascaded D flip-flops of the pulse width transmission sequence module and the signal output terminal of the first-stage D flip-flop are respectively connected to the signal input terminals matched with the delay array module, there is a group of delay sub-arrays connected between the n signal input terminals and the corresponding n signal output terminals thereof to form n groups of delay sub-arrays, the n signal input terminals of the delay array module are respectively configured as the signal input terminals of the corresponding group of delay sub-arrays, and the n signal output terminals of the delay array module are respectively configured as the signal output terminals of the corresponding group of delay sub-arrays; the signal output end of the first-stage D trigger (D _ 1) is connected with the signal input ends of the corresponding delay sub-arrays, and the group of delay sub-arrays connected with the signal output end of the first-stage D trigger (D _ 1) comprises 0 delay units;
the signal input end of the (n-1) th-level D trigger (D _ n-1) is connected with the signal input ends of the corresponding delay sub-arrays, and the group of delay sub-arrays connected with the signal input end of the (n-1) th-level D trigger (D _ n-1) comprises n-1 cascaded delay units;
in the group of delay subarrays, the signal output end of the (n-1) th-level delay unit is connected with the signal input end of the (n-2) th-level delay unit, the signal input end of the delay unit with the highest level number is connected with the signal input end of the group of delay subarrays, and the signal output end of the delay unit with the lowest level number is connected with the signal output end of the group of delay subarrays.
4. The n-fold pulse width expansion circuit of claim 3, wherein the OR logic bank module comprises a first preset number of OR logic cells; the OR logic unit comprises a second preset number of signal input ends;
the n signal output ends of the delay array module are respectively and correspondingly connected with the signal input ends of a first preset number of OR logic units matched in the OR logic group module, so that the n signal output ends of the delay array module are respectively and correspondingly connected with the matched signal input ends of the OR logic group module;
the first preset number of OR logic units perform OR logic operation on the n signals input by the delay array module and output one signal as an output signal of the OR logic group module.
5. The n-fold pulse width expansion circuit according to claim 4, wherein if the first preset number of OR logic cells is equal to 1, the signal output terminal of the OR logic cell is connected to the signal input terminal of the D flip-flop (D _ 0) of the output shaping unit module;
if the first preset number of the OR logic units is greater than OR equal to 2, one OR logic unit (OR 1) in the OR logic units with the first preset number is used for carrying out OR logic operation on signals output by the rest OR logic units and outputting a final signal as an output signal of the OR logic group module, and the signal output end of the OR logic unit (OR 1) is connected with the signal input end of the D flip-flop (D _ 0) of the output shaping unit module.
6. The n-fold pulse width expansion circuit according to claim 4, wherein the connection of the signal output terminal of the OR logic group module to the signal input terminal of the D flip-flop (D _ 0) of the output shaping unit module means that the signal output terminal of the OR logic unit from which the OR logic group module outputs the final signal is connected to the signal input terminal of the D flip-flop (D _ 0) of the output shaping unit module.
7. The n-fold pulse width expansion circuit of claim 6, wherein the output shaping unit comprises a single D flip-flop (D)0) D flip-flop (D)0) Is connected with the clock signal input end of the n-1D triggers of the pulse width transmission sequence.
8. A pulse width spreading circuit, characterized in that the pulse width spreading circuit is composed of m n-fold pulse width spreading circuits of the same or different values, which are connected in series, according to any one of claims 1 to 7, so that the pulse width spreading multiple of the pulse width spreading circuit is the sum of the m pulse width spreading multiple of the n-fold pulse width spreading circuit according to any one of claims 1 to 7, minus m plus one, and m is an integer greater than or equal to 2.
9. A phase-locked loop system using a pulse width expansion circuit, comprising: -a Phase Frequency Detector (PFD), a charge pump module (CP), a Low Pass Filter (LPF), a Voltage Controlled Oscillator (VCO), a frequency divider (N divider) and an N-fold pulse width extension circuit module (fbk _ pwe) according to claims 1 to 8; the signal output end of the Phase Frequency Detector (PFD) is connected with the signal input end of the charge pump module (CP), the signal output end of the charge pump module (CP) is connected with the signal input end of the low-pass filter (LPF), the signal output end of the low-pass filter (LPF) is connected with the signal input end of the Voltage Controlled Oscillator (VCO), the signal output end of the Voltage Controlled Oscillator (VCO) is connected with the signal input end of the frequency divider (N divider), the signal output end of the frequency divider (N divider) is connected with the signal input end of the pulse width expansion circuit module (fbk _ pwe), the signal output end of the pulse width expansion circuit module (fbk _ pwe) is connected with the feedback signal input end of the Phase Frequency Detector (PFD), and a reference signal is input from the signal input end of the phase frequency detector.
CN202011232531.5A 2020-11-06 2020-11-06 N-time pulse width expansion circuit and pulse width expanded phase-locked loop system Pending CN112202424A (en)

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