CN204144239U - 一种等面积大功率裸芯片的叠层装配结构 - Google Patents

一种等面积大功率裸芯片的叠层装配结构 Download PDF

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CN204144239U
CN204144239U CN201420500232.9U CN201420500232U CN204144239U CN 204144239 U CN204144239 U CN 204144239U CN 201420500232 U CN201420500232 U CN 201420500232U CN 204144239 U CN204144239 U CN 204144239U
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刘均东
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Wuxi Huace Electronic System Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本实用新型公开了一种等面积大功率裸芯片的叠层装配结构，包括电路基板、底层芯片、垫片和上层芯片；底层芯片的背面通过导电胶与电路基板胶接，上层芯片的背面通过焊料与垫片焊接，垫片的另一面通过绝缘胶与底层芯片的正面胶接，底层芯片的焊盘与电路基板的焊盘、上层芯片的焊盘与电路基板的焊盘之间分别连接有键合金丝。本实用新型无需专门定制叠层芯片，可根据普通裸芯片的焊盘分布情况制作垫片，一方面实现了等面积裸芯片的叠层装配，利于实现小型化，另一方面通过增加导热良好的垫片也满足了大功率芯片的散热需求。

Description

一种等面积大功率裸芯片的叠层装配结构
技术领域
本实用新型属于电子装配领域，特别涉及一种等面积大功率裸芯片的叠层装配结构。
背景技术
随着便携式电子***复杂性的增加，对VLSI集成电路用的轻型及小型封装工艺技术提出了越来越高的要求，同样，许多航空和军事应用也正在朝该方向发展，为满足这些要求，在X、Y平面内的二维封装基础上，将裸芯片沿Z轴叠层在一起，这样，在小型化方面就取得了极大的改进。
当前实现芯片叠层的方式大致有如下几种，如叠带IC间的***互连、焊接边缘导带、立方体表面上的薄膜导带、折叠式柔性电路以及丝焊叠层芯片。上述前四种结构由于需要借助专用设备、操作复杂等原因使其在实际应用中存在灵活性差、适用范围有限等问题，丝焊叠层芯片结构是目前应用比较普遍的结构，即母芯片充当子芯片的基板，芯片焊盘与电路基板通过引线键合方式互连。该结构的常见特点是：a)母芯片面积大于子芯片，子芯片可以直接胶接在母芯片的无焊盘区域；b)芯片焊盘交错排布，如芯片为长方体，下层芯片焊盘分布在两长边边缘，上层芯片焊盘分布在两短边边缘，上下两层芯片垂直交叉叠层，该种芯片通常需要定制；c)直接使用绝缘胶实现上下两层芯片的结构互连，适用于对散热要求不高的芯片。而当需要对面积相等、散热要求高的裸芯片进行叠层装配时，上述结构的局限性便凸显出来。
实用新型内容
鉴于传统叠层装配结构的局限性，申请人经过研究改进，提供一种适用范围广、易于实现的等面积大功率裸芯片的叠层装配结构。
本实用新型的技术方案如下：
一种等面积大功率裸芯片的叠层装配结构，包括电路基板、底层芯片、垫片和上层芯片；底层芯片的背面通过导电胶与电路基板胶接，上层芯片的背面通过焊料与垫片焊接，垫片的另一面通过绝缘胶与底层芯片的正面胶接，底层芯片的焊盘与电路基板的焊盘、上层芯片的焊盘与电路基板的焊盘之间分别连接有键合金丝。
其进一步的技术方案为：所述底层芯片与上层芯片面积相等。
其进一步的技术方案为：所述垫片为绝缘材料。
其进一步的技术方案为：所述键合金丝的直径为25μm。
本实用新型的有益技术效果是：
本实用新型的装配结构采用了比较经济的方式实现了普通等面积裸芯片的叠层装配，同时解决了大功率芯片的散热问题。解决了传统芯片叠层装配方法操作复杂、适用范围窄的缺点。并且本实用新型的装配结构在整个装配过程中所涉及的装配技术均为成熟技术，易于实现，具有适用范围广，操作简单的优点。
附图说明
图1是本实用新型的整体结构图。
附图标记说明：1、电路基板；2、导电胶；3、底层芯片；4、绝缘胶；5、垫片；6、焊料；7、上层芯片；8、键合金丝。
具体实施方式
下面结合附图对本实用新型的具体实施方式做进一步说明。
如图1所示，本实用新型包括电路基板1、导电胶2、底层芯片3、绝缘胶4、垫片5、焊料6、上层芯片7和键合金丝8。底层芯片3的背面通过导电胶2与电路基板1胶接，上层芯片7的背面通过焊料6与垫片5焊接，垫片5的另一面通过绝缘胶4与底层芯片3的正面胶接。底层芯片3与上层芯片7面积相等。垫片5是绝缘材料并具有良好的散热特性；垫片5的底面形状应是能够避开底层芯片3表面焊盘，不影响引线键合；垫片5的顶面形状与上层芯片7外形相同，对上层芯片7起到支撑作用，避免上层芯片7引线键合时劈刀力对芯片造成损伤。底层芯片3的焊盘与电路基板1的焊盘、上层芯片7的焊盘与电路基板1的焊盘之间分别连接有键合金丝8。键合金丝8的直径为25μm。
本实用新型的装配步骤如下：
1)使用导电胶2将底层芯片3胶接至电路基板1，并加热固化，固化条件为120℃，45min，实现电气与结构互连。
2)使用25μm的键合金丝8键合互连底层芯片3的焊盘与电路基板1的焊盘。
3)使用焊料6将上层芯片7焊接至垫片5使之成为一个独立的芯片部件，并加热固化，固化条件为120℃，45min。
4)使用DELA9218绝缘胶4将步骤3)所述的芯片部件胶接至底层芯片3，并加热固化，固化条件为100℃，15min。
5)采用热压超声键合工艺，使用25μm的键合金丝8键合互连上层芯片7的焊盘与电路基板1的焊盘。
以上所述的仅是本实用新型的优选实施方式，本实用新型不限于以上实施例。可以理解，本领域技术人员在不脱离本实用新型的精神和构思的前提下直接导出或联想到的其他改进和变化，均应认为包含在本实用新型的保护范围之内。

Claims (4)

1.一种等面积大功率裸芯片的叠层装配结构，其特征在于：包括电路基板(1)、底层芯片(3)、垫片(5)和上层芯片(7)；底层芯片(3)的背面通过导电胶(2)与电路基板(1)胶接，上层芯片(7)的背面通过焊料(6)与垫片(5)焊接，垫片(5)的另一面通过绝缘胶(4)与底层芯片(3)的正面胶接，底层芯片(3)的焊盘与电路基板(1)的焊盘、上层芯片(7)的焊盘与电路基板(1)的焊盘之间分别连接有键合金丝(8)。
2.根据权利要求1所述等面积大功率裸芯片的叠层装配结构，其特征在于：所述底层芯片(3)与上层芯片(7)面积相等。
3.根据权利要求1所述等面积大功率裸芯片的叠层装配结构，其特征在于：所述垫片(5)为绝缘材料。
4.根据权利要求1所述等面积大功率裸芯片的叠层装配结构，其特征在于：所述键合金丝(8)的直径为25μm。
CN201420500232.9U 2014-09-01 2014-09-01 一种等面积大功率裸芯片的叠层装配结构 Expired - Fee Related CN204144239U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108323009A (zh) * 2018-01-11 2018-07-24 南昌黑鲨科技有限公司 器件结构及器件布局
CN110132453A (zh) * 2019-05-28 2019-08-16 无锡莱顿电子有限公司 一种压力传感器键合方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108323009A (zh) * 2018-01-11 2018-07-24 南昌黑鲨科技有限公司 器件结构及器件布局
CN110132453A (zh) * 2019-05-28 2019-08-16 无锡莱顿电子有限公司 一种压力传感器键合方法

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